阅读说明：本技术 一种改善亚阈值摆幅的纵向隧穿场效应晶体管 (Longitudinal tunneling field effect transistor for improving sub-threshold swing amplitude ) 是由 王向展 陈玉翔 刘洋 于奇 于 2019-10-23 设计创作，主要内容包括：本发明涉及半导体技术。本发明解决了现有异质结TFET器件中,特别是采用SiGe窄禁带材料提高TFET开态电流时,由于锗硅材料与硅材料能带失配所导致的两个隧穿区先后发生隧穿,造成器件亚阈值特性变差的缺点,提供了一种改善亚阈值摆幅的纵向隧穿场效应晶体管,其技术方案可概括为：一种改善亚阈值摆幅的纵向隧穿场效应晶体管,包括源区、本征区、漏区、外延区、栅极及栅极侧墙,所述栅极包括栅氧化层及金属栅,所述外延区采用窄禁带材料,外延区的掺杂浓度在外延区内由与源区相接触界面向与栅氧化层相接触界面呈现由高到低的渐变。本发明的有益效果是,改善亚阈值特性,适用于纵向隧穿场效应晶体管。(The present invention relates to semiconductor technology. The invention solves the defect that in the prior heterojunction TFET device, particularly when a SiGe narrow band gap material is adopted to improve the TFET on-state current, two tunneling regions are sequentially tunneled due to the mismatch of energy bands of a germanium-silicon material and a silicon material, so that the subthreshold characteristic of the device is poor, and provides a longitudinal tunneling field effect transistor for improving the subthreshold swing, wherein the technical scheme can be summarized as follows: a longitudinal tunneling field effect transistor for improving subthreshold swing comprises a source region, an intrinsic region, a drain region, an epitaxial region, a grid and a grid side wall, wherein the grid comprises a grid oxide layer and a metal grid, the epitaxial region is made of narrow forbidden band materials, and the doping concentration of the epitaxial region is gradually changed from high to low from a contact interface with the source region to a contact interface with the grid oxide layer in the epitaxial region. The invention has the beneficial effects of improving the sub-threshold characteristic and being suitable for the longitudinal tunneling field effect transistor.)

1. A longitudinal tunneling field effect transistor for improving subthreshold swing comprises a source region, an intrinsic region, a drain region, an epitaxial region, a grid electrode and grid electrode side walls, wherein the grid electrode comprises a grid oxide layer and a metal grid, the source region and the drain region are respectively arranged on two opposite sides of the intrinsic region and are respectively contacted with two sides of the intrinsic region, the epitaxial region is arranged between the grid electrode and the grid electrode side walls and the intrinsic region and the source region and at least covers a part of the intrinsic region and a part of the source region, a grid oxide layer is arranged between the epitaxial region and the metal grid and is respectively contacted with the epitaxial region and the metal grid, the grid electrode side walls are arranged on one side of the metal grid close to the drain region and are contacted with the metal grid and one side of the grid oxide layer, the metal grid and the grid oxide layer at least correspond to a part of the source region covered with the epitaxial region, and the, the epitaxial region is made of narrow forbidden band materials, and the doping concentration of the epitaxial region is gradually changed from high to low from a contact interface with the source region to a contact interface with the gate oxide layer in the epitaxial region.

2. The tunneling fet with improved subthreshold swing according to claim 1, wherein the doping concentration of the epi region is gradually changed from high to low in the epi region from the contact interface with the source region to the contact interface with the gate oxide layer, and the gradual change is gaussian distribution or linear distribution or residual error distribution.

3. The vertical tunneling field effect transistor with improved sub-threshold swing according to claim 1, further comprising a substrate disposed on one side of the intrinsic region and the source region not covering the epitaxial region and one side corresponding to the drain region, and contacting one side of the intrinsic region and the source region not covering the epitaxial region and one side corresponding to the drain region; the substrate may be a semiconductor substrate using conventional silicon or an SOI substrate.

4. The TFET of claim 3, applied to a vertical heterojunction FinFET.

5. The fet of claim 1, wherein two of the gate and the epi region respectively cover above and below at least a portion of the intrinsic region and at least a portion of the source region, and are opposite to each other.

6. The tffet of claim 1, wherein the narrow bandgap material of the epitaxial region is a III-V semiconductor material, and comprises at least SiGe or InAs; when SiGe is used, the molar composition of the Ge material is greater than 0 and less than or equal to 0.3.

7. The mtj of claim 1, wherein the epi region has a thickness of 2nm or more and 10nm or less.

8. The mtj (longitudinal tunneling field effect transistor) according to claim 1, wherein when the mtj is an N-type longitudinal tunneling field effect transistor, the source region is heavily P-doped and the drain region is heavily N-doped; when the tunneling field effect transistor is a P-type longitudinal tunneling field effect transistor, the source region is heavily doped in an N type, and the drain region is heavily doped in a P type; the doping concentration of the source region and the drain region is more than or equal to 1 multiplied by 10¹⁸cm^-3And is not more than 1 x 10²⁰cm^-3And the doping concentration of the source region is greater than that of the drain region.

9. The FET of claim 8, wherein the doping concentration of the epitaxial region at the interface with the source region is 1 x 10 or more¹⁷cm^-3And is not more than 1 x 10²⁰cm^-3The doping concentration of the epitaxial region at the contact interface with the gate oxide layer is 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3。

10. The improved subthreshold swing TFET of claim 1, 2, 3, 4, 5, 6, 7, 8 or 9 wherein the intrinsic region is lightly doped N-type or P-type single crystal silicon; the light doping is doping concentration of 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3(ii) a The width of the intrinsic region is more than or equal to 15nm and less than or equal to 25 nm; the gate oxide layer is made of a high-K dielectric material, and the relative dielectric constant of the gate oxide layer is greater than 20; the grid side wall can adopt SiO₂Or Si₃N₄Or a high-K dielectric material with a width not greater than 20 nm; when the transistor is an N-type longitudinal tunneling field effect transistor, the work function of the metal gate is more than or equal to 3.6eV and less than or equal to 4.25eV, and when the transistor is a P-type longitudinal tunneling field effect transistor, the work function of the metal gate is more than or equal to 4.7eV and less than or equal to 5.5 eV.

Technical Field

The present invention relates to semiconductor technology, and more particularly to a Tunneling Field Effect Transistor (TFET).

Background

Along with the continuous reduction of the characteristic size of the traditional MOSFET device, the chip integration level is gradually improved, the short channel effect of the device becomes more and more obvious, the leakage current is obviously increased when the device is turned off, the power consumption problem is more and more serious, and the further improvement of the chip integration level is not facilitated. The sub-threshold swing of the traditional MOSFET at room temperature is higher than 60mV/dec due to the carrier drift diffusion working principle, so that the off-state current is higher; the subthreshold slope of the Tunneling Field Effect Transistor (TFET) based on the quantum tunneling effect can break through the theoretical limit of subthreshold swing of an MOSFET device, and the TFET has extremely low off-state leakage current and low power consumption, and is very suitable for application of a low-power consumption super-large-scale integrated circuit. In addition, the silicon-based TFET has strong compatibility with the common CMOS process, and the manufacturing cost is favorably reduced.

The nature of the tunneling field effect transistor is a gate voltage controlled P-I-N junction. Similar to the MOSFET device, the TFET device is also composed of electrodes such as a gate, a source, and a drain, except that the channel of the MOSFET device refers to an inversion layer under the gate, and the channel of the TFET device refers to a tunneling region under the gate. According to the relationship between the tunneling direction and the gate electric field, two tunneling field effect transistors can be classified: when the tunneling direction is vertical to the gate field direction, the tunneling field effect transistor is a transverse TFET device; when the tunneling direction is parallel to the gate field direction, the tunneling field effect transistor is a longitudinal TFET device.

For the lateral tunneling TFET structure, the gate can only control the tunneling of the interface surface area of the source region and the intrinsic region, and the small area of the tunneling region results in no large on-state current. And the area of a carrier tunneling region of the longitudinal tunneling TFET is in direct proportion to the area of the gate covering the source region/the intrinsic region, the tunneling area is much larger than that of transverse tunneling, and the driving current of the device is higher. However, the current density of the TFET device is usually about 2 to 3 orders of magnitude lower than that of the MOSFET due to the limitation of the tunneling area and the tunneling probability, and the practical application of the TFET device is limited.

Aiming at the problems that the traditional TFET device is small in on-state current, the subthreshold characteristic needs to be improved and the like, a plurality of solutions are provided: 1. reducing an equivalent gate oxide thickness (EOT); 2. using narrow bandgap materials instead of conventional silicon; 3. the tunneling probability is increased by enhancing the electric field. Carrier tunneling to a gate dielectric occurs when the thickness of the equivalent gate oxide layer is continuously reduced, and gate leakage current is increased, so that extra high-K dielectric is needed to ensure the thickness of the gate dielectric and increase the electric field intensity of a tunneling region; the narrow forbidden band material can be used in one or more of a source region, a drain region, an epitaxial region or an intrinsic region, but the narrow forbidden band material is directly used for constructing the TFET device, so that the high SRH (Shockley-Read-Hall, an indirect composite model of a single composite center) generation rate of the device in a turn-off state can be caused, the leakage current of the device is increased, and the low power consumption is not facilitated.

Meanwhile, in a heterojunction TFET formed by some narrow-bandgap materials and silicon materials, energy band mismatch can be generated on the contact surface of the materials due to the difference between the electron affinity energy and the forbidden band width of the two materials. For example, a SiGe/Si heterojunction formed by a SiGe low-doped epitaxial region (i.e., a tunneling region, a channel region) and a Si source region (heavily doped) has a substantially flush conduction band position but a significantly different valence band position, and thus a valence band mismatch is formed at the SiGe/Si interface. This does not present a problem for P-type TFETs, but if used in N-type TFETs, it may cause the current in the transfer characteristic curve of the device to rise twice, which in turn affects the characteristics of the device such as on-state current and sub-threshold swing. Therefore, N-type TFETs typically apply SiGe material to the heavily doped source region and Si material to the structure of the lowly doped epitaxial region (i.e., tunneling region, channel region), i.e., the used area of the SiGe material is changed relative to P-type TFETs to avoid the influence of valence band mismatch. In addition, after the SiGe use region in the conventional N-type TFET is changed, the energy band of the tunneling region is relatively widened, which is not favorable for increasing the on-state current of the device. In order to solve the problem that the performance of the device is affected by the mismatch of the energy band, foreign researchers have formed the mismatch of the conduction band instead of the valence band by adjusting the energy band structure by using a SiGe material with a high Ge component (for example, the Ge molar component is greater than 0.5) and using other narrow bandgap materials (for example, InAs/Si, etc.), so as to achieve the purpose of improving the electrical characteristics of the device. However, heterojunctions with conduction band mismatch are not favorable for P-type TFETs, although they are favorable for N-type TFETs. The above-mentioned heterojunction TFET having conduction band mismatch heterojunction or valence band mismatch causes structural difference due to different regions using narrow bandgap materials for N-type and P-type devices, and when integrating the N-type TFET and the P-type TFET to form a complementary structure similar to CMOS, the process steps are complicated, and it is difficult to complete NMOS and PMOS with the same device structure as CMOS.

Disclosure of Invention

The invention aims to solve the problem that in the prior heterojunction TFET device, particularly when a SiGe narrow band gap material is adopted to improve the TFET on-state current, tunneling occurs successively in two tunneling regions due to band mismatch of a germanium-silicon material and a silicon material, so that the subthreshold characteristic of the device is poor, and provides a longitudinal tunneling field effect transistor for improving the subthreshold swing.

The invention solves the technical problem, adopts the technical proposal that a longitudinal tunneling field effect transistor for improving the subthreshold swing comprises a source region, an intrinsic region, a drain region, an epitaxial region, a grid electrode and grid electrode side walls, wherein the grid electrode comprises a grid oxide layer and a metal grid, the source region and the drain region are respectively arranged at two opposite sides of the intrinsic region and are respectively contacted with two sides of the intrinsic region, the epitaxial region is arranged between the grid electrode and the grid electrode side walls and the intrinsic region and between the grid electrode side walls and the source region and at least covers a part of the intrinsic region and a part of the source region, the grid oxide layer is arranged between the epitaxial region and the metal grid and is respectively contacted with the epitaxial region and the metal grid, the grid electrode side walls are arranged at least at one side of the metal grid close to the drain region and are contacted with the metal grid and one side of the grid oxide layer, the metal grid electrode and the grid oxide layer at least correspond to a part of the, the epitaxial region is made of narrow forbidden band materials, and the doping concentration of the epitaxial region is gradually changed from high to low from a contact interface with the source region to a contact interface with the gate oxide layer in the epitaxial region.

Specifically, to explain the above gradual change, the doping concentration of the epitaxial region gradually changes from high to low in the epitaxial region from the contact interface with the source region to the contact interface with the gate oxide layer, and the gradual change may be gaussian distribution, linear distribution, or residual error distribution.

Further, in order to provide a specific structure of the vertical tunneling field effect transistor for improving the sub-threshold swing amplitude, the vertical tunneling field effect transistor may further include a substrate, where the substrate is disposed on one side of the intrinsic region and the source region not covering the epitaxial region and one side corresponding to the drain region, and is in contact with one side of the intrinsic region and the source region not covering the epitaxial region and one side corresponding to the drain region. The vertical tunneling field effect transistor can be applied to a vertical heterojunction fin type tunneling field effect transistor.

Specifically, to explain the substrate, the substrate may be a semiconductor substrate using conventional silicon or an SOI substrate.

Still further, in order to provide a specific structure of the vertical tunneling field effect transistor for improving the subthreshold swing, the specific structure can be applied to a double-gate structure, and two gates and two epitaxial regions are respectively covered above and below at least one part of the intrinsic region and at least one part of the source region and correspond to each other.

Specifically, for explaining the narrow bandgap material, the narrow bandgap material adopted by the epitaxial region is a III-V semiconductor material, such as SiGe or InAs; when SiGe is adopted, the molar component of the Ge material is more than 0 and less than or equal to 0.3; the molar composition of Ge can be increased to reduce the forbidden bandwidth of the material in the epitaxial region, thereby reducing the tunneling distance and increasing the tunneling current of the device.

Still further, in order to provide a preferable thickness range of the epitaxial region, the thickness of the epitaxial region is greater than or equal to 2nm and less than or equal to 10 nm. The above range is adopted because the epitaxial region has a thickness of less than 2nm and is susceptible to the FIBL (edge-induced barrier lowering effect), and when the thickness is more than 10nm, the control effect of the gate on the tunneling region is weakened and the tunneling current is reduced.

Specifically, since the vertical tunneling field effect transistor may be an N-type vertical tunneling field effect transistor or a P-type vertical tunneling field effect transistor, the doping of the source region and the drain region thereof are respectively: when the tunneling field effect transistor is an N-type longitudinal tunneling field effect transistor, the source region is heavily doped in a P type mode, and the drain region is heavily doped in an N type mode; when the tunnel junction transistor is a P-type longitudinal tunneling field effect transistor, the source region is N-type heavy doping, and the drain region is P-typeHeavily doping; the doping concentration of the source region and the drain region is more than or equal to 1 multiplied by 10¹⁸cm^-3And is not more than 1 x 10²⁰cm^-3And the doping concentration of the source region is greater than that of the drain region so as to inhibit the bipolar conduction characteristic of the TFET.

Still further, in order to provide a better doping concentration range of the epitaxial region, the doping concentration of the epitaxial region at the contact interface with the source region is greater than or equal to 1 × 10¹⁷cm^-3And is not more than 1 x 10²⁰cm^-3The doping concentration of the epitaxial region at the contact interface with the gate oxide layer is 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3。

Specifically, in order to provide a parameter range adopted by other regions, the intrinsic region is lightly doped N-type monocrystalline silicon or P-type monocrystalline silicon; the light doping is doping concentration of 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3(ii) a The width of the intrinsic region is more than or equal to 15nm and less than or equal to 25 nm; the gate oxide layer is made of a high-K dielectric material, and the relative dielectric constant of the gate oxide layer is greater than 20; the grid side wall can adopt SiO₂Or Si₃N₄Or a high-K dielectric material with a width not greater than 20 nm; when the transistor is an N-type longitudinal tunneling field effect transistor, the work function of the metal gate is more than or equal to 3.6eV and less than or equal to 4.25eV, and when the transistor is a P-type longitudinal tunneling field effect transistor, the work function of the metal gate is more than or equal to 4.7eV and less than or equal to 5.5 eV.

The invention has the beneficial effects that through the longitudinal tunneling field effect transistor for improving the subthreshold swing, the difference between the device and the existing TFET device is mainly that a narrow forbidden band material is adopted in an epitaxial region, the doping concentration of the epitaxial region is gradually changed from high to low from a contact interface with a source region to a contact interface with a gate oxide layer in the epitaxial region, taking an N-type longitudinal tunneling field effect transistor as an example, a TFET off-state leakage current path is mainly present in a transverse P-I-N junction, when a substrate or a source drain region adopts a narrow forbidden band semiconductor material, the introduction of the large-area narrow forbidden band material can cause the increase of SRH generated current, and the leakage current can be increased; in the invention, only the epitaxial region is made of narrow forbidden band material, and the Ge component of the SiGe material is lower, so that the off-state characteristic is not greatly influenced; the epitaxial region adopts gradual doping, and the tunneling region under low gate voltage is adjusted by improving the doping concentration near the source region in the epitaxial region, so that the sub-threshold characteristic is improved; meanwhile, the tunneling distance of the lower band is shortened, and the on-state current is favorably improved; the gradual doping can be formed by limited source diffusion based on a heavily doped source region or by constant surface source diffusion based on diffusion time and diffusion temperature, so that the requirement that the doping concentration of the traditional TFET device is suddenly changed on the surfaces of an epitaxial region and a source region is relaxed, and the process manufacturing difficulty is reduced. In addition, the N-type TFET and the P-type TFET can adopt the same device structure, only the doping type of the corresponding region needs to be changed, complementary TFETs similar to CMOS are conveniently formed, the flexibility of circuit design is enhanced, and meanwhile, the complexity of process realization is reduced.

Drawings

Fig. 1 is a cross-sectional view of a vertical tunneling field effect transistor with improved subthreshold swing according to embodiment 1 or 2 of the present invention;

fig. 2 to 8 are schematic diagrams illustrating a method for manufacturing a vertical tunneling field effect transistor with an improved sub-threshold swing according to embodiment 1 of the present invention;

fig. 9 and 10 are schematic energy band diagrams illustrating a current hump phenomenon occurring in a conventional N-type SiGe epitaxial TFET;

FIG. 11 is a schematic diagram of an energy band of a vertical tunneling field effect transistor with an improved sub-threshold swing at a low gate voltage when the epitaxial region is SiGe and is doped in a graded manner according to the present invention;

figure 12 is a schematic current characteristic comparison plot for a conventional silicon-based TFET, a SiGe uniformly doped epitaxial region, and a graded doped epitaxial region TFET of the present invention;

fig. 13 is a schematic energy band diagram of N-type and P-type TFETs when the material of the epitaxial region is InAs in embodiment 2 of the present invention;

fig. 14 is a cross-sectional view of an epitaxial region graded doped complementary TFET in embodiment 3 of the invention;

fig. 15 is a cross-sectional view of an epitaxial region graded doped TFET with SOI substrate according to embodiment 4 of the present invention;

fig. 16 is a cross-sectional view of an epitaxial region graded doped dual gate TFET in embodiment 5 of the invention;

fig. 17 is a schematic structural view of a graded-doping fin TFET in an epitaxial region according to embodiment 6 of the present invention;

the semiconductor device comprises a semiconductor substrate 1, a source region 2, an intrinsic region 3, a drain region 4, an epitaxial region 5, a gate oxide 6, a metal gate 7, a gate sidewall 8, shallow trench isolation 9, an epitaxial layer 10, a passivation layer 11, metal tungsten 12 and a buried oxide 13.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

The invention relates to a longitudinal tunneling field effect transistor for improving subthreshold swing amplitude, which comprises a source region, an intrinsic region, a drain region, an epitaxial region, a grid electrode and grid electrode side walls, wherein the grid electrode comprises a grid oxide layer and a metal grid, the source region and the drain region are respectively arranged at two opposite sides of the intrinsic region and are respectively contacted with two sides of the intrinsic region, the epitaxial region is arranged between the grid electrode and the grid electrode side walls, the grid electrode side walls are respectively contacted with the epitaxial region and the metal grid, the grid electrode side walls are arranged at least at one side of the metal grid close to the drain region and are contacted with one side of the metal grid and one side of the grid oxide layer, the metal grid and the grid oxide layer at least correspond to one part of the source region covered with the epitaxial region, and the grid electrode side walls at least correspond to one, the epitaxial region is made of narrow forbidden band materials, and the doping concentration of the epitaxial region is gradually changed from high to low from a contact interface with the source region to a contact interface with the gate oxide layer in the epitaxial region.

To explain the above gradient, the doping concentration of the epitaxial region is gradually changed from high to low in the epitaxial region from the contact interface with the source region to the contact interface with the gate oxide layer, and the gradient can be gaussian distribution or linear distribution or residual error distribution.

In order to provide a specific structure of the vertical tunneling field effect transistor for improving the subthreshold swing, the vertical tunneling field effect transistor further comprises a substrate, wherein the substrate is arranged on one surface of the intrinsic region and the source region, which is not covered by the epitaxial region, and one surface of the substrate, which is corresponding to the drain region, and is in contact with one surface of the intrinsic region and the source region, which is not covered by the epitaxial region, and one surface of the substrate, which is corresponding. The vertical tunneling field effect transistor can be applied to a vertical heterojunction fin type tunneling field effect transistor. And the substrate may be a semiconductor substrate using conventional silicon or an SOI substrate.

In order to provide a specific structure of the vertical tunneling field effect transistor for improving the subthreshold swing amplitude, the structure can be applied to a double-gate structure, and two grid electrodes and two epitaxial regions are respectively covered above and below at least one part of intrinsic region and at least one part of source region and correspond to each other.

In order to explain the narrow bandgap material, the narrow bandgap material used in the epitaxial region is a III-V semiconductor material, such as SiGe or InAs; when SiGe is adopted, the molar component of the Ge material is more than 0 and less than or equal to 0.3; the molar composition of Ge can be increased to reduce the forbidden bandwidth of the material in the epitaxial region, thereby reducing the tunneling distance and increasing the tunneling current of the device. The Ge component is closer to 0.3, the forbidden band width of the epitaxial region is smaller, and therefore the tunneling distance is reduced, and the tunneling current of the device is increased. This range is mainly due to: although the Ge component is more beneficial to promoting tunneling after being higher than 0.3, due to the fact that the thickness of the epitaxial region is small, Ge atoms can diffuse to other regions to influence the mobility of carriers after the Ge component is higher than 0.3, and meanwhile, when the Ge component is limited to be larger than 0 and smaller than or equal to 0.3, the epitaxial region can be guaranteed to introduce fewer defects.

In order to provide a preferred thickness range for the epitaxial region, the thickness of the epitaxial region is greater than or equal to 2nm and less than or equal to 10 nm. The above range is adopted because the epitaxial region has a thickness of less than 2nm and is susceptible to the FIBL (fringe-induced barrier lowering) effect, and when the thickness is more than 10nm, the control effect of the gate on the tunneling region is weakened and the tunneling current is reduced. The thickness of the epitaxial region should be as small as theoretically possible, and the smaller the thickness, the stronger the electric field control effect of the gate electrode on the epitaxial region, but in practice, it is difficult to make an ultra-thin epitaxial region, and therefore, it is preferable that the thickness is 2nm or more and 10nm or less. Because the thickness of the epitaxial region is not large, the narrow forbidden band material is adopted, and the tunneling distance of the epitaxial region is shorter after the gate voltage is added, the tunneling probability of electrons from the source region to the epitaxial region is improved, and the tunneling current is increased.

Because the longitudinal tunneling field effect transistor can be an N-type longitudinal tunneling field effect transistor or a P-type longitudinal tunneling field effect transistor, the doping of the source region and the drain region of the longitudinal tunneling field effect transistor is respectively as follows: when the tunneling field effect transistor is an N-type longitudinal tunneling field effect transistor, the source region is heavily doped P-type, and the drain region is heavily doped N-type; when the tunneling field effect transistor is a P-type longitudinal tunneling field effect transistor, the source region is heavily doped in an N-type mode, and the drain region is heavily doped in a P-type mode; the doping concentration of the source region and the drain region is 1 × 10 or more¹⁸cm^-3And is not more than 1 x 10²⁰cm^-3And the doping concentration of the source region is greater than that of the drain region so as to inhibit the bipolar conduction characteristic of the TFET. The source region is highly doped to improve the tunneling probability and increase the current, while the drain region is doped with a lower concentration than the source region to reduce the off-state leakage current and suppress the bipolar conduction phenomenon, but the drain region is not doped too low, which causes the drain series resistance to become large, and therefore, the doping concentration is preferably equal to or greater than 1 × 10¹⁸cm^-3And is not more than 1 x 10²⁰cm^-3。

In order to provide a better doping concentration range of the epitaxial region, the doping concentration of the epitaxial region at the contact interface with the source region is greater than or equal to 1 × 10¹⁷cm^-3And is not more than 1 x 10²⁰cm^-3The doping concentration of the epitaxial region at the contact interface with the gate oxide layer is 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3. This is because the doping concentration of the source region is 1 × 10 or more at the contact interface between the source region and the epitaxial region¹⁸cm^-3And is not more than 1 x 10²⁰cm^-3Therefore, the doping concentration range of the epitaxial region at the interface is selected to be 1 × 10 or more¹⁷cm^-3And is not more than 1 x 10²⁰cm^-3The continuity of the doping concentration at the interface can be ensured to be more beneficial to manufacture, and at the contact interface of the epitaxial region and the gate oxide layer, because the doping concentration is required to be gradually changed from high to low from the contact interface with the source region to the contact interface with the gate oxide layer in the epitaxial region, a lower doping concentration is selectedIn the range of 1X 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3。

In order to provide a parameter range adopted by other regions, the intrinsic region is lightly doped N-type monocrystalline silicon or P-type monocrystalline silicon; the light doping is preferably performed in a manner that the doping concentration is 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3The doping type is N-type doping or P-type doping, and theoretically the doping concentration of the intrinsic region should be low, but in practice, the difficulty of controlling the low doping is large, so that the doping concentration is 1 × 10 or more¹⁴cm^-3And is not more than 1 x 10¹⁶cm^-3A range is feasible in which the change in doping concentration does not substantially affect the electrical characteristics.

The width of the intrinsic region is preferably 15nm or more and 25nm or less; when the width of the intrinsic region is less than 15nm, the off-state current between the source and the drain is obviously increased, and the current is not obviously increased after the width is more than 25nm, but the gate capacitance is increased, so that the frequency characteristic of the device is deteriorated, and the area of the device is increased, so that the width is preferably more than or equal to 15nm and less than or equal to 25 nm.

The gate oxide layer is made of a high-K dielectric material, and the relative dielectric constant of the gate oxide layer is larger than 20 so as to ensure the control capability of the gate.

The gate side wall can be made of SiO₂Or Si₃N₄Or a high-K dielectric material with a width not greater than 20 nm; the grid side wall can be arranged on one side of the metal grid close to the drain region, and can also be arranged on two sides of the metal grid, and the width of the grid side wall is not more than 20nm, so that the influence on the electrical characteristics of the device is small, and the width of the grid side wall is not more than 20 nm. The gate side wall and a part of the epitaxial region corresponding to the gate side wall can exceed the upper part of the drain region, but the significance is not great.

Since the metal gate can select a metal material with a specific work function to adjust the threshold voltage of the device, the work function of the metal gate is preferably equal to or greater than 3.6eV and equal to or less than 4.25eV in the case of an N-type vertical tunneling field effect transistor, and is preferably equal to or greater than 4.7eV and equal to or less than 5.5eV in the case of a P-type vertical tunneling field effect transistor.