阅读说明：本技术 混合差分放大器及其方法 (Hybrid differential amplifier and method therefor ) 是由 谢娟 梁宝文 林嘉亮 于 2019-03-14 设计创作，主要内容包括：一种差分放大器及差分放大方法,所述差分放大器包括第一共源放大器,其具有用以接收第一电压并输出第一电流的第一P型通道金属氧化物半导体(PMOS)晶体管；第二共源放大器,具有用以接收第二电压并输出第二电流的第一N型通道金属氧化物半导体(NMOS)晶体管,其中第一共源放大器及第二共源放大器共用共源节点,且第一电压的交流(AC)分量是第二电压的AC分量的反转；第一共栅放大器,具有用以接收第一电流并输出第三电流的第二PMOS晶体管；第二共栅放大器,具有用以接收第二电流并输出第四电流的第二NMOS晶体管；以及负载,用以端接第三电流及第四电流。(A differential amplifier and a differential amplification method, the differential amplifier includes a first common source amplifier having a first P-channel metal oxide semiconductor (PMOS) transistor for receiving a first voltage and outputting a first current; a second common-source amplifier having a first N-channel metal oxide semiconductor (NMOS) transistor for receiving a second voltage and outputting a second current, wherein the first common-source amplifier and the second common-source amplifier share a common-source node, and an Alternating Current (AC) component of the first voltage is an inverse of an AC component of the second voltage; a first common-gate amplifier having a second PMOS transistor for receiving the first current and outputting a third current; a second common-gate amplifier having a second NMOS transistor for receiving the second current and outputting a fourth current; and a load for terminating the third current and the fourth current.)

1. A differential amplifier, comprising:

a first common source amplifier including a first P-channel metal oxide semiconductor transistor for receiving a first voltage and outputting a first current;

a second common-source amplifier including a first N-channel mos transistor for receiving a second voltage and outputting a second current, wherein the first common-source amplifier and the second common-source amplifier share a common-source node, and an ac component of the first voltage is an inverse of an ac component of the second voltage;

a first common-gate amplifier including a second P-channel metal oxide semiconductor transistor for receiving the first current and outputting a third current;

a second common-gate amplifier including a second N-channel metal oxide semiconductor transistor for receiving the second current and outputting a fourth current; and

a load for terminating the third current and the fourth current.

2. The differential amplifier of claim 1, wherein said load comprises a first inductor interposed between a drain of said second pmos transistor and a ground node, and a second inductor interposed between a drain of said second nmos transistor and a power supply node.

3. The differential amplifier of claim 1, wherein said load further comprises an adjustment capacitor for adjusting an impedance of said load.

4. A differential amplifier as claimed in claim 3, wherein:

the gate of the second P-channel MOS transistor is coupled to a first bias DC current;

the gate of the second N-channel MOS transistor is coupled to a second biased DC current;

the source of the second N-channel MOS transistor is an AC current coupled to the gate of the second P-channel MOS transistor;

the source of the second PMOS transistor is an AC current coupled to the gate of the second NMOS transistor.

5. A differential amplifier, comprising:

a first hybrid differential amplifier for receiving a first input signal and a second input signal and outputting a first output signal and a second output signal using a first cascode amplifier and a second cascode amplifier, respectively; and

a second hybrid differential amplifier for receiving a third input signal and a fourth input signal, respectively, and outputting a third output signal and a fourth output signal using a third cascode amplifier and a fourth cascode amplifier, respectively;

wherein:

the first cascode amplifier and the third cascode amplifier are based on using P-channel metal oxide semiconductor transistors, the second cascode amplifier and the fourth cascode amplifier are based on using N-channel metal oxide semiconductor transistors, the dc component of the first input signal is the same as the dc component of the third input signal, the dc component of the second input signal is the same as the dc component of the fourth input signal, the ac component of the first input signal is the same as the ac component of the fourth input signal, the ac component of the second input signal is the same as the ac component of the third input signal, and the ac component of the second input signal is an inverse of the ac component of the first input signal.

6. The differential amplifier of claim 5, further comprising:

a first load including a first inductor and a second inductor for providing terminals for the first output signal and the second output signal, respectively, and

a second load comprising a third inductor and a fourth inductor for providing terminals for the third output signal and the fourth output signal, respectively.

7. The differential amplifier of claim 6, further comprising a power combining network including a fifth inductor, a sixth inductor, a seventh inductor, and an eighth inductor configured to inductively couple with the first inductor, the second inductor, the third inductor, and the fourth inductor, respectively.

8. The differential amplifier of claim 7, wherein said fifth inductor, said sixth inductor, said seventh inductor, and said eighth inductor are connected in a manner effective to sum their respective voltages.

9. The differential amplifier of claim 7, wherein said fifth inductor, said sixth inductor, said seventh inductor, and said eighth inductor are connected in a manner effective to sum their respective currents.

10. A differential amplification method, comprising:

receiving a first voltage and a second voltage, wherein the alternating current component of the first voltage is the reverse of the alternating current component of the second voltage;

converting the first voltage into a first current using a first common source amplifier comprising a first P-channel metal oxide semiconductor transistor;

converting the second voltage to a second current using a second common-source amplifier comprising a first N-channel metal oxide semiconductor transistor, wherein the first common-source amplifier and the second common-source amplifier share a common source node;

relaying the first current to a third current using a first common gate amplifier comprising a second P-channel metal oxide semiconductor transistor;

relaying the second current to a fourth current using a second common-gate amplifier comprising a second N-channel metal oxide semiconductor transistor; and

terminating the third current and the fourth current with a load.

Technical Field

The present invention claims priority from U.S. patent application No. 16/035897 (application date: 2018, 07, 16), the entire contents of which are incorporated by reference as part of the present patent specification.

The present invention relates generally to a differential amplifier circuit and, more particularly, to a circuit that mitigates the adverse effects of ground bounce and source degeneration.

Background

As shown in fig. 1, a conventional differential amplifier 100 includes a core circuit 110 and a load 130. The core circuit 110 includes a differential pair 111 and a splice pair 112. The differential pair 111 includes a first N-channel metal oxide semiconductor (NMOS) transistor 111A and a second NMOS transistor 111B for receiving a signal including a first terminal V_IPAnd a second terminal V_INAnd outputs a first current I_1aAnd a second current I_1bThe cascode pair 112 includes a third NMOS transistor 112A and a fourth NMOS transistor 112B for receiving the first current I_1aAnd a second current I_1bAnd outputs a third current I_1cAnd a fourth current I_1d. The load 130 includes a first inductor 131 and a second inductor 132, and the first inductor 131 and the second inductor 132 are used to provide a termination (termination) for the third current I_1cAnd a fourth current I_1dAnd establishing a first terminal V_ONAnd a second terminal V_OPThe output signal of (1). In the present invention, "V_DD"used to denote a first Direct Current (DC) node called a power supply node, and" V_SS"is used to denote a second DC node, referred to as a ground node. In FIG. 1, "V_BC"is used to denote the DC node that provides a bias voltage to the NMOS transistors 112A and 112B of the cascode pair 112. The conventional differential amplifier 100 is well known to those skilled in the art and thus will not be described in detail herein. Mathematically, V_IPAnd V_INCan be expressed as:

V_IP＝V_BI+v_in(t)(1)

V_IN＝V_BI-v_in(t)(2)

here, V_BIIs V_IPAnd V_INWhich establishes a bias voltage for NMOS transistors 111A and 111B, and v_in(t) represents the Alternating Current (AC) signal as a function of time t.

One problem with the conventional differential amplifier 100 is that:when v is_in(t) when large, a large AC current flows into the ground node "V_SS". Ideally, the ground node "V_SS"has zero impedance and is therefore not disturbed by large AC currents. However, in practice, the ground node "V_SS"has non-zero impedance, resulting in" ground bounce "and" source degeneration, "which will reduce the gain of the differential pair 111, thereby degrading the differential amplifier 100 in terms of performance.

Therefore, there is a need for a differential amplifier that can mitigate the adverse effects of ground bounce and source degeneration.

Disclosure of Invention

In one embodiment, an apparatus comprises: a first common source amplifier including a first P-channel metal oxide semiconductor (PMOS) transistor for receiving a first voltage and outputting a first current; a second common-source amplifier including a first N-channel metal oxide semiconductor (NMOS) transistor for receiving a second voltage and outputting a second current, wherein the first common-source amplifier and the second common-source amplifier share a common-source node, and an Alternating Current (AC) component of the first voltage is an inversion (inversion) of the AC component of the second voltage; a first common-gate amplifier (first common-gate amplifier) including a second PMOS transistor for receiving the first current and outputting a third current; a second common-gate amplifier including a second NMOS transistor for receiving the second current and outputting a fourth current; and a load for terminating the third current and the fourth current.

In one embodiment, an apparatus comprises: a first hybrid differential amplifier for receiving a first input signal and a second input signal and outputting a first output signal and a second output signal using a first cascode amplifier and a second cascode amplifier, respectively; and a second hybrid differential amplifier for receiving the third input signal and the fourth input signal, respectively, and outputting a third output signal and a fourth output signal using the third cascode amplifier and the fourth cascode amplifier, respectively; wherein: the first cascode amplifier and the third cascode amplifier are based on using p-channel metal oxide semiconductor (PMOS) transistors, the second cascode amplifier and the fourth cascode amplifier are based on using n-channel metal oxide semiconductor (NMOS) transistors, a DC component of the first input signal is the same as a DC component of the third input signal, a DC component of the second input signal is the same as a DC component of the fourth input signal, an AC component of the first input signal is the same as an AC component of the fourth input signal, an AC component of the second input signal is the same as an AC component of the third input signal, and an AC component of the second input signal is an inversion (inversion) of the AC component of the first input signal.

In one embodiment, a method comprises: receiving a first voltage and a second voltage, wherein an AC component of the first voltage is an inversion of an AC component of the second voltage; converting the first voltage to a first current using a first common source amplifier including a first P-channel metal oxide semiconductor (PMOS) transistor; converting the second voltage to a second current using a second common-source amplifier comprising a first N-channel metal oxide semiconductor (NMOS) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common-source node; relaying the first current to a third current using a first common-gate amplifier comprising a second PMOS transistor; relaying the second current to a fourth current using a second common-gate amplifier comprising a second NMOS transistor; and terminating the third current and the fourth current with a load.

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.

Drawings

Fig. 1 shows a schematic diagram of a conventional differential amplifier.

Fig. 2A shows a schematic diagram of a hybrid differential amplifier according to an embodiment of the invention.

Fig. 2B shows a schematic diagram of a hybrid differential amplifier according to another embodiment of the invention.

Fig. 3 shows a schematic diagram of a complementary hybrid differential amplifier according to an embodiment of the invention.

Fig. 4A shows a schematic diagram of a power combining network.

Fig. 4B shows a schematic diagram of another power combining network.

Fig. 5 shows a flow chart of a method according to the invention.

Description of the symbols

100: differential amplifier

110. 210, 210_ 1: core circuit

111. 211: differential pair

V_DD: first direct current DC node

130. 230: load(s)

131. 231: first inductor

132. 232: second inductor

V_ON、V_IP、V_2c、V_P+: first end

V_OP、V_IN、V_2d、V_N-: second end

I_1a、I_2a: first current

I_1b、I_2b: the second current

I_1c、I_2c: third current

I_1d、I_2d: the fourth current

112. 212, and (3): splicing pair

111A, 111B, 112A, 112B, 211N, 212N: NMOS transistor

V_BC: DC node

V_SS: ground node

233. CN1, CN2, C1, C2, C3, C4: capacitor with a capacitor element

212_ 1: hybrid splice pair

211P, 212P: PMOS transistor

200A, 200B: hybrid differential amplifier

V_BC1、V_BC2: bias voltage

219: common source node

R1: a first resistor

R2: second resistance

300: complementary hybrid differential amplifier

310. 320, and (3) respectively: hybrid differential amplifier

311. 312, 321, 322, 411, 412, 421, 422: inductance

I_3a、I_3b、I_3c、I_3d、I_4a、I_4b: electric current

V_CM: common source voltage

V_CS、V_3a、V_3b、V_3c、V_3d、V_4a、V_4b: voltage of

N311, N312, N321, N322: output node

K11, K12, K21, K22: inductive coupling

N411, N421, N422: node point

V_O+、V_O-、V_P-、V_N+: voltage of

400A, 400B: power combining network

Detailed Description

The present invention relates to a differential amplifier. While the specification describes several exemplary embodiments of the invention considered as advantageous modes of carrying out the invention, it is to be understood that the invention may be embodied in various forms and is not limited to the specific examples described below or to the specific ways of carrying out any of the features of these examples. In other instances, well-known details are not shown or described to avoid obscuring embodiments of the invention.

Those skilled in the art understand the terms and concepts related to microelectronics used in this disclosure, such as "voltage", "current", "signal", "differential signal", "common mode", "capacitance", "inductance", "resistance", "transistor", "metal-oxide semiconductor (MOS)", "p-channel metal-oxide semiconductor (PMOS)", "n-channel metal-oxide semiconductor", "Alternating Current (AC)", "Direct Current (DC)", "DC coupling", "AC coupling", "source", "gate", "drain", "ground node", "power node", "cascode", "common-source amplifier", "common-gate amplifier", and "cascode amplifier". Those skilled in the art can also readily recognize the symbols of a MOS transistor and its associated "source", "gate" and "drain" terminals. These terms and basic concepts will be readily apparent to those skilled in the art and will therefore not be explained in detail here.

In the present disclosure, "DC" represents direct current and "AC" represents alternating current. The DC node is a node having a substantially fixed potential. In particular, "V_DD"used to denote a first DC node, referred to as the supply node," V_SS"is used to denote a second DC node, referred to as a ground node. Similarly, a differential signal is a composite signal including a first component signal and a second component signal. The first component signal is generally referred to as the first terminal and the second component signal is generally referred to as the second terminal.

A schematic diagram of a hybrid differential amplifier 200A according to an embodiment of the present invention is shown in fig. 2A. The hybrid differential amplifier 200A includes a core circuit 210 and a load 230. The core circuit 210 includes a hybrid differential pair 211 and a hybrid splice pair 212. The hybrid differential pair 211 comprises a pair of common-source amplifiers including a first PMOS transistor 211P and a first NMOS transistor 211N for receiving a signal comprising a first terminal V_P+And a second terminal V_N-And outputs a first current I_2aAnd a second current I_2b. In an alternative embodiment, the hybrid differential pair 211 further comprises: a first neutralization capacitor CN1 and a second neutralization capacitor CN2, the first neutralization capacitor CN1 is used to couple the gate of the first PMOS transistor 211P to the drain of the first NMOS transistor 211N, and the second neutralization capacitor CN2 is used to couple the gate of the first NMOS transistor 211N to the drain of the first PMOS transistor 211P. Neutralizing capacitors CN1 and CN2 can mitigate the Miller effect (Miller effect) of hybrid differential pair 211. Miller effect on the fieldAre well known to the skilled person and will therefore not be described here.

The cascode pair 212 includes a second PMOS transistor 212P and a second NMOS transistor 212N, which are embodied as a pair of common-gate amplifiers for respectively receiving the first current I_2aAnd a second current I_2bAnd outputs a third current I_2cAnd a fourth current I_2d. From another perspective, first PMOS transistor 211P and second PMOS transistor 212P are formed to receive V_P+And output I_2cAnd the first NMOS transistor 211N and the second NMOS transistor 212N are formed to receive V_N-And output I_2dThe second cascode amplifier of (1). The load 230 includes a first inductor 231 and a second inductor 232 for providing a terminal for the third current I_2cAnd a fourth current I_2dAnd establishes a first terminal V_2cAnd a second end V_2dThe output signal of (1). In an alternative embodiment, the load 230 further comprises an adjusting capacitor 233 for adjusting the impedance of the load 230. In FIG. 2A, "V_BC1"used to denote bias voltage for PMOS transistor 212P," V_BC2"is used to denote the bias voltage for the NMOS transistor 212N. Mathematically, V_P+And V_N-Can be expressed as:

V_P+＝V_BP+v_in(t)(3)

V_N-＝V_BN-v_in(t)(4)

here, V_BPIs V_P+A DC component of which establishes a bias voltage, V, for PMOS transistor 211P_BNIs V_N-A DC component that establishes a bias voltage for the NMOS transistor 211N, and v_in(t) represents an Alternating Current (AC) signal as a function of time t. Although V_P+And V_N-Have different DC components but, except for polarity reversal, they have the same AC component. In terms of AC component, V_P+And V_N-Forming a differential signal. Functionally, the hybrid differential amplifier 200A and the conventional differential amplifier 100 are identical in terms of the AC component. However, rather than using the same type of device to amplify the differential signal, the hybrid differential amplifier 200A uses a different type of device:PMOS transistors 211P and 212P for amplifying V_P+And NMOS transistors 211N and 212N are used to amplify V_N-. Assuming that the first cascode amplifier (including PMOS transistors 211P and 212P) and the second cascode amplifier (including NMOS transistors 211N and 212N) are appropriately sized and biased to have substantially equal transconductance (transconductance), the first current I_2aWill be substantially equal to the second current I_2bAnd even V_P+And V_N-Is dependent on v_in(t) change, voltage V at common source node 219_CSOr may be substantially fixed. Therefore, a large v_in(t) does not cause substantial "source degradation" of PMOS transistor 211P and NMOS transistor 211N. Also in this regard, therefore, the hybrid differential amplifier 200A is inherently superior to the conventional differential amplifier 100 of fig. 1.

Fig. 2B shows a schematic diagram of a hybrid differential amplifier 200B according to another embodiment of the invention. The hybrid differential amplifier 200B of fig. 2B is the same as the hybrid differential amplifier 200A of fig. 2A, except that the core circuit 210 in fig. 2A is replaced with an alternate core circuit 210_1, where the core circuit 210_1 is the same as the core circuit 210 in fig. 2, except that the hybrid splice pair 212 in the core circuit 210 is replaced with an alternate hybrid splice pair 212_1 in the alternate core circuit 210_ 1. The hybrid splice pair 212_1 is identical to the hybrid splice pair 212, but the sources and gates of the PMOS transistor 212P and the NMOS transistor 212N are cross-coupled through the first capacitor C1 and the second capacitor C2, while the drains and gates 212P of the PMOS transistor and the NMOS transistor 212N are cross-coupled through the third capacitor C3 and the fourth capacitor C4. More specifically, the source of NMOS transistor 212N is coupled to the gate of PMOS transistor 212P through capacitor C1; the source of PMOS transistor 212P is coupled to the gate of NMOS transistor 212N through capacitor C2; the drain of NMOS transistor 212N is coupled to the gate of PMOS transistor 212P through capacitor C3; the drain of PMOS transistor 212P is coupled to the gate of NMOS transistor 212N through capacitor C4. In addition, at the gate of PMOS transistor 212P and "V_BC1"A first resistor R1 is interposed between and at the gate and" V "of the NMOS transistor 212N_BC2"between which is interposed a second resistor R2.

This configuration enables the hybrid differential amplifier 2 to be replacedThe bias conditions for 00B are the same as those for the hybrid differential amplifier 200A. The cross coupling of the source and gate between the PMOS transistor 212P and the NMOS transistor 212N through the capacitors C1 and C2 may provide a first positive feedback, which may effectively increase the gain of the hybrid differential amplifier 200B. The cross coupling of the drains and gates between PMOS transistor 212P and NMOS transistor 212N through capacitors C3 and C4 may provide a second positive feedback that may also effectively increase the gain of hybrid differential amplifier 200B. In fact, the second positive feedback tends to be stronger and more efficient than the first positive feedback, since the voltage signal on the drain of the MOS transistor tends to be stronger than the voltage signal on the source thereof, which is true for the PMOS transistor 212P and the NMOS transistor 212N. However, the second positive feedback may cause instability due to having a high gain, and must therefore be used with caution. In another embodiment, the capacitors C3 and C4 are removed; that is, the second positive feedback is not used. V_O+And V_O-Is the voltage of the output on load 230.

A schematic diagram of a complementary hybrid differential amplifier 300 according to an embodiment of the invention is depicted in fig. 3. The complementary hybrid differential amplifier 300 includes a first hybrid differential amplifier 310 and a second hybrid differential amplifier 320. The first hybrid differential amplifier 310 is the same as the hybrid differential amplifier 200A in fig. 2A. (Note that for simplicity, the alternate embodiment of FIG. 2A including capacitors 233, CN1, and CN2 are not explicitly shown in FIG. 3, but they may be at the discretion of the circuit designer.) second hybrid differential amplifier 320 is identical to first hybrid differential amplifier 310, except for voltage V_P-And a voltage V_N+Input to a second hybrid differential amplifier 320 instead of V_P+And V_N-Input to a second hybrid differential amplifier 320, wherein:

V_P-＝V_BP-v_in(t)(5)

V_N+＝V_BN+v_in(t)(6)

in this manner, the input provided to the second hybrid differential amplifier 320 is complementary to the input provided to the first hybrid differential amplifier 310. The common source nodes of the two hybrid differential amplifiers 310 and 320 are connected togetherTo generate a common source voltage V_CM. The first hybrid differential amplifier 310 has two inductances labeled 311 and 312; the second hybrid differential amplifier 320 has two inductances labeled 321 and 322; v_3aAnd V_3bTo represent the voltages at the output nodes N311 and N312 of the first hybrid differential amplifier 310, respectively; v_3cAnd V_3dThe voltages at the output nodes N321 and N322 of the second hybrid differential amplifier 320 are respectively represented; i is_3aAnd I_3bThe current of inductors 311 and 312 are shown; and I_3cAnd I_3dWhich are used to represent the currents of inductors 321 and 322, respectively.

The two hybrid differential amplifiers 310 and 320 are replaced by the hybrid differential amplifier 200B in fig. 2B, which is not explicitly shown in the figure, but is an alternative implementation for those skilled in the art; that is, positive feedback is used to enhance gain.

The output (i.e., V) of the first hybrid differential amplifier 310_3aAnd V_3bOr I_3aAnd I_3b) And the output (i.e., V) of the second hybrid differential amplifier 320_3cAnd V_3dOr I_3cAnd I_3d) The combining may be performed using the power combining network 400A shown in fig. 4A. Power combining network 400A includes: the inductor 411 is used for generating an inductive coupling K11 with the inductor 311; the inductor 412 is used for generating an inductive coupling K12 with the inductor 312; the inductor 421 is used to generate an inductive coupling K21 with the inductor 312; and the inductor 422 is used to generate an inductive coupling K22 with the inductor 322. Inductors 411, 412, 421 and 422 are connected in such a way that the respective voltages coupled to inductors 311, 312, 321 and 322 effectively sum up, thereby generating voltage V at node N412 and node N422, respectively_4aAnd V_4bWhich can be represented as V_3a、V_3b、V_3c、V_3dThe sum of (a) and (b). As an example for illustration purposes: the inductors 311, 312, 321, 322, 411, 412, 421 and 422 all have the same inductance, and the inductive couplings K11, K12, K21 and K22 all have substantially uniform coupling coefficients, so that a substantially uniform coupling coefficient can be obtained

V_4a-V_4b＝V_3b-V_3a+V_3c-V_3d(7)

It is to be noted that V_3b-V_3aRepresents the output, V, of the first hybrid differential amplifier 310_3c-V_3dRepresents the output of the second hybrid differential amplifier 320, thus V_4a-V_4bRepresenting the sum of the outputs of the two hybrid differential amplifiers 310 and 320.

In an alternative embodiment shown in fig. 4B, inductors 411, 412, 421 and 422 are connected in such a way that their respective currents coupled to inductors 311, 312, 321 and 322 can effectively sum up, thereby resulting in current I being output to nodes N411 and N421, respectively_4aAnd I_4bCan represent I_3a、I_3b、I_3cAnd I_3dThe sum of (a) and (b). Under the same conditions as described above (i.e., the inductors 311, 312, 321, 322, 411, 412, 421 and 422 all have the same inductance value, and the inductive couplings K11, K12, K21 and K22 all have approximately uniform coupling coefficients), the aforementioned characteristics can be obtained

I_4a-I_4b＝I_3a+I_3b–(I_3c+I_3d)(8)

It is to be noted that_3a+I_3bRepresents the output of the first hybrid differential amplifier 310, and I_3c+I_3dRepresents the output of the second hybrid differential amplifier 320, and therefore I_4a-I_4bRepresenting the sum of the outputs of the two hybrid differential amplifiers 310 and 320.

In contrast, power combining network 400A of fig. 4A is beneficial for generating high output voltages, while power combining network 400B of fig. 4B is beneficial for generating high output currents.

As illustrated in the flow chart shown in fig. 5, a method includes: (step 510) receiving a first voltage and a second voltage, wherein an AC component of the first voltage is an inversion of an AC component of the second voltage; (step 520) converting the first voltage to a first current using a first common source amplifier comprising a first p-channel metal oxide semiconductor (PMOS) transistor; (step 530) converting the second voltage to a second current using a second common-source amplifier comprising a first n-channel metal oxide semiconductor (NMOS) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common-source node; (step 540) relaying the first current to a third current using a first common-gate amplifier comprising a second PMOS transistor; (step 550) relaying the second current to a fourth current using a second common-gate amplifier comprising a second NMOS transistor; and (step 560) terminating the third current and the fourth current with a load.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the following claims.

The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, which is defined by the appended claims.