阅读说明：本技术 包括场效应晶体管的半导体器件 (Semiconductor device including field effect transistor ) 是由 金珍永 益冈有里 于 2019-07-18 设计创作，主要内容包括：本发明公开了一种半导体器件,该半导体器件包括：衬底,包括第一阱区；设置在衬底上的栅电极；设置在衬底和栅电极之间的半导体图案；设置在衬底上且在栅电极的相对两侧的多个源极/漏极图案；杂质层,设置在衬底中且在半导体图案与第一阱区之间；以及阻挡层,设置在衬底中且在半导体图案与杂质层之间。阻挡层包括氧。(The invention discloses an semiconductor device, which comprises a substrate, a gate electrode, a semiconductor pattern, a plurality of source/drain patterns, an impurity layer and a barrier layer, wherein the substrate comprises a th well region, the gate electrode is arranged on the substrate, the semiconductor pattern is arranged between the substrate and the gate electrode, the source/drain patterns are arranged on the substrate and are arranged on two opposite sides of the gate electrode, the impurity layer is arranged in the substrate and is arranged between the semiconductor pattern and a th well region, and the barrier layer is arranged in the substrate and is arranged between the semiconductor pattern and the impurity layer.)

1, semiconductor device, comprising:

a substrate comprising an th well region;

a gate electrode disposed on the substrate;

a semiconductor pattern disposed between the substrate and the gate electrode;

a plurality of source/drain patterns disposed on the substrate and on opposite sides of the gate electrode;

an impurity layer disposed in the substrate between the semiconductor pattern and the th well region, and

a barrier layer disposed in the substrate between the semiconductor pattern and the impurity layer,

wherein the barrier layer comprises oxygen.

2. The semiconductor device of claim 1, wherein the semiconductor pattern is disposed between the source/drain patterns and comprises a semiconductor material.

3. The semiconductor device of claim 1, wherein the impurity layer and the well region include impurities of a conductivity type,

wherein an impurity concentration of the th conductivity type in the impurity layer is greater than an impurity concentration of the th conductivity type in the well region.

4. The semiconductor device according to claim 3, wherein an impurity concentration of the th conductivity type in an upper portion of the impurity layer is larger than an impurity concentration of the th conductivity type in a lower portion of the impurity layer,

wherein the upper portion of the impurity layer is closer to the barrier layer than the lower portion of the impurity layer.

5. The semiconductor device of claim 3, wherein the source/drain pattern includes an impurity having a second conductivity type,

wherein the second conductivity type is different from the th conductivity type.

6. The semiconductor device according to claim 3, further comprising a second well region disposed in the substrate between the well region and the impurity layer,

wherein the second well region includes impurities having the th conductivity type.

7. The semiconductor device according to claim 6, wherein the impurity concentration of the th conductivity type in the impurity layer is greater than an impurity concentration of the th conductivity type in the second well region.

8. The semiconductor device of claim 1, wherein each of the source/drain patterns contacts the blocking layer or both the blocking layer and the impurity layer.

9. The semiconductor device according to claim 8, wherein each of the source/drain patterns penetrates the barrier layer and contacts the impurity layer.

10. The semiconductor device according to claim 1, wherein the impurity layer is disposed between the th well region and each of the source/drain patterns.

11. The semiconductor device according to claim 10, wherein the blocking layer is disposed between the impurity layer and each of the source/drain patterns.

12. The semiconductor device of claim 11, wherein the semiconductor pattern is disposed between the barrier layer and each of the source/drain patterns.

13. The semiconductor device of claim 1, further comprising a plurality of device isolation patterns disposed on the substrate and on respective opposite sides of the semiconductor pattern,

wherein the source/drain patterns are spaced apart from each other in an th direction across the semiconductor pattern,

wherein th ones of the plurality of device isolation patterns are spaced apart from each other in a second direction crossing the th direction, wherein each of the device isolation patterns exposes a side surface of the semiconductor pattern, an

Wherein the gate electrode extends in the second direction and covers a top surface and exposed side surfaces of the semiconductor pattern.

14, semiconductor device, comprising:

a substrate;

a gate electrode disposed on the substrate;

a semiconductor pattern disposed between the substrate and the gate electrode;

a plurality of source/drain patterns disposed on the substrate and on opposite sides of the gate electrode;

an impurity layer disposed in the substrate and adjacent to the semiconductor pattern; and

a barrier layer disposed in the substrate between the semiconductor pattern and the impurity layer,

wherein the impurity layer includes an impurity having a th conductivity type,

wherein an impurity concentration of the th conductive type in an upper portion of the impurity layer is greater than an impurity concentration of the th conductive type in a lower portion of the impurity layer.

15. The semiconductor device according to claim 14, wherein an upper portion of the impurity layer is closer to the barrier layer than the lower portion of the impurity layer.

16. The semiconductor device of claim 14, wherein the barrier layer comprises oxygen.

17. The semiconductor device of claim 14, wherein the source/drain pattern includes an impurity having a second conductivity type,

wherein the second conductivity type is different from the th conductivity type.

18. The semiconductor device of claim 14, further comprising well regions and a second well region disposed in the substrate, wherein

The second well region is disposed between the th well region and the impurity layer,

the th well region and the second well region include impurities having the th conductivity type, an

An impurity concentration of the th conductivity type in the impurity layer is greater than an impurity concentration of the th conductivity type in the th well region and an impurity concentration of the th conductivity type in the second well region.

19, semiconductor device, comprising:

a substrate;

a plurality of gate electrodes disposed on the substrate;

a semiconductor pattern disposed between the substrate and the gate electrode;

a plurality of source/drain patterns disposed on the substrate, wherein each of the plurality of source/drain patterns is disposed between pairs of the plurality of gate electrodes;

an impurity layer disposed in the substrate and including impurities having a th conductivity type, and

a barrier layer disposed in the substrate and between the semiconductor pattern and the impurity layer,

wherein the barrier layer is disposed adjacent to an upper surface of the impurity layer.

20. The semiconductor device according to claim 19, wherein the impurity layer includes an upper portion adjacent to the upper surface of the impurity layer and a lower portion adjacent to a lower surface of the impurity layer, and the upper portion has an impurity concentration of the th conductivity type greater than the lower portion.

Technical Field

The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors.

Background

Accordingly, has been a continuing effort to produce semiconductor devices having improved performance while overcoming limitations due to increased integration of the semiconductor devices.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, an semiconductor device includes a substrate including a th well region, a gate electrode disposed on the substrate, a semiconductor pattern disposed between the substrate and the gate electrode, a plurality of source/drain patterns disposed on the substrate and on opposite sides of the gate electrode, an impurity layer disposed in the substrate and between the semiconductor pattern and a th well region, a barrier layer disposed in the substrate and between the semiconductor pattern and the impurity layer, the barrier layer including oxygen.

According to an exemplary embodiment of the inventive concept, an semiconductor device includes a substrate, a gate electrode disposed on the substrate, a semiconductor pattern disposed between the substrate and the gate electrode, a plurality of source/drain patterns disposed on the substrate on opposite sides of the gate electrode, an impurity layer disposed in the substrate and adjacent to the semiconductor pattern, a barrier layer disposed in the substrate between the semiconductor pattern and the impurity layer, the impurity layer including an impurity having a conductive type, an impurity concentration of a conductive type in an upper portion of the impurity layer being greater than an impurity concentration of a conductive type in a lower portion of the impurity layer.

According to an exemplary embodiment of the inventive concept, an semiconductor device includes a substrate, a plurality of gate electrodes disposed on the substrate, a semiconductor pattern disposed between the substrate and the gate electrodes, a plurality of source/drain patterns disposed on the substrate, wherein each of the plurality of source/drain patterns is disposed between pairs of the gate electrodes among the plurality of gate electrodes, an impurity layer disposed in the substrate and including impurities having a th conductive type, a blocking layer disposed in the substrate and between the semiconductor pattern and the impurity layer, the blocking layer being disposed adjacent to an upper surface of the impurity layer.

Drawings

The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

FIGS. 2A, 2B and 2C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of FIG. 1, respectively, according to an exemplary embodiment of the inventive concept;

fig. 3 is a graph illustrating impurity concentrations in an impurity layer according to an exemplary embodiment of the inventive concept;

fig. 4A, 5A, 6A, 7A and 8A are cross-sectional views taken along line I-I' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 4B, 5B, 6B, 7B, and 8B are cross-sectional views taken along line II-II' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 4C, 5C, 6C, 7C, and 8C are cross-sectional views taken along line III-III' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

FIGS. 9A, 9B and 9C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of FIG. 1, respectively, illustrating a semiconductor device according to an exemplary embodiment of the present invention;

fig. 10A, 11A, and 12A are cross-sectional views taken along line I-I' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 10B, 11B, and 12B are cross-sectional views taken along line II-II' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 10C, 11C, and 12C are cross-sectional views taken along line III-III' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 13A, 13B and 13C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of fig. 1, respectively, illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 14A, 15A and 16A are cross-sectional views taken along line I-I' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 14B, 15B and 16B are cross-sectional views taken along line II-II' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept; and

fig. 14C, 15C, and 16C are cross-sectional views taken along line III-III' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Detailed Description

Exemplary embodiments of the inventive concept will be described in more detail below with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown.

Fig. 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 2A, 2B and 2C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of fig. 1, respectively, according to an exemplary embodiment of the inventive concept. Fig. 3 is a graph illustrating impurity concentrations in an impurity layer according to an exemplary embodiment of the inventive concept.

Referring to fig. 1 and 2A to 2C, a substrate 100 may include an active region AR and a plurality of active patterns AP. protruding from the active region AR, active patterns AP may extend in a direction D1 on the active region AR, and each of the active patterns AP may be spaced apart from each other in a second direction D2 crossing the direction D1 a direction D1 and a second direction D2 may extend parallel to a bottom surface 100B of the substrate 100 a substrate 100 may be, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate.

The substrate 100 may include a th device isolation pattern 130 defining an active area AR, a th device isolation pattern 130 may be disposed on a corresponding side surface of the active area AR, for example, the th device isolation pattern 130 may contact a corresponding side surface of the active area AR, the substrate 100 may further include a second device isolation pattern 132 defining an active pattern AP, the second device isolation pattern 132 may be disposed on the active area AR, the second device isolation pattern 132 may extend in a direction D1 on the active area AR, and each of the second device isolation patterns 132 may be spaced apart from each other in a second direction D2, the second device isolation pattern 132 and the active pattern AP may be alternately disposed in the second direction D2 on the active area AR, pairs of the second device isolation patterns 132 may be disposed on respective opposite side surfaces of each of the active pattern AP, for example, each of the second device isolation pattern 132 may be disposed between each pair of the active pattern AP, the th device isolation pattern 130 may be disposed deeper than the second device isolation pattern 132, the second device isolation pattern 132 may be disposed at a height from the bottom surface of the second device isolation pattern 130B, the nitride isolation pattern 132, and the bottom surface isolation pattern 132 may indicate that the device isolation pattern 132 may be at a height greater than the second device isolation pattern 130B, the height of the second device isolation pattern 132, the nitride isolation pattern 132, the bottom surface of the nitride isolation pattern 130, the nitride isolation pattern 132, and the bottom surface of the nitride isolation pattern 130 may indicate that the device isolation pattern 132 may be, the device isolation pattern 132 may be at a distance , the height of the bottom.

The well region 102 may be disposed in the active region AR of the substrate 100. the well region 102 may be an impurity region where the substrate 100 is doped with a dopant (or, for example, an impurity) having a conductivity type, for example, the well region 102 may have a conductivity type, for example, when the conductivity type is an N-type, the dopant having a conductivity type may be, for example, phosphorus (P), for example, the conductivity type is a P-type, and the dopant having a conductivity type may be, for example, boron (B).

The second well region 104, the impurity layer 110, and the barrier layer 120 may be disposed in each of the active patterns AP, the second well region 104 may be disposed at a lower portion of each of the active patterns AP, and the impurity layer 110 and the barrier layer 120 may be disposed at an upper portion of each of the active patterns AP, the impurity layer 110 may be interposed between the second well region 104 and the barrier layer 120, for example, the second well region 104 may be disposed on the active region AR, the impurity layer 110 may be disposed on the second well region 104, and the barrier layer 120 may be disposed on the barrier layer 110, the second well region 104 may be an impurity region where the substrate 100 is doped with a dopant having a th conductive type, the second well region 104 may have a conductive type identical to that of the well region 102, according to an exemplary embodiment of the present inventive concept, a dopant concentration of a th conductive type in the second well region 104 may be substantially identical to that of a th conductive type in the well region 102.

The impurity layer 110 may be an impurity region where the substrate 100 is doped with a dopant having a th conductive type, the impurity layer 110 may have the same conductive type as that of the and second well regions 102 and 104, the dopant concentration of the th conductive type in the impurity layer 110 may be greater than that of the th conductive type in each of the and second well regions 102 and 104, the barrier layer 120 may be disposed in the substrate 100 and may include oxygen atoms, for example, the barrier layer 120 may include silicon oxide, the barrier layer 120 may function as a diffusion interruption layer, which may prevent a dopant having the th conductive type from diffusing in the impurity layer 110.

Referring to fig. 3, a dotted line (a) may represent a concentration distribution of dopants having a th conductive type in the impurity layer 110 before an annealing process, and a solid line (b) may represent a concentration distribution of dopants having a th conductive type in the impurity layer 110 after the annealing process may cause diffusion of dopants having a th conductive type in the impurity layer 110, and the barrier layer 120 may prevent diffusion of dopants having a th conductive type as a result, dopants having a th conductive type may diffuse from a lower portion 110L of the impurity layer 110 and may then be stacked in an upper portion 110U of the impurity layer 110, for example, the upper portion 110U may be adjacent to an upper surface of the impurity layer 110, and the lower portion 110L may be adjacent to a lower surface of the impurity layer 110.

Referring to fig. 1 and 2A to 2C, active structures AS may be disposed on a substrate 100 active structures AS may be disposed on respective active patterns AP may extend in an th direction D1 and may be spaced apart from each other in a second direction D2 each active structure AS may include a semiconductor pattern SP and source/drain patterns SD. source/drain patterns SD may be spaced apart from each other in a th direction D1 across the semiconductor pattern SP extending in a th direction D1, for example, the semiconductor patterns SP may be disposed between adjacent source/drain patterns SD.

The semiconductor pattern SP may be an epitaxial pattern grown from the substrate 100 serving as a seed, the semiconductor pattern SP may include an intrinsic semiconductor material, for example, the semiconductor pattern SP may include undoped silicon.the source/drain pattern SD may be an epitaxial pattern grown from the substrate 100 serving as a seed, the source/drain pattern SD may include at least of, for example, silicon germanium (SiGe), silicon (Si), and/or silicon carbide (SiC). the source/drain pattern SD may also include dopants having a second conductivity type.

In an exemplary embodiment of the inventive concept, each source/drain pattern SD may contact the barrier layer 120 or the impurity layer 110 and the barrier layer 120. for example, each source/drain pattern SD may penetrate the barrier layer 120 and contact the impurity layer 110. in this case, at least portions of the impurity layer 110 may extend between adjacent source/drain patterns SD. in addition, the impurity layer 110 may be between the second well region 104 and the source/drain pattern SD. for example, each source/drain pattern SD may have a lowest bottom surface SD _ B at a height higher than that of the bottom surface 110B of the impurity layer 110. however, the inventive concept is not limited thereto.

The active fin AF may include a semiconductor pattern SP. exposed by the second device isolation pattern 132, a top surface 132U of the second device isolation pattern 132 may be at a height lower than that of a top surface SP _ U of the semiconductor pattern SP, and a top surface of a th device isolation pattern 130 may be at a height substantially the same AS that of the top surface 132U of the second device isolation pattern 132, and may expose a side surface SP _ s of the semiconductor pattern SP, but the inventive concept is not limited thereto.

The gate structures GS disposed on the substrate 100 may extend across the active structures AS, the gate structures GS may extend in the second direction D2 and may cover the semiconductor pattern SP. of each active structure AS, the gate structures GS may cover the top surface SP _ U and the side surface SP _ S of the semiconductor pattern SP, and may extend in the second direction D2 to cover the top surface 132U of the second device isolation pattern 132.

The gate structure GS may include a gate electrode GE extending in the second direction D2, a gate dielectric pattern GI between the gate electrode GE and the semiconductor pattern SP, a gate capping pattern CAP on a top surface of the gate electrode GE, and a gate spacer GSP on a side surface of the gate electrode GE. The gate electrode GE may cover the top surface SP _ U and the side surface SP _ S of the semiconductor pattern SP and may extend in the second direction D2 to cover the top surface 132U of the second device isolation pattern 132. The gate dielectric pattern GI may extend along a bottom surface of the gate electrode GE. The gate dielectric pattern GI may be interposed between the gate electrode GE and the top surface SP _ U of the semiconductor pattern SP and between the gate electrode GE and each side surface SP _ S of the semiconductor pattern SP. The gate dielectric pattern GI may extend between the gate electrode GE and each top surface 132U of the second device isolation pattern 132. The gate dielectric pattern GI may extend from a bottom surface of the gate electrode GE toward a gap between the gate electrode GE and the gate spacer GSP. The gate spacer GSP may extend in the second direction D2 along a side surface of the gate electrode GE, and the gate capping pattern CAP may extend in the second direction D2 along a top surface of the gate electrode GE.

The gate electrode GE may include a doped semiconductor, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and/or a metal (aluminum, tungsten, etc.). the gate dielectric pattern GI may include or more high-k dielectric layers.

The 3556 th and second well regions 102 and 104 and the th conductivity type of the impurity layer 110 may be a P-type and the second conductivity type of the source/drain pattern SD may be an N-type when the transistor is an NMOSFET.

When the transistor uses the intrinsic semiconductor pattern as a channel, the resistance distribution of the transistor can be increased to drive the transistor to operate at a low voltage; however, the transistor may be susceptible to short channel effects caused by diffusion of dopants in the source/drain pattern SD.

According to an exemplary embodiment of the inventive concept, the impurity layer 110 and the blocking layer 120 may be disposed adjacent to the semiconductor pattern SP and the source/drain pattern SD, for example, the impurity layer 110 may be a region where the substrate 100 is heavily doped with a dopant (e.g., a dopant having a th conductive type) having a conductive type different from that of the source/drain pattern SD, and the blocking layer 120 may include oxygen atoms the blocking layer 120 may function as a diffusion interruption layer which may prevent diffusion of a dopant having a th conductive type in the impurity layer 110 and thus a dopant having a th conductive type in the impurity layer 110 may be accumulated in an upper portion 110U of the impurity layer 110. as a result, a dopant concentration of a th conductive type in the impurity layer 110 may have a maximum value in the upper portion 110U of the impurity layer 110.

Interlayer dielectric layer 200 may be disposed on substrate 100 and may cover active structure AS and gate structure GS. interlayer dielectric layer 200 may cover top surfaces of th and second device isolation patterns 130 and 132 interlayer dielectric layer 200 may include source/drain contacts and gate contacts, for example, interlayer dielectric layer 200 may be connected to corresponding source/drain patterns SD and may be connected to gate electrode GE. source/drain contacts and gate contacts may apply voltages to source/drain patterns SD and gate electrode GE, respectively, interlayer dielectric layer 200 may include, for example, an oxide, a nitride, or an oxynitride.

Fig. 4A to 8A are cross-sectional views taken along line I-I' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 4B to 8B are cross-sectional views taken along line II-II' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 4C to 8C are cross-sectional views taken along line III-III' of fig. 1, illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. The description described below, which may be the same as or similar to the description of the semiconductor device discussed with reference to fig. 1 and 2A to 2C, may be omitted to the extent that the omitted details may be at least similar to the corresponding elements already discussed.

Referring to fig. 1 and 4A through 4C, an th well region 102, a second well region 104, an impurity layer 110, and a barrier layer 120 may be sequentially formed in a substrate 100. the th well region 102 and the second well region 104 may be formed by doping the substrate 100 with a dopant having a th conductive type (e.g., by performing an ion implantation process). the th conductive type dopant concentration in the second well region 104 may be substantially the same as the th conductive type dopant concentration in the th well region 102. the impurity layer 110 may be formed by doping the substrate 100 with a dopant having a th conductive type, for example, by performing an ion implantation process.the th conductive type dopant concentration in the impurity layer 110 may be greater than the th conductive type dopant concentration in each of the th and second well regions 102 and 104. the barrier layer 120 may be formed adjacent to a surface of the substrate 100. the impurity layer 110 and the barrier layer 120 may be formed by using an ion implantation process in which, for example, oxygen atoms are implanted into the substrate 100.

As discussed with reference to fig. 3, the dopant concentration of the th conductive type in the impurity layer 110 may be distributed as expressed by a dotted line (a) when the subsequent annealing process is performed, the dopant having the th conductive type in the impurity layer 110 may be diffused, and the barrier layer 120 may prevent the diffusion of the dopant having the th conductive type as a result, the dopant having the th conductive type may be diffused from the lower portion 110L of the impurity layer 110 and then may be stacked on the upper portion 110u of the impurity layer 110. after the subsequent annealing process, the dopant concentration of the th conductive type in the impurity layer 110 may be distributed as expressed by a solid line (b) shown in fig. 3.

The semiconductor layer 140 may be formed on the substrate 100. the formation of the semiconductor layer 140 may include performing a selective epitaxial growth process in which the substrate 100 serves as a seed crystal the semiconductor layer 140 may include an intrinsic semiconductor material, for example, the semiconductor layer 140 may include undoped silicon in exemplary embodiments of the inventive concept, the semiconductor layer 140 may have a th thickness T1.

According to example embodiments of the inventive concept, th device isolation patterns 130 may be formed in the semiconductor layer 140 and in the substrate 100. the formation of the th device isolation pattern 130 may include forming th trenches 130T to penetrate portions of the substrate 100 and the semiconductor layer 140, forming th device isolation layers on the semiconductor layer 140 to fill the th trenches 130T, and performing a planarization process on the th device isolation layers until a top surface of the semiconductor layer 140 is exposed. the th trenches 130T may define active regions AR of the substrate 100. the th well regions 102, the second well regions 104, the impurity layers 110, and the barrier layers 120 may be sequentially disposed in the active regions AR, and the semiconductor layer 140 may be disposed on the active regions AR.

Referring to fig. 1 and 5A through 5C, second device isolation patterns 132 may be formed in the semiconductor layer 140 and in the active region AR, the formation of the second device isolation patterns 132 may include forming second trenches 132T to penetrate upper portions of the active region AR and the semiconductor layer 140, the second trenches 132T may separate the semiconductor layer 140 into the initial semiconductor patterns 142 and also separate upper portions of the active region AR into active patterns AP. active patterns AP may extend in a direction D1 and may be spaced apart from each other in a second direction D2 (e.g., a second direction D2 crossing the th direction D1), a direction D1 and a second direction D2 may be parallel to the bottom surface 100B of the substrate 100 and may cross each other, each active pattern AP may protrude upward from a lower portion of the active region AR, for example, well regions 102 may be disposed in a lower portion of the active region AR, the second barrier layer 104, the impurity layer 110, and the well regions 120 may be sequentially disposed in the second active region AP 25 direction p , each active pattern 142 may be spaced apart from each other in the initial semiconductor pattern 4642 direction D .

The formation of the second device isolation pattern 132 may include forming a second device isolation layer on the substrate 100 to fill the second trench 132T and performing a planarization process on the second device isolation layer until the top surface 142 of the initial semiconductor pattern is exposed, according to an exemplary embodiment of the inventive concept, th and upper portions of the second device isolation patterns 130 and 132 may be recessed to expose the initial semiconductor pattern 142.

Referring to fig. 1 and 6A through 6C, a sacrificial gate structure SGS may extend across the initial semiconductor pattern 142 and the th and second device isolation patterns 130 and 132, the sacrificial gate structure SGS may extend in the second direction D2 the sacrificial gate structure SGS may include a sacrificial gate pattern SGP extending in the second direction D2, an etch stop pattern 152 extending along a bottom surface of the sacrificial gate pattern SGP, a mask pattern 150 disposed on a top surface of the sacrificial gate pattern SGP, and a gate spacer GSP disposed on a side surface of the sacrificial gate pattern SGP, for example, the formation of the sacrificial gate structure SGS may include forming an etch stop layer on the substrate 100 to cover the initial semiconductor pattern 142 and the th and second device isolation patterns 130 and 132, forming a sacrificial gate layer on the etch stop layer, forming a mask pattern 150 on the sacrificial gate layer, and sequentially etching the sacrificial gate layer and the etch stop pattern using the mask pattern 150 as an etch stop mask, and forming a sacrificial gate layer and an etch stop pattern 150 on the sacrificial gate layer, and the etch stop pattern may include an etch stop pattern SGP, an etch stop pattern 150, a silicon nitride layer, and an etch stop pattern, for example, an etch stop pattern, a silicon nitride layer, and an etch stop pattern, and a silicon nitride layer, for example, and a silicon nitride layer.

The sacrificial gate structure SGS may be used as an etch mask to pattern each of the preliminary semiconductor patterns 142. Accordingly, the recess regions RR may be formed at opposite sides of the sacrificial gate structure SGS, and the semiconductor pattern SP may be formed under the sacrificial gate structure SGS. For example, the recessed regions RR may be disposed between adjacent sacrificial gate structures SGS. The recess region RR may expose a side surface of the semiconductor pattern SP. According to an exemplary embodiment of the inventive concept, each active pattern AP may be recessed during the formation of the recess region RR. Each recess region RR may expose the impurity layer 110 and/or the barrier layer 120. For example, each recess region RR may penetrate the barrier layer 120 and expose the impurity layer 110. For example, each recess region RR may partially penetrate the impurity layer 110.

Referring to fig. 1 and 7A through 7C, the formation of the source/drain pattern SD. the source/drain pattern SD may be formed in the corresponding recess region RR may include performing a selective epitaxial growth process in which the semiconductor pattern SP and each active pattern AP serve as a seed, the source/drain pattern SD may include one or more of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC), for example, the formation of the source/drain pattern SD may further include implanting a dopant having a second conductive type into the source/drain pattern SD. with the dopant having a second conductive type during or after the selective epitaxial growth process may be different from a dopant having a conductive type, for example, when the conductive type is an N type, the second conductive type may be a P type, and when the conductive type is a P type, the second conductive type may be an N type.

According to an exemplary embodiment of the inventive concept, each of the source/drain patterns SD may contact the impurity layer 110 and/or the blocking layer 120. Each of the source/drain patterns SD may penetrate the barrier layer 120 and contact the impurity layer 110. For example, each of the source/drain patterns SD may partially penetrate the impurity layer 110. For example, each of the source/drain patterns SD may have a lowermost bottom surface SD _ B at a height higher than that of the bottom surface 110B of the impurity layer 110 with respect to the substrate 100. However, the inventive concept is not limited thereto. For example, the lowermost bottom surface SD _ B of each source/drain pattern SD may be located at substantially the same height as the height of the bottom surface 110B of the impurity layer 110.

The source/drain patterns SD may be disposed on opposite sides of the sacrificial gate structure SGS and may be spaced apart from each other in an -th direction D1 across the semiconductor patterns SP, for example, the source/drain patterns SD may be disposed between adjacent sacrificial gate structures SGS, the source/drain patterns SD and the semiconductor patterns SP may constitute an active structure AS. interlayer dielectric layer 200 may be formed on the substrate 100 covering the sacrificial gate structure SGS and the active structure AS.

Referring to fig. 1 and 8A through 8C, a gap 160 may be formed in the interlayer dielectric layer 200, the gap 160 may be formed by removing the mask pattern 150, the sacrificial gate pattern SGP, and the etch stop pattern 152, for example, the formation of the gap 160 may include performing a planarization process on the interlayer dielectric layer 200, the mask pattern 150, and the gate spacer GSP until the sacrificial gate pattern SGP is exposed, the formation of the gap 160 may further include removing the sacrificial gate pattern SGP by performing an etch process having an etch selectivity with respect to the etch stop pattern 152 and the gate spacer GSP, and removing the etch stop pattern 152 by performing an etch process having an etch selectivity with respect to the semiconductor pattern SP and the gate spacer GSP, the gap 160 may expose an inner surface of the gate spacer GSP contacting the sacrificial gate structure SGS, the gap 160 may expose a top surface and a side surface of the semiconductor pattern SP, and also expose top surfaces of the and the second device isolation patterns 130 and 132.

Referring to fig. 1 and 2A to 2C, a gate structure GS may be formed in the gap 160. For example, the formation of the gate structure GS may include sequentially forming a gate dielectric layer and a gate electrode layer on the interlayer dielectric layer 200 to fill the gap 160. The forming of the gate structure GS may further include: a planarization process is performed on the gate dielectric layer and the gate electrode layer to form a gate dielectric pattern GI and a gate electrode GE, and a gate cover pattern CAP is formed on a top surface of the gate electrode GE in the gap 160. For example, the formation of the gate capping pattern CAP may include: forming empty spaces in the interlayer dielectric layer 200 by recessing upper portions of the gate electrode GE, the gate dielectric pattern GI, and the gate spacer GSP, forming a gate capping layer on the interlayer dielectric layer 200 to fill the empty spaces overlapping each upper portion of the gate electrode GE, and performing a planarization process on the gate capping layer until the interlayer dielectric layer 200 is exposed.

According to an exemplary embodiment of the inventive concept, source/drain contacts may be formed in the interlayer dielectric layer 200. The forming of the source/drain contact may include: contact holes are formed in the interlayer dielectric layer 200 to expose the corresponding source/drain patterns SD, a conductive layer is formed on the interlayer dielectric layer 200 to fill the contact holes, and a planarization process is performed on the conductive layer until the interlayer dielectric layer 200 is exposed. A gate contact may be formed on the interlayer dielectric layer 200 to be connected with the gate electrode GE.

Fig. 9A, 9B and 9C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of fig. 1, respectively, illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. The following semiconductor devices may be the same as or similar to the semiconductor devices discussed with reference to fig. 1 and 2A to 2C, and thus, differences between the semiconductor devices may be described below, and details may be omitted to the extent that they may be at least similar to the corresponding elements already discussed.

Referring to fig. 1 and 9A to 9C, a barrier layer 120 may be interposed between the impurity layer 110 and the semiconductor pattern SP. Each of the source/drain patterns SD may contact the impurity layer 110 and/or the barrier layer 120. According to an exemplary embodiment of the inventive concept, each of the source/drain patterns SD may penetrate the barrier layer 120 and the impurity layer 110. A lowermost bottom surface SD _ B of each source/drain pattern SD may be located at a height lower than that of a bottom surface 110B of the impurity layer 110 with respect to an upper surface of the substrate 100.

The second device isolation patterns 132 may be disposed at opposite sides of each active structure AS. For example, each of the second device isolation patterns 132 may be disposed between adjacent active structures AS. According to an exemplary embodiment of the inventive concept, the second device isolation pattern 132 may expose the semiconductor pattern SP and an upper portion of each active pattern AP. The active fin AF may refer to an upper portion of the semiconductor pattern SP and each active pattern AP exposed by the second device isolation pattern 132. The second device isolation pattern 132 may expose an upper portion of each source/drain pattern SD. The top surface 132U of the second device isolation pattern 132 may be located at a height lower than that of the top surface SP _ U of the semiconductor pattern SP, and the second device isolation pattern 132 may expose the side surface SP _ S of the semiconductor pattern SP and the side surface of each active pattern AP.

The gate structure GS may extend in the second direction D2 and may cover the semiconductor pattern SP of each active structure AS. According to an exemplary embodiment of the inventive concept, the gate structure GS may cover the top surface SP _ U and the side surface SP _ S of the semiconductor pattern SP and also cover the side surface of each active pattern AP. For example, the gate electrode GE may cover the top surface SP _ U and the side surface SP _ S of the semiconductor pattern SP and also cover the side surface of each active pattern AP. For example, the gate electrode GE may partially cover the side surface of each active pattern AP. The gate dielectric pattern GI may be interposed between the gate electrode GE and the top surface SP _ U of the semiconductor pattern SP and between the gate electrode GE and the side surface SP _ S of the semiconductor pattern SP, and may extend between the gate electrode GE and the side surface of each active pattern AP.

According to an exemplary embodiment of the inventive concept, each of the source/drain patterns SD may penetrate the impurity layer 110 and the barrier layer 120, and the lowest bottom surface SD _ B of each of the source/drain patterns SD may be located at a height lower than that of the bottom surface 110B of the impurity layer 110. In this case, the impurity layer 110 and the barrier layer 120 may inhibit the diffusion of the dopant having the second conductive type in the source/drain pattern SD. As a result, the short-channel effect and punch-through of the transistor can be suppressed.

Fig. 10A to 12A illustrate cross-sectional views taken along line I-I' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 10B to 12B illustrate cross-sectional views taken along line II-II' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 10C to 12C illustrate cross-sectional views taken along line III-III' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. The following semiconductor devices may be the same as or similar to the semiconductor devices discussed with reference to fig. 4A to 8A, 4B to 8B, and 4C to 8C, and thus, differences between the semiconductor devices may be described below for the sake of simplifying the description.

Referring to fig. 1 and 10A to 10C, a semiconductor layer 140 may be formed on a substrate 100. the semiconductor layer 140 may include an intrinsic semiconductor material according to an exemplary embodiment of the inventive concept, the semiconductor layer 140 may have a relatively small thickness, for example, the semiconductor layer 140 may have a second thickness T2 less than an th thickness T1 (see, for example, fig. 4A, 4B, and 4C).

The th trench 130T may penetrate through the portion of the substrate 100 and the semiconductor layer 140, and the th device isolation pattern 130 may be formed in the corresponding th trench 130T the th trench 130T may define an active region AR of the substrate 100 the th well region 102, the second well region 104, the impurity layer 110, and the barrier layer 120 may be sequentially disposed in the active region AR, and the semiconductor layer 140 may be disposed on the active region AR of the substrate 100.

Referring to fig. 1 and 11A to 11C, second trenches 132T may penetrate the upper portions of the active regions AR and the semiconductor layer 140, and may form second device isolation patterns 132 in the corresponding second trenches 132T, the second trenches 132T may separate the semiconductor layer 140 into initial semiconductor patterns 142, and also separate the upper portions of the active regions AR into active patterns AP. each of which may protrude upward from the lower portion of the active regions AR, the initial semiconductor patterns 142 may be disposed on the corresponding active patterns AP, according to an exemplary embodiment of the inventive concept, the upper portions of the th and second device isolation patterns 130 and 132 may be recessed, and the initial semiconductor patterns 142 and the upper portions of each of the active patterns AP may be exposed.

Referring to fig. 1 and 12A through 12C, a sacrificial gate structure SGS may extend across the preliminary semiconductor pattern 142 and the th and second device isolation patterns 130 and 132, for example, the sacrificial gate structure SGS may overlap the preliminary semiconductor pattern 142 and the th and second device isolation patterns 130 and 132, according to an exemplary embodiment of the inventive concept, the sacrificial gate structure SGS may be used as an etch mask to pattern an upper portion of each preliminary semiconductor pattern 142 and each active pattern AP.

The subsequent processes may be the same as or similar to the processes discussed with reference to fig. 1, 7A to 7C, and 8A to 8C according to exemplary embodiments of the inventive concept.

Fig. 13A, 13B and 13C are cross-sectional views taken along lines I-I ', II-II ' and III-III ' of fig. 1, respectively, showing a semiconductor device according to an exemplary embodiment of the inventive concept. The following semiconductor devices may be the same as or similar to the semiconductor devices discussed with reference to fig. 1 and 2A to 2C, and therefore, differences between the semiconductor devices will be described below, and details will be omitted to the extent that they may be at least similar to the corresponding elements already discussed.

Referring to fig. 1 and 13A to 13C, an active structure AS. an active structure AS may be disposed on a substrate 100 may be disposed on a corresponding active pattern AP and may extend in a th direction D1 each of the active structures AS may include a semiconductor pattern SP and a source/drain pattern SD. according to an exemplary embodiment of the inventive concept, the semiconductor pattern SP may extend in an th direction D1, and each of the source/drain patterns SD may be disposed on the semiconductor pattern SP.

The semiconductor pattern SP may be an epitaxial pattern grown from the substrate 100 serving as a seed. The semiconductor pattern SP may include an intrinsic semiconductor material. According to an exemplary embodiment of the inventive concept, the source/drain pattern SD may be an epitaxial pattern grown from the semiconductor pattern SP serving as a seed.

According to an exemplary embodiment of the inventive concept, the impurity layer 110 may extend between the second well region 104 and each source/drain pattern SD, and the barrier layer 120 may extend between the impurity layer 110 and each source/drain pattern SD.

The second device isolation patterns 132 may be disposed at opposite sides of each active structure AS. For example, the second device isolation pattern 132 may be disposed between adjacent active structures AS. According to an exemplary embodiment of the inventive concept, the second device isolation pattern 132 may expose an upper portion of the semiconductor pattern SP. In addition, the second device isolation pattern 132 may expose an upper portion of each source/drain pattern SD. The active fin AF may refer to an upper portion of the semiconductor pattern SP exposed by the second device isolation pattern 132. The semiconductor pattern SP may have a lower portion between the adjacent second device isolation patterns 132.

According to an exemplary embodiment of the inventive concept, each of the source/drain patterns SD may be spaced apart from the barrier layer 120 and the impurity layer 110. In this case, portions of the source/drain patterns SD and the semiconductor patterns SP interposed between the source/drain patterns SD may be less or minimally affected by the dopants included in the barrier layer 120 and the impurity layer 110. In addition, the impurity layer 110 and the barrier layer 120 may suppress diffusion of the dopant having the second conductive type in the source/drain pattern SD, and thus, a short channel effect and diffusion of the dopant from the transistor may be suppressed.

Fig. 14A to 16A illustrate cross-sectional views taken along line I-I' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 14B to 16B illustrate cross-sectional views taken along line II-II' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 14C to 16C illustrate cross-sectional views taken along line III-III' of fig. 1, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. The following semiconductor devices may be the same as or similar to the semiconductor devices discussed with reference to fig. 4A to 8A, 4B to 8B, and 4C to 8C, and thus, differences between the semiconductor devices will be described below for the sake of simplifying the description.

Referring to fig. 1 and 14A through 14C, a semiconductor layer 140 may be formed on a substrate 100, the semiconductor layer 140 may include an intrinsic semiconductor material according to an exemplary embodiment of the inventive concept, the semiconductor layer 140 may be relatively thick, for example, the semiconductor layer 140 may have a third thickness T3 greater than an th thickness T1 (see, e.g., fig. 4A, 4B, and 4C).

The th trench 130T may penetrate through the portion of the substrate 100 and the semiconductor layer 140, and the th device isolation pattern 130 may correspond to the th trench 130T. the th trench 130T may define an active area AR of the substrate 100. the th well region 102, the second well region 104, the impurity layer 110, and the barrier layer 120 may be sequentially disposed in the active area AR of the substrate 100, and the semiconductor layer 140 may be disposed on the active area AR.

Referring to fig. 1 and 15A through 15C, second trenches 132T may penetrate upper portions of active regions AR and the semiconductor layer 140, and second device isolation patterns 132 may be formed in the corresponding second trenches 132T, the second trenches 132T may separate the semiconductor layer 140 into initial semiconductor patterns 142, in addition, the second trenches 132T may separate upper portions of the active regions AR into active patterns AP. each of which may protrude upward from a lower portion of the active regions AR, for example, each of the active patterns AP may extend vertically with respect to an upper surface of the substrate 100, the initial semiconductor patterns 142 may be disposed on the corresponding active patterns AP, according to an exemplary embodiment of the inventive concept, upper portions of th and second device isolation patterns 130 and 132 may be recessed to expose upper portions of each of the initial semiconductor patterns 142, for example, top and side surfaces of each of the initial semiconductor patterns 142 may be exposed.

Referring to fig. 1 and 16A through 16C, a sacrificial gate structure SGS may extend across the preliminary semiconductor pattern 142 and the th and second device isolation patterns 130 and 132 according to an exemplary embodiment of the inventive concept, the sacrificial gate structure SGS may be used as an etch mask to pattern an upper portion of each preliminary semiconductor pattern 142, and thus, recess regions RR may be formed at opposite sides of the sacrificial gate structure SGS, and semiconductor patterns SP may be formed under the sacrificial gate structure SGS.

The subsequent processes may be the same as or similar to the processes discussed with reference to fig. 1, 7A to 7C, and 8A to 8C.

According to an exemplary embodiment of the inventive concept, the impurity layer 110 and the blocking layer 120 may be disposed adjacent to the semiconductor pattern SP and the source/drain pattern SD, and may suppress diffusion of the dopant having the second conductive type in the source/drain pattern SD. Accordingly, it is possible to suppress short channel effects of the transistor and prevent diffusion between the source/drain patterns SD. In addition, since the semiconductor layer 140 may have a relatively small or large thickness, the source/drain pattern SD may penetrate the impurity layer 110 and the barrier layer 120 or may be spaced apart from the impurity layer 110 and the barrier layer 120. Accordingly, the degree to which the source/drain patterns SD and the semiconductor patterns SP are affected by the dopant may be controlled by the barrier layer 120 and the impurity layer 110.

According to an exemplary embodiment of the inventive concept, the impurity layer and the barrier layer may be formed adjacent to the semiconductor pattern and the source/drain pattern, and diffusion of a dopant in the source/drain pattern may be suppressed. Accordingly, a short channel effect of a transistor including the semiconductor pattern and the source/drain pattern may be suppressed, and punch-through between the source/drain patterns may be prevented. For example, the semiconductor device may have improved electrical characteristics.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept.

This application claims priority from korean patent application No. 10-2018-0083892, filed on 19.7.2018 with the korean intellectual property office, the entire contents of which are incorporated herein by reference.