阅读说明：本技术 一种采样保持电路 (kinds of sampling hold circuit ) 是由 卢萍 张俊亭 张兴 徐泽锋 陈强 董宇 王玉宝 丁帅 候飞 于 2019-10-21 设计创作，主要内容包括：本发明实施例提供了一种采样保持电路,包括采样保持模块、模式选择模块、脉冲发生模块、计数模块和复位模块,其中,采样保持模块分别与直流正向电源、第一滤波电容的一端、模式选择模块、直流负向电源、脉冲发生模块中的与非门的第一输入端和复位模块连接；模式选择模块分别与直流正向电源和与非门的第一输入端连接；脉冲发生模块分别与直流正向电源和计数模块连接；计数模块与复位模块连接；复位模块与计数模块中的与门的第一单元输出端连接；与门和与非门均是采用集成芯片制成的。本发明实施例可以减小电路体积,提高功率密度,具有良好的灵敏性与线性特性,并且,通过脉冲与计数器定时,可实现任意时间的信号保持,增加了信号输出的可靠性。(The embodiment of the invention provides sample-and-hold circuits, which comprise a sample-and-hold module, a mode selection module, a pulse generation module, a counting module and a reset module, wherein the sample-and-hold module is respectively connected with a direct-current positive power supply, a end of a filter capacitor, the mode selection module, a direct-current negative power supply, a input end of a NAND 0 in the pulse generation module and the reset module, the mode selection module is respectively connected with the direct-current positive power supply and a input end of the NAND , the pulse generation module is respectively connected with the direct-current positive power supply and the counting module, the counting module is connected with the reset module, the reset module is connected with an output end of a unit of the in the counting module, and the and the NAND are both made of integrated chips.)

The sample-hold circuit of 1, kinds is characterized in that it includes sample-hold module, mode selection module, pulse generation module, counting module and reset module,

the sample-and-hold module is respectively connected with a direct-current positive power supply, a terminal of an th filter capacitor, the mode selection module, a direct-current negative power supply, a th input terminal of a NAND in the pulse generation module and the reset module;

the mode selection module is respectively connected with the direct current positive power supply and a input end of the NAND ;

the pulse generation module is respectively connected with the direct-current forward power supply and the counting module;

the counting module is connected with the resetting module;

the reset module is connected with the output end of the unit of the counting module which is connected with ;

the and and the nand are both fabricated using integrated chips.

2. The sample-and-hold circuit of claim 1, wherein the sample-and-hold module comprises: the device comprises a power supply positive input end, a bias adjusting end, a power supply negative input end, a logic reference end, a maintaining signal input end, a logic input end, a signal input end and a signal output end;

the mode selection module comprises: a comparator and a reference resistor;

the pulse generating module comprises a two-way monostable trigger, a frequency reference resistor, a frequency reference capacitor and a NAND ;

the counting module comprises a double-output counter chip and an chip;

the reset module includes: and a switch tube.

3. The sample-and-hold circuit of claim 2, wherein the supply positive input is connected to a dc positive supply and to terminal of an th filter capacitor;

the bias adjusting end is connected with the zero setting resistor;

the negative input end of the power supply is connected with a direct-current negative power supply and a second filter capacitor;

the logic reference end is connected with an th reference resistor and a second reference resistor;

the maintaining signal input end is connected with an end of a maintaining capacitor and a collector electrode of the reset module;

the logic input end is connected with the output end of the comparator;

the other end of the th reference resistor is connected with the direct current positive power supply;

the second reference resistor is connected with the analog ground, the end of the holding capacitor and the radioactive electrode of the reset module;

the signal input end is connected with an input voltage signal and the positive input end of the comparator;

the signal output terminal is connected with the negative input terminal of the comparator, the th input terminal of the NAND and the th enabling terminal of the pulse generator.

4. The sample-and-hold circuit of claim 3, wherein the power supply input of the comparator is connected to the DC positive supply, of the th reference resistor;

the negative input end of the comparator is connected with the th input end of the NAND ;

the output end of the comparator is connected with the other end of the th reference resistor and the end of the second reference resistor.

5. The sample-and-hold circuit of claim 4, wherein the power input of the two-way monostable flip-flop is connected to the DC positive supply, of an th frequency reference resistor, of a second frequency reference resistor, the reset of the second cell, and the negative input of the second cell;

the resistor input end of the th unit is connected with the other end of the th frequency reference resistor and the end of the th frequency reference capacitor;

the capacitor input end of the th unit is connected with the other end of the th frequency reference capacitor;

the reset terminal of the unit is connected with the output terminal of the sample-and-hold module and the input terminal of the NAND ;

the positive input end of the th unit is digitally connected with the ground end of the two-way monostable trigger and the ground end of the counting module;

the negative input end of the unit is connected with the output end of the NAND ;

the positive output terminal of the th unit is connected with the positive output terminal of the second unit;

a negative output terminal of the cell is connected to a second input terminal of the NAND ;

the resistance input end of the second unit is connected with another end of the second frequency reference resistance and end of the second frequency reference capacitance;

the capacitance input end of the second unit is connected with another end of the second frequency reference capacitance;

the negative output terminal of the second unit is connected with the th enabling terminal of the counting module.

6. The sample-and-hold circuit of claim 5, wherein the enable terminal of the th cell is connected to the negative going output terminal of the second cell;

the clock signal of the second cell is connected with the th cell output signal of the AND ;

and the reset signal output end of the second unit is connected with the second unit output end of the AND and the base of the reset module.

7. The sample-and-hold circuit of claim 6, wherein the collector of the switch tube is connected to terminal of the sustain capacitor, the input terminal of the sustain capacitor of the sample-and-hold module;

the emitter is connected to the other terminal of the holding capacitor, the other terminal of the second reference resistor, and the analog ground;

the base is connected to the second cell reset signal output terminal, the th cell output terminal of the AND .

8. The sample-and-hold circuit of claim 1, wherein a sample-and-hold time of the sample-and-hold circuit is jointly determined by the pulse generation module and the counting module.

9. The sample-and-hold circuit of claim 8, wherein the hold time is expressed by the following equation:

t ( th rc value, th rc value, second rc value) x decimal digit/2, where T is the sample-hold time.

10. The sample-and-hold circuit of claim 3, wherein the DC positive power supply and the DC negative power supply are both DC voltage sources, and the switch tube is a fully-controlled device.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to sample-and-hold circuits.

Background

In industrial control or automatic detection of aerospace and the like, some signals are required to be collected, but the maintaining time of some signals (such as Hall induction current and the like) is short or disappears suddenly, the situation that the signals cannot be collected occurs during reading of the later stage, and the collected signals need to be kept until the later stage can receive the signals, so that the reliability of the system can be improved, and how to keep the collected signals is realized, and the keeping time is adjusted according to the requirement is particularly important.

The existing sampling hold circuit adopts an operational amplifier, a diode, a capacitor and software to control the hold time and reset, and the mode has the following defects: 1. the reliability is insufficient; 2. the diode results in a sample and hold circuit that is insensitive to small signals and not highly linear.

Disclosure of Invention

The invention solves the technical problems that the sample-and-hold circuit in the prior art has insufficient reliability, and the sample-and-hold circuit is insensitive to small signals and has low linearity, and provides sample-and-hold circuits.

In order to solve the above problem, an embodiment of the present invention provides sample-and-hold circuits, including a sample-and-hold module, a mode selection module, a pulse generation module, a counting module, and a reset module, wherein,

the sample-and-hold module is respectively connected with a direct-current positive power supply, a terminal of an th filter capacitor, the mode selection module, a direct-current negative power supply, a th input terminal of a NAND in the pulse generation module and the reset module;

the mode selection module is respectively connected with the direct current positive power supply and a input end of the NAND ;

the pulse generation module is respectively connected with the direct current positive power supply, a input end of the NAND , the counting module and an output end of the NAND ;

the counting module is connected with the resetting module;

the reset module is connected with the output end of the unit of the counting module which is connected with ;

the and and the nand are both fabricated using integrated chips.

Preferably, the sample-and-hold module comprises: the device comprises a power supply positive input end, a bias adjusting end, a power supply negative input end, a logic reference end, a maintaining signal input end, a logic input end, a signal input end and a signal output end;

the mode selection module comprises: a comparator and a reference resistor;

the pulse generating module comprises a two-way monostable trigger, a frequency reference resistor, a frequency reference capacitor and a NAND ;

the counting module comprises a double-output counter chip and an chip;

the reset module includes: and a switch tube.

Preferably, the positive input end of the power supply is connected with a direct current positive power supply and the end of an th filter capacitor;

the bias adjusting end is connected with the zero setting resistor;

the negative input end of the power supply is connected with a direct-current negative power supply and a second filter capacitor;

the logic reference end is connected with an th reference resistor and a second reference resistor;

the maintaining signal input end is connected with an end of a maintaining capacitor and a collector electrode of the reset module;

the logic input end is connected with the output end of the comparator;

the other end of the th reference resistor is connected with the direct current positive power supply;

the second reference resistor is connected with the analog ground, the end of the holding capacitor and the radioactive electrode of the reset module;

the signal input end is connected with an input voltage signal and the positive input end of the comparator;

the signal output terminal is connected with the negative input terminal of the comparator, the th input terminal of the NAND and the th enabling terminal of the pulse generator.

Preferably, the power supply input end of the comparator is connected with the direct current positive power supply and the end of the th reference resistor;

the negative input end of the comparator is connected with the th input end of the NAND ;

the output end of the comparator is connected with the other end of the th reference resistor and the end of the second reference resistor.

Preferably, a power supply input end of the two-way monostable flip-flop is connected with the direct-current positive power supply, a end of an th frequency reference resistor, a end of a second frequency reference resistor, a reset end of a second unit and a negative input end of the second unit;

the resistor input end of the th unit is connected with the other end of the th frequency reference resistor and the end of the th frequency reference capacitor;

the capacitor input end of the th unit is connected with the other end of the th frequency reference capacitor;

the reset terminal of the unit is connected with the output terminal of the sample-and-hold module and the input terminal of the NAND ;

the positive input end of the th unit is digitally connected with the ground end of the two-way monostable trigger and the ground end of the counting module;

the negative input end of the unit is connected with the output end of the NAND ;

the positive output terminal of the th unit is connected with the positive output terminal of the second unit;

a negative output terminal of the cell is connected to a second input terminal of the NAND ;

the resistance input end of the second unit is connected with another end of the second frequency reference resistance and end of the second frequency reference capacitance;

the capacitance input end of the second unit is connected with another end of the second frequency reference capacitance;

the negative output terminal of the second unit is connected with the th enabling terminal of the counting module.

Preferably, the enable terminal of the th unit is connected with the negative output terminal of the second unit;

the clock signal of the second cell is connected with the th cell output signal of the AND ;

and the reset signal output end of the second unit is connected with the second unit output end of the AND and the base of the reset module.

Preferably, the collector of the switch tube is connected with the terminal of the holding capacitor and the input terminal of the holding capacitor of the sample-and-hold module;

the emitter is connected to the other terminal of the holding capacitor, the other terminal of the second reference resistor, and the analog ground;

the base is connected to the second cell reset signal output terminal, the th cell output terminal of the AND .

Preferably, the sample-and-hold time of the sample-and-hold circuit is determined by both the pulse generation module and the counting module.

Preferably, the holding time is expressed by the following formula:

t ( th rc value, th rc value, second rc value) x decimal digit/2, where T is the sample-hold time.

Preferably, the direct-current positive power supply and the direct-current negative power supply are both direct-current voltage sources, and the switching tube is a fully-controlled device.

Compared with the prior art, the invention has the advantages that: the sampling hold circuit provided by the embodiment of the invention adopts the integrated chip, can reduce the volume, improve the power density, has good sensitivity and linear characteristics, can realize signal holding at any time by timing of the pulse and the counter, and increases the reliability of signal output.

Drawings

Fig. 1 is a schematic structural diagram of sample-and-hold circuits according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of sample-and-hold circuits according to an embodiment of the present invention;

fig. 3 is a schematic diagram of sample-and-hold circuits in the prior art.

Detailed Description

Referring to fig. 1, a schematic diagram of structures of sample-and-hold circuits provided by an embodiment of the present invention is shown.

As shown in fig. 1, the sample-and-hold circuit may include: a sample-and-hold module 100, a mode selection module 200, a pulse generation module 300, a counting module 400, and a reset module 500, wherein,

the sample-and-hold module 100 is respectively connected to the dc positive power supply, the terminal of the th filter capacitor, the mode selection module 200, the dc negative power supply, the th input terminal of the nand in the pulse generation module 300, and the reset module 500;

the mode selection module 200 is respectively connected with a direct current positive power supply and the input end of the NAND ;

the pulse generating module 300 is respectively connected with the direct current positive power supply and the counting module 400;

the counting module 400 is connected with the reset module 500;

the reset module 500 is connected to the output of the th cell of in the count module 400;

and and nand are both fabricated using integrated chips.

The sampling hold circuit provided by the embodiment of the invention adopts the integrated chip, can reduce the volume, improve the power density, has good sensitivity and linear characteristics, can realize signal holding at any time by timing of the pulse and the counter, and increases the reliability of signal output.

Next, the structure of the sample-and-hold circuit provided by the embodiment of the present invention is described in detail with reference to fig. 2.

Referring to fig. 2, a schematic diagram of structures of sample-and-hold circuits provided by the embodiment of the invention is shown.

As shown in fig. 1 and 2, the sample-and-hold circuit includes a sample-and-hold module 100, a mode selection module 200, a pulse generation module 300, a counting module 400, and a reset module 500, where + VCC is a dc positive power supply, -VCC is a dc negative power supply, Vin is an input voltage signal, Vout is an output voltage signal, SGND is an analog signal ground, and DGND is a digital signal ground.

The sample-and-hold module 100 may be composed of a sample-and-hold chip LF198H, zero resistors R1 and R2, reference resistors R3 and R4, a holding capacitor Ch, and filter capacitors C1 and C2.

Mode select block 200 may be comprised of comparator LM193 and reference resistors R5 and R6.

The pulse generation module 300 may be composed of a two-way monostable flip-flop CC4098, frequency reference resistors R7 and R8, and frequency reference capacitors C3 and C4.

The counting module 400 can adopt a dual output counter chip CC4518, an integrated chip CC4070 for AND , and an integrated chip CC4011 for NAND .

The mode selection module 500 is formed by a comparator and a reference resistor.

The positive power supply input terminal (i.e., pin 1 of LF 198) of the sample-and-hold module 100 is connected to the terminals of the dc positive power supply and the third filter capacitor C, the other 2 of the 0 th filter capacitor C is connected to ground, the bias adjustment terminal (i.e., pin 2 of LF 198) is connected to the zero-setting resistor R, R and R are connected in series, the other 3 terminals of the zero-setting resistor R are connected to ground, the negative power supply input terminal (i.e., pin 4 of LF 198) is connected to the dc negative power supply and the second filter capacitor C, the other terminal of the second filter capacitor C is connected to ground, the logical reference terminal (i.e., pin 7 of LF 198) is connected to the first reference resistor R and the second reference resistor R, the input terminal of the sustain signal (i.e., pin 6 of LF 198) is connected to the terminal of the sustain capacitor Ch and the collector of the reset module Q, the logical input terminal (i.e., pin 8 of LF 198) is connected to the output terminal (i.e., pin 1 of the LM 193) of the mode selection module 200, the other terminal of the first reference resistor R is connected to the positive power supply + of the dc positive power supply, the second reference resistor R is connected to the analog ground, the sustain capacitor VCC terminal, the negative ground, the sustain capacitor 193, the negative terminal of the sustain module R is connected to the negative terminal of the reset module Ch 198, i.e., pin 3, the negative terminal of the reset module R, i.e., pin 3, the negative terminal of the negative.

The power input terminal of the comparator (i.e., pin 8 of LM 193) is connected to the dc positive power supply + VCC, the terminal of the th reference resistor R5, the ground terminal of the comparator (i.e., pin 4 of LM 193) is connected to the analog ground SGND, the negative input terminal of the comparator (i.e., pin 2 of LM 193) is connected to the output terminal of the sample-and-hold module 100 (i.e., pin 5 of LF 198H), the th input terminal of the nand (i.e., pin 1 of CC 4011), the positive input terminal of the comparator (i.e., pin 3 of LM 193) is connected to the input signal Vin, the signal input terminal of the sample-and-hold module 100 (i.e., pin 3 of LF 198H), the output terminal of the comparator (i.e., pin 1 of LM 193) is connected to the logic input terminal of the sample-and-hold module 100 (i.e., pin 8 of LF 198H), the other terminal of the th reference resistor R5, and the 733 terminal of the second reference resistor R6 is.

The pulse generating module 300 may be composed of a two-way monostable flip-flop, a frequency reference resistor, a frequency reference capacitor, and a nand, where a power input terminal (i.e., pin 16 of CC 4098) of the two-way monostable flip-flop is connected to a dc positive power supply + VCC, a 0 terminal of a second frequency reference resistor R, a 1 terminal of the second frequency reference resistor R, a reset terminal (i.e., pin 13 of CC 4098), and a negative input terminal (i.e., pin 11 of CC 4098) of the second cell, a 2 terminal of a 2 nd cell resistor (i.e., pin 2 of CC 4098) is connected to another 5 terminal of a 4 th frequency reference resistor R and an 8 terminal of a 6 th frequency reference capacitor C, a 9 th cell capacitor input terminal (i.e., pin 1 of CC 4098) is connected to another 1 terminal of a second frequency reference capacitor C, a 3 terminal of the 2 nd cell reset terminal (i.e., pin 3 of CC 4098) is connected to an output terminal (i.e., pin 5 of the sample and hold module 100), a 3 rd input terminal (i.e., pin 1 of non-ground terminal of CC 4091 of LF 3, a non-ground terminal of the non-cell 4011, a 4 th cell counter, a positive pin of the second cell counter, a positive counter-reference resistor, a positive input terminal of a counter-.

The counting module 400 may be composed of a dual output counter chip and an chip, wherein the th cell enable terminal (i.e., pin 2 of CC 4518) is connected to the second cell negative output terminal (i.e., pin 9 of CC 4098) of the pulse generating module 300, the second cell clock signal (i.e., pin 15 of CC 4518) is connected to the th cell output terminal (i.e., pin 3 of CC 4081) of , and the second cell reset signal output terminal (i.e., pin 9 of CC 4518) is connected to the second cell output terminal (i.e., pin 4 of CC 4081) and the base of the reset module 500.

The reset module 500 is composed of a switch transistor, a collector of the switch transistor Q2 is connected to the terminal of the holding capacitor Ch and the input terminal of the holding capacitor of the sample-and-hold module 100 (i.e., pin 6 of LF 198H), an emitter of the switch transistor Q2 is connected to the other terminal of the holding capacitor Ch, the other terminal of the second reference resistor R4 and the analog ground SGND, and a base of the switch transistor Q2 is connected to the second unit reset signal output terminal of the count module 400 (i.e., pin 15 of CC 4081) and the output terminal of the unit of (i.e., pin 3 of CC 4081).

In preferred embodiments of the present invention, the sample-and-hold time of the sample-and-hold circuit based on an integrated chip is determined by the pulse generation module and the counting module, and the sample-and-hold time is T ( frequency resistance value, frequency capacitance value + second frequency resistance value, second frequency capacitance value) x binary digit/2, where T is the sample-and-hold time.

In another preferred embodiments of the present invention, the counting module can be composed of a counter and a counter , which can be connected to form an arbitrary bit number counter.

In another preferred embodiments of the present invention, the positive DC power supply and the negative DC power supply are both DC voltage sources.

In another preferred embodiments of the present invention, the switching tube is a fully controlled device.

The sampling hold circuit based on the integrated chip can realize the holding of a sampling signal at any time, can realize integration and miniaturization, can play an important role in the corresponding control fields of industrial production, transportation, communication systems, electric power systems, new energy systems, various power supply systems, aerospace and the like, is suitable for application occasions of high-speed narrow-pulse signal acquisition and signal hold function realization, and greatly improves the reliability of sampling control.

The researchers have proposed a sample-and-hold circuit composed of integrated operational amplifiers, as shown in fig. 3, the sample-and-hold module uses the operational amplifier as a follower, and uses the unidirectional conductivity of a diode to sample and hold the input signal, but the actual diode has a large difference from the ideal diode characteristic, and there is a dead zone voltage in the forward characteristic, and the input signal can be conducted only when the amplitude of the input signal is larger than the conduction voltage of the diode, and the input signal can charge the capacitor through the diode to realize the hold, which limits the sensitivity and the linear characteristic of the circuit for processing small signals.

The invention realizes that the sampling mode is entered when the input voltage rises by using the integrated chip through the sampling and holding module and the mode selection module, the output voltage rises along with the rise of the input voltage, and the output voltage is kept as the peak value when the input voltage falls. The diode has no influence of conduction voltage drop of the diode, and has good sensitivity and linear characteristics. The pulse generation module sends out fixed frequency pulse, the counter module realizes timing through counting pulse, the timing is finished and counting is stopped, and simultaneously, the pulse is sent out to reset the reset module, so that the sampling and holding of signals are realized.

In summary, compared with the prior art, the invention has the following advantages: the sampling hold circuit adopts an integrated chip to reduce the volume, improve the power density, have good sensitivity and linear characteristics, can realize signal hold at any time by timing of a pulse and a counter, and increase the reliability of signal output.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions and scope of the present invention as defined in the appended claims.