阅读说明：本技术 一种脉冲锁存单元结构 (pulse latch unit structure ) 是由 白雨鑫 陈鑫 张颖 刘小雨 高翔 毛志明 单永欣 马丽萍 姚嘉祺 陈凯 施聿哲 于 2019-11-18 设计创作，主要内容包括：本发明涉及种脉冲锁存单元结构,包含第一PMOS管、第一NMOS管、第二PMOS管、第二NMOS管和门控单元DUC,实现了对输入信号的锁存功能。本发明可广泛应用在构建锁存器的结构中,适用于对锁存器的可靠性及综合开销要求较高的领域。(The invention relates to a pulse latch unit structure which comprises a PMOS (P-channel metal oxide semiconductor) transistor, a NMOS (N-channel metal oxide semiconductor) transistor, a second PMOS transistor, a second NMOS transistor and a control unit DUC (Dual-purpose Integrated Circuit), and realizes the latch function of input signals.)

1, kinds of pulse latch unit structures, characterized by, include PMOS pipe, NMOS pipe, second PMOS pipe, second NMOS pipe and accuse of the unit;

the control unit comprises a input end, a second input end and an inverting output end, wherein the second input end is used for inputting an external inverting clock signal, and the inverting input end is used for inverting and outputting a signal input by the signal input end;

the source electrode of the NMOS transistor is respectively connected with the source electrode of the second PMOS transistor, the input end of the control unit, the gate electrode of the NMOS transistor and the gate electrode of the second PMOS transistor, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor;

the source electrode of the PMOS tube is connected with an external power supply, and the grid electrode of the PMOS tube is respectively connected with the grid electrode of the second NMOS tube and the inverted output end of the control unit;

the drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube;

and the source electrode of the second NMOS tube is grounded.

Technical Field

The invention relates to the technical field of single event upset resistance reinforcement of integrated circuits, in particular to pulse latch unit structures.

Background

With the rapid development of semiconductor technology, digital integrated circuits are more and more susceptible to spatial radiation and are subject to the phenomenon of single event upset. The latch is a sequential circuit unit with a storage structure, works in a space radiation environment for a long time, and the latch unit is used as a basic structure for forming the latch, so that the necessary reinforcement design for resisting single event upset on the latch unit is of great significance for improving the reliability of the integrated circuit.

At present, aiming at the structural design of a latch unit, the main problems are as follows: the latch unit has the problems of poor portability, large area overhead and large power consumption.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide novel pulse latch units for the drawbacks involved in the background art.

The invention adopts the following technical scheme for solving the technical problems:

kinds of pulse latch unit structure, including PMOS transistor, NMOS transistor, second PMOS transistor, second NMOS transistor and control unit;

the control unit comprises a input end, a second input end and an inverting output end, wherein the second input end is used for inputting an external inverting clock signal, and the inverting input end is used for inverting and outputting a signal input by the signal input end;

the source electrode of the NMOS transistor is respectively connected with the source electrode of the second PMOS transistor, the input end of the control unit, the gate electrode of the NMOS transistor and the gate electrode of the second PMOS transistor, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor;

the source electrode of the PMOS tube is connected with an external power supply, and the grid electrode of the PMOS tube is respectively connected with the grid electrode of the second NMOS tube and the inverted output end of the control unit;

the drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube;

and the source electrode of the second NMOS tube is grounded.

Compared with the prior art, the invention adopting the technical scheme has the following technical effects:

the invention has the characteristics of strong portability and small area overhead, and simultaneously adopts the clock control technology to effectively reduce the power consumption overhead.

Drawings

FIG. 1 is a schematic structural diagram of the present invention.

Detailed Description

The invention is described in further detail with reference to the figures and the detailed description.

The present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, components are exaggerated for clarity.

As shown in fig. 1, the present invention discloses kinds of pulse latch unit structures, which include PMOS transistor, NMOS transistor, second PMOS transistor, second NMOS transistor and control unit;

the control unit comprises a input end, a second input end and an inverting output end, wherein the second input end is used for inputting an external inverting clock signal, and the inverting input end is used for inverting and outputting a signal input by the signal input end;

the source electrode of the NMOS transistor is respectively connected with the source electrode of the second PMOS transistor, the input end of the control unit, the gate electrode of the NMOS transistor and the gate electrode of the second PMOS transistor, and the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor;

the source electrode of the PMOS tube is connected with an external power supply, and the grid electrode of the PMOS tube is respectively connected with the grid electrode of the second NMOS tube and the inverted output end of the control unit;

the drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube;

and the source electrode of the second NMOS tube is grounded.

The following explains the working principle of the pulse latch unit proposed by the present invention, and the specific working principle is as follows:

the signal of the signal input end I is directly transmitted to the signal output end OUT, at the moment, the signal of the signal output end OUT respectively generates two kinds of feedback, wherein the th type is directly fed back to the grids of the N-channel metal oxide semiconductor (NMOS) transistor and the second PMOS transistor, the second type is fed back to the grids of the PMOS transistor and the second NMOS transistor after passing through the control unit DUC, steps are carried OUT, and the signal output end OUT keeps the original value unchanged after being transmitted by the MOS transistor, so that the function of temporarily storing the signal is realized.

It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein as .

The above-mentioned embodiments, objects, technical solutions and advantages of the present invention have been described in , it should be understood that the above-mentioned embodiments are only illustrative and not restrictive, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.