阅读说明：本技术 一种评估单片机中非易失性存储器数据残留的装置 (Device for evaluating data residue of nonvolatile memory in single chip microcomputer ) 是由 曾慧中 肖化宇 葛宛兵 杨潇 张万里 于 2019-09-10 设计创作，主要内容包括：本发明属于信息安全技术领域,涉及非易失性存储器的安全存储,具体涉及一种评估单片机中非易失性存储器数据残留的装置。本发明先通过SEM断面扫描的方获取了待测非易失性存储器的物理结构和使用材料,根据扫描得到的物理结构参数和使用材料对应的半导体特性参数,仿真得到浮栅电荷Q与阈值电压V<Sub>th</Sub>的关系；然后通过芯片复位中断,并用掉电法获取阈值电压,获得在单片机中非易失性存储单元擦写过程中,阈值电压随时间的变化关系；最后利用之前获取的擦写过程中阈值电压随时间的变化关系,使用电荷注入和掉电的方法,结合浮栅电荷Q与阈值电压V<Sub>th</Sub>的关系,获得一条浮栅上注入电荷与残留电荷之和Q<Sub>0</Sub>+Q<Sub>r</Sub>与擦除次数N的关系曲线。(The invention belongs to the technical field of information security, relates to the secure storage of a nonvolatile memory, and particularly relates to a device for evaluating data residue of the nonvolatile memory in a single chip microcomputer. The method comprises the steps of firstly obtaining a physical structure and a used material of the nonvolatile memory to be detected through SEM section scanning, and simulating to obtain floating gate charge Q and threshold voltage V according to the physical structure parameters obtained through scanning and semiconductor characteristic parameters corresponding to the used material th The relationship of (1); then, resetting and interrupting through a chip, and acquiring a threshold voltage by using a power failure method to acquire a change relation of the threshold voltage along with time in the erasing process of a nonvolatile storage unit in the singlechip; finally, by utilizing the change relation of the threshold voltage along with time in the erasing process obtained before, the method of charge injection and power failure is used, and the floating gate charge Q and the threshold voltage V are combined th Obtaining the sum Q of the injected charges and the residual charges on one floating gate 0 +Q r Curve with erase times N.)

1. A device for evaluating data residue of a nonvolatile memory in a single chip microcomputer is characterized in that: comprises a PC controller, a digital acquisition card and a singlechip control circuit;

the PC controller is connected with the digital acquisition card and is used for controlling the output voltage of an output channel of the digital acquisition card and enabling the digital acquisition card to be in a mode of waiting for a trigger signal;

the analog output channel 0 of the digital acquisition card is connected with the reset pin of the singlechip to be tested and outputs a voltage V_PPThe digital trigger end 1 of the digital acquisition card is connected with an I/O port 1 in the singlechip; when the data acquisition card receives a TTL trigger signal given by the I/O port 1 of the singlechip to be tested, the V is changed_PPThe single chip microcomputer is reset and interrupted when the voltage is low; the analog output channel 1 of the digital acquisition card is connected with the power supply pin of the singlechip, and the output voltage is V in the process of executing a reading command by the singlechip_DDThe output voltage in the time except the reading command is the working voltage of the single chip microcomputer, and the digital trigger end 2 of the digital acquisition card is connected with an I/O port 2 in the single chip microcomputer; when the data acquisition card receives a TTL trigger signal given by the I/O port 2 of the singlechip to be tested, the output voltage V of the channel 1 in the reading command process is reduced_DD。

The singlechip control circuit controls a program written by the singlechip to be tested: erasing and reading the nonvolatile storage unit of the singlechip to be tested, and sending a TTL trigger signal before the reading and erasing operation so that the data acquisition card can be synchronous with the erasing operation or the reading operation of the singlechip to be tested.

2. The apparatus for evaluating data residual of the nonvolatile memory in the single chip microcomputer according to claim 1, wherein: the nonvolatile memory unit is EEPROM or/and FLASH.

3. The device for evaluating data residual of the nonvolatile memory in the single chip microcomputer according to claim 1, wherein the working process is as follows:

first, obtaining a threshold voltage V_thRelationship to floating gate charge Q:

the method comprises the steps of scanning the section of a nonvolatile memory area in a single chip microcomputer through SEM (scanning electron microscope), determining the physical structure and the used material of the nonvolatile memory in the single chip microcomputer to be tested, establishing a model according to the obtained actual physical structure of the nonvolatile memory and the semiconductor physical parameters corresponding to the used material, and obtaining a threshold voltage V through software simulation_thThe relationship with the floating gate charge Q;

secondly, obtaining the change of the floating gate charge along with time in the erasing process:

executing an erasing command on a certain nonvolatile storage unit in the singlechip to be tested, and resetting at the moment t after the erasing command is started to be executed, wherein t is all time in the whole erasing process; at the moment, the power-down step is carried out, namely the logic value of the unit is read for multiple times, and the output voltage V of the channel 1 in the reading process is gradually reduced in the process_DDRecording the output voltage value until the reading of the memory cell changes from 0 to 1, thereby obtaining the change relation of the threshold voltage in the erasing process along with the time, and combining the threshold voltage V obtained in the first step_thConverting the relation between the floating gate charge Q and the floating gate charge Q to obtain the change relation of the floating gate charge Q along with time;

third, the evaluation of data retention, i.e. charge retention, is performed:

firstly, writing a selected nonvolatile storage unit in a singlechip to be tested for 1 time, and erasing for N times, wherein at the moment, different numbers of data residues exist for different erasing times N; next, charge injection is required, i.e. writing operation is performed on the nonvolatile memory cell and the interruption is reset during the writing process, and the interruption time t is strictly controlled₀The amount of charge injected into the floating gate is Q₀Raising the threshold voltage; said t is₀Selecting a threshold voltage V on a write process curve_thIncreasing the corresponding value of the middle position area of the part along with the increase of the time t, so that the threshold voltage is still in the test range after being raised;

obtaining the threshold voltage V when different N values are obtained through the power-down step_thI.e. threshold voltage V_thAnd the relation with the erasing times N, and the sum of the injected charges and the residual charges on the floating gate is obtained through conversionQ₀+Q_rWith respect to the number of erasures N.

Technical Field

The invention belongs to the technical field of information security, relates to the secure storage of a nonvolatile memory, and particularly relates to a device for evaluating data residue of the nonvolatile memory in a single chip microcomputer.

Background

With the rapid development of information storage technology, solid state storage technology is widely used. Solid-state memories can be divided into volatile and non-volatile memories. Compared with a volatile memory which is powered off or loses data, the nonvolatile memory can still keep the data therein when the power supply is temporarily interrupted or is in a power-off state for a longer time. At present, the solid-state storage technology taking the nonvolatile memory as the core is widely applied to the aspects of computers, automobiles, mobile devices, communication, medical treatment and the like, and brings a lot of benefits to our lives and study.

However, none of the memories is absolutely secure. A non-volatile memory is theoretically a memory in which data in the memory is unrecoverable after erasure, but this is not the case, and in fact, the device still has a problem of data retention. Non-volatile memories store information in the form of electrical charges, and during writing, electrons can enter the floating gate from the substrate of the device through an oxide layer, and during erasing, electrons can return to the substrate from the floating gate. However, a single erase operation does not cause the charge that entered the floating gate during the write operation to flow completely out of the floating gate, which causes a portion of the electrons to remain in the floating gate and the amount of electrons remaining is related to the number of erase operations. Therefore, even when the cell in the nonvolatile memory is read by a read operation, the read logic values are all '1', and the read logic values do not represent that no electrons exist in the floating gate completely, and because the device parameters of the nonvolatile memory in the writing and erasing process are fixed and unchanged, an attacker simulates the working process of the nonvolatile memory on the basis of knowing the device parameters, and can recover the data stored in the nonvolatile memory according to the device parameters representing the data residues in the nonvolatile memory.

As early as 1996, PeterGutmann discovered that there was a problem of data retention in semiconductor memory through research, and further research was conducted in 2001 on the phenomenon of data retention in memory cells of a nonvolatile memory EEPROM, and discovered that programming time, cell conditions, and the like affect the threshold voltage of the memory device. Data retention in a non-volatile memory is related to many factors, such as the source voltage of its erase operation, the erase time, etc. These parameters are fixed and constant during use due to the manufacturing process and operating voltage determined by the device. This allows an attacker to simulate the working process of the non-volatile memory by these fixed parameters and to recover the data in the non-volatile memory by comparing with the actually measured threshold voltage.

In 2005, the change of the threshold voltage of the floating gate memory in the read-write process was quantitatively obtained through experimental research tests, and a curve that the threshold voltage gradually decreased with the increase of the erase times N after the cell was written was obtained. However, in different single-chip microcomputers, due to different designs and different structural parameters, the amount of floating gate charges in the nonvolatile memory is different, and the result of the Sergei Skoorocogatov can only prove that data has certain residual characteristics from the threshold voltage, and can not reflect the real situation of data residual in different device structures, such as the amount of floating gate charges, which brings great uncertainty to subsequent research and application.

Disclosure of Invention

Aiming at the problems or the defects, the invention provides a device for evaluating the data residue of the nonvolatile memory in the singlechip, which aims to solve the technical problems that the existing method for evaluating the data residue of the nonvolatile memory in the singlechip only can prove that the data has certain residue characteristics and cannot reflect the true data residue conditions (such as different floating gate charges) in different device structures.

A device for evaluating data residue of a nonvolatile memory in a singlechip is shown in figure 1 and comprises a PC controller, a digital acquisition card and a singlechip control circuit.

The PC controller is connected with the digital acquisition card and is used for controlling the output voltage of an output channel of the digital acquisition card and enabling the digital acquisition card to be in a mode of waiting for a trigger signal.

The analog output channel 0 of the digital acquisition card is connected with the reset pin of the singlechip to be tested and outputs a voltage V_PPThe digital trigger end 1 of the digital acquisition card is connected with an I/O port 1 in the singlechip; when the data acquisition card receives a TTL trigger signal given by the I/O port 1 of the singlechip to be tested, the V is changed_PPAnd the single chip microcomputer is reset and interrupted when the voltage is low. The analog output channel 1 of the digital acquisition card is connected with the power supply pin of the singlechip, and the output voltage is V in the process of executing a reading command by the singlechip_DDThe output voltage in the time except the reading command is the working voltage of the single chip microcomputer, and the digital trigger end 2 of the digital acquisition card is connected with an I/O port 2 in the single chip microcomputer; when the data acquisition card receives a TTL trigger signal given by the I/O port 2 of the singlechip to be tested, the output voltage V of the channel 1 in the reading command process is reduced_DD。

The singlechip control circuit controls a program written by the singlechip to be tested: erasing and reading the nonvolatile storage unit of the singlechip to be tested, and sending a TTL trigger signal before the reading and erasing operation so that the data acquisition card can be synchronous with the erasing operation or the reading operation of the singlechip to be tested.

The work flow of the device for evaluating the data residue of the nonvolatile memory in the single chip microcomputer is shown in fig. 2:

first, obtaining a threshold voltage V_thRelationship to floating gate charge Q:

the method comprises the steps of determining the physical structure and the used material of a nonvolatile memory in a singlechip to be tested by scanning SEM (scanning electron microscope) section of the nonvolatile memory area in the singlechip, establishing a model according to the obtained actual physical structure of the nonvolatile memory and the semiconductor physical parameters (such as electron mobility) corresponding to the used material, and obtaining a threshold voltage V through software simulation_thThe relationship with the floating gate charge Q.

Secondly, obtaining the change of the floating gate charge along with time in the erasing process:

executing an erasing command on a certain nonvolatile storage unit in the singlechip to be tested, and repeating the erasing command at the t (t is all time in the whole erasing process) moment after the erasing command is started to be executedA bit; at the moment, the power-down step is carried out, namely the logic value of the unit is read for multiple times, and the output voltage V of the channel 1 in the reading process is gradually reduced in the process_DDUntil the reading of the memory cell changes from "0" to "1", the value of the output voltage at that time is recorded. Because of the logic reference voltage V of the single chip microcomputer_refAnd a supply voltage V_DDThere is a linear relationship, i.e. V_ref＝0.5*V_DDTherefore, the memory cell reading changes from "0" to "1" V_DDCorresponding logic reference voltage V_refI.e. the threshold voltage (turn-on voltage) V of the channel_th(ii) a Therefore, the change relation of the threshold voltage with time in the erasing process can be obtained, and the threshold voltage V obtained in the first step is combined_thThe relationship between the floating gate charge Q and the floating gate charge Q is converted to obtain the variation relationship of the floating gate charge Q along with time.

Thirdly, evaluating the data residual (charge residual), and the specific flow is shown in fig. 3:

firstly, writing a selected nonvolatile memory unit in a singlechip to be tested for 1 time and erasing for N times, wherein different data residues (charges are not completely removed and charges are remained) exist for different erasing times N; next, charge injection is required, i.e. writing operation is performed on the nonvolatile memory cell and the interruption is reset during the writing process, and the interruption time t is strictly controlled₀The amount of charge injected into the floating gate is Q₀Raising the threshold voltage; said t is₀Selecting a threshold voltage V on a write process curve_thThe corresponding value of the middle position area of the part is increased along with the increase of the time t, so that the threshold voltage is still in the testing range after being raised.

Obtaining the threshold voltage V when different N values are obtained through the power-down step_thI.e. threshold voltage V_thAnd the relation with the erasing times N, and the sum Q of the injected charges and the residual charges on the floating gate is obtained through conversion₀+Q_rWith respect to the number of erasures N.

The invention firstly obtains the physical structure and the used material of the nonvolatile memory in the singlechip to be tested by scanning the SEM section, and obtains the physical structure parameters and the used material according to the scanningSimulating the semiconductor physical parameters corresponding to the material to obtain floating gate charge Q and threshold voltage V_thThe relationship of (1); then, resetting and interrupting the chip, and testing the threshold voltage at the moment by using a power failure method to obtain the change relation of the threshold voltage along with time in the erasing and writing process of the singlechip; finally, the change relation of the threshold voltage along with time in the erasing process is obtained, and charge injection (the injected charge is Q)₀) And a power-down method combining floating gate charge Q with threshold voltage V_thObtaining the sum Q of the injected charges and the residual charges on one floating gate₀+Q_rAnd the number of times of erasing V_thThe relationship of (1). Finally, the invention obtains the threshold voltage V of the device by a device simulation method_thIn relation to the floating gate charge Q, the result is directly reflected as the sum Q of the injected charge and the residual charge₀+Q_rThe relation with the erasing times N can reflect the state of data residual (charge residual) in the actual nonvolatile memory device more intuitively and accurately.

In summary, the present invention obtains the charge Q and the threshold voltage V through device simulation_thThe evaluation result is combined with the actual device structure to obtain a more accurate result; the possibility for evaluating non-volatile memory data retention has a more accurate effect.

Drawings

FIG. 1 is a schematic view of an apparatus of the present invention;

FIG. 2 is a schematic view of an embodiment of the evaluation method of the present invention;

FIG. 3 is a flow chart illustrating the steps of the evaluation method of the present invention;

FIG. 4 shows an example of a threshold voltage V_thThe relationship to the floating gate charge Q;

FIG. 5 is a graph of floating gate charge Q versus time t during an erase process according to an embodiment;

FIG. 6 is a graph of floating gate charge Q versus time t during an embodiment write process;

FIG. 7 shows the sum Q of the injected charge and the residual charge on the floating gate of the FLASH cell according to the embodiment₀+Q_rAnd the number of wipes N.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The basic structure of data storage in the nonvolatile memory is a floating gate unit, the structure of the nonvolatile memory unit stores charges and is a floating gate, the floating gate is positioned between a control gate and a substrate and is surrounded by an insulating layer, and a wide forbidden band of the insulating layer forms a potential barrier to prevent electrons from flowing into or flowing out of the floating gate.

The logic "0" and logic "1" states of a nonvolatile memory cell can be distinguished based on the amount of negative charge on the floating gate, which is determined by the programming operation. The program operation is divided into a write operation and an erase operation. The writing operation utilizes channel hot electron injection effect to make electrons flow into floating gate, increase negative charge on floating gate and raise threshold voltage V of transistor_thRaised to be higher than the applied grid source voltage V in read operation_GSWhen the transistor is off, the data is stored as logic '0'; the erasing operation utilizes F-N tunneling effect, the source end is applied with fixed high voltage, the control grid is grounded, the drain end is suspended, electrons flow out of the floating grid, negative charges on the floating grid are reduced, and the threshold voltage V of the transistor is reduced_thLower than the applied gate-source voltage V during read operation_GSThe transistor is turned on and the data is stored as a logic "1".

It can be known from knowledge about the floating gate device that the electric field intensity between the floating gate of the floating gate device and the substrate is related to the amount of electrons remaining in the floating gate, and when the remaining amount of the floating gate charge is less and less, it is difficult to form an electric field intensity sufficient for tunneling a large amount of electrons between the floating gate and the substrate, so that it is more difficult to remove the charge in the floating gate under the condition of less floating gate charge. Therefore, for a written cell, many erasures may be required to make the floating gate charge unchanged.

As shown in fig. 2:

firstly, carrying out memory structure simulation:

1-1, scanning the SEM section of a nonvolatile memory in a single chip microcomputer to obtain the physical structure and the used material of the nonvolatile memory, and establishing a simulation model;

1-2, calculating the channel current I of the floating gate when different electric charge quantities are contained in the floating gate through a finite element algorithm_DSAnd control gate voltage V_GThe relationship between them, and then find its threshold voltage (turn-on voltage) V_thMaking a floating gate threshold voltage V_thAnd floating gate charge Q, as shown in fig. 4.

Test cell threshold voltage V_thBy a step of power-down, i.e. slowly lowering the supply voltage V_DDAnd then the logic value of the storage unit is read. Because of the logic reference voltage V of the single chip microcomputer_refAnd a supply voltage V_DDThere is a linear relationship, i.e. V_ref＝0.5*V_DDTherefore, the memory cell reading changes from "0" to "1" V_DDCorresponding logic reference voltage V_refI.e. the threshold voltage (turn-on voltage) V of the channel_th. However, due to the supply voltage V_DDWith a minimum limit, the threshold voltage V of the non-volatile memory cell, even for an erase operation_thStill not directly accessible by testing. Therefore, it is also necessary to perform an operation of injecting charges, which requires a change in threshold voltage with time during the erasing process.

And secondly, acquiring the change of the floating gate charge along with time in the erasing process:

2-1, selecting a nonvolatile storage unit, and performing reset interruption on the moment t in the erasing process, wherein the value of t is all the moments in the erasing process;

2-2, measuring the threshold voltage V after each interruption by using the power-down method in the first step_th。

2-3 threshold voltage V obtained by simulation_thAnd obtaining the change of the floating gate charge Q along with the time t in the writing and erasing process according to the relation of the floating gate charge Q.