阅读说明：本技术 金属氧化物半导体元件及其制造方法 (Metal oxide semiconductor element and manufacturing method thereof ) 是由 黄宗义 于 2018-06-29 设计创作，主要内容包括：本发明提出一种型金属氧化物半导体元件及其制造方法。金属氧化物半导体元件包含：半导体层、绝缘结构、阱区、栅极、源极、漏极、第一轻掺杂区以及第二轻掺杂区。其中,第一轻掺杂区位于栅极的间隔层及部分介电层的正下方。且于通道方向上,第一轻掺杂区邻接于漏极与反转电流通道之间,并分隔漏极与反转电流通道。第二轻掺杂区包括第一部分与第二部分。第一部分位于栅极靠近源极侧的间隔层的正下方,且第一部分邻接于源极与反转电流通道之间。第二部分位于栅极靠近漏极侧的间隔层的正下方,且邻接漏极与第一轻掺杂区。(The invention provides a metal oxide semiconductor element and a manufacturing method thereof. The metal oxide semiconductor element comprises: the semiconductor device comprises a semiconductor layer, an insulating structure, a well region, a grid electrode, a source electrode, a drain electrode, a first lightly doped region and a second lightly doped region. The first lightly doped region is located right below the spacer layer of the gate and a part of the dielectric layer. And in the channel direction, the first lightly doped region is adjacent to the drain electrode and between the inversion current channel, and separates the drain electrode and the inversion current channel. The second lightly doped region includes a first portion and a second portion. The first portion is located directly under the spacer layer on the gate side near the source, and the first portion is adjacent between the source and the inversion current channel. The second part is positioned right below the spacer layer on the side of the grid electrode close to the drain electrode and is adjacent to the drain electrode and the first lightly doped region.)

1. A metal oxide semiconductor device, comprising:

the semiconductor layer is formed on a substrate and is provided with an upper surface and a lower surface which are opposite in a vertical direction;

an insulating structure formed on the upper surface and connected to the upper surface for defining an operation region;

a well region of a first conductivity type formed in the operating region of the semiconductor layer and located below and connected to the upper surface in the vertical direction;

a gate formed in the operating region on the upper surface of the semiconductor layer, wherein in the vertical direction, a portion of the well region is located directly below the gate and connected to the gate to provide an inversion current path for the MOS device in a turn-on operation, wherein the gate comprises:

a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the well region in the vertical direction;

a conductive layer as an electrical contact of the gate electrode, formed on all the dielectric layers and connected to the dielectric layers; and

a spacer layer formed outside two sidewalls of the conductive layer and connected to the conductive layer to serve as an electrical insulation layer of the gate;

a source and a drain of a second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the source and the drain being respectively located in the well region under the outer portions of the two sides of the gate and adjacent to the gate, and the reverse current channel being interposed between the source and the drain in a channel direction and separating the source and the drain on the two sides of the gate;

a first lightly doped region of the second conductivity type formed under the upper surface and connected to the operating region of the upper surface in the vertical direction, the first lightly doped region being located under the spacer layer and a portion of the dielectric layer of the gate adjacent to the drain and connected to the spacer layer and a portion of the dielectric layer, and the first lightly doped region being adjacent to and separating the drain from the inversion current channel in the channel direction; and

a second lightly doped region of the second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the second lightly doped region including:

a first portion directly under and connected to the spacer on the gate side adjacent to the source side, the first portion abutting the source in the channel direction, and the first portion abutting between and separating the source and the inversion current channel in the channel direction; and

a second portion located directly under the spacer layer on the side of the gate close to the drain and connected to the spacer layer, wherein the second portion is adjacent to the drain in the channel direction, and the second portion is adjacent to the drain and the first lightly doped region in the channel direction;

wherein the depth of the first lightly doped region is greater than the depth of the second lightly doped region.

2. The MOS device of claim 1, wherein the insulation structure comprises a local oxidation structure, a shallow trench insulation structure or a CVD oxide region.

3. The MOS device of claim 1, wherein said first lightly doped region is not located directly under said spacer on said gate side close to said source side.

4. The MOS device of claim 1, wherein the first lightly doped region is formed by a first self-aligned process, the first self-aligned process comprising: the conductive layer and the dielectric layer are used as a shield, and second conductive type impurities in the form of accelerated ions and a first included angle with the vertical direction are implanted into the operation region.

5. The MOS device of claim 1, wherein the second lightly doped region is formed by a second self-aligned process, the second self-aligned process comprising: the spacing layer and the conductive layer are used as a shield, and second conductive type impurities in the form of accelerated ions and a second included angle with the vertical direction penetrate through the spacing layer and are implanted into the operation region.

6. A method for manufacturing a metal oxide semiconductor device comprises:

forming a semiconductor layer on a substrate, wherein the semiconductor layer has an upper surface and a lower surface opposite to each other in a vertical direction;

forming an insulating structure on the upper surface and connected to the upper surface to define an operation region;

forming a well region in the operating region of the semiconductor layer in the vertical direction, the well region being located below the upper surface and connected to the upper surface, the well region having a first conductivity type;

forming a gate in the operating region on the upper surface of the semiconductor layer, wherein in the vertical direction, a portion of the well region is located directly below the gate and connected to the gate to provide an inversion current path for the MOS device in a turn-on operation, wherein the gate comprises:

a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the well region in the vertical direction;

a conductive layer as an electrical contact of the gate electrode, formed on all the dielectric layers and connected to the dielectric layers; and

a spacer layer formed outside two sidewalls of the conductive layer and connected to the conductive layer to serve as an electrical insulation layer of the gate;

forming a first lightly doped region under the upper surface and connected to the operating region of the upper surface, the first lightly doped region having a second conductivity type and being located under the spacer layer and a portion of the dielectric layer, the gate being adjacent to a drain and connected to the spacer layer and a portion of the dielectric layer, and the first lightly doped region being adjacent to and between the drain and the inversion current channel in the channel direction and separating the drain and the inversion current channel;

forming a source and a drain under the upper surface and connected to the operating region of the upper surface, the source and the drain having the second conductivity type and being respectively located in the well region under the outside of both sides of the gate and adjacent to the gate, and the reverse current channel being between the source and the drain in a channel direction and separating the source and the drain on both sides of the gate; and

forming a second lightly doped region under the upper surface and connected to the operation region of the upper surface, the second lightly doped region having the second conductivity type, the second lightly doped region comprising:

a first portion directly under and connected to the spacer on the gate side adjacent to the source side, the first portion abutting the source in the channel direction, and the first portion abutting between and separating the source and the inversion current channel in the channel direction; and

a second portion located directly under the spacer layer on the side of the gate close to the drain and connected to the spacer layer, wherein the second portion is adjacent to the drain in the channel direction, and the second portion is adjacent to the drain and the first lightly doped region in the channel direction;

wherein the depth of the first lightly doped region is greater than the depth of the second lightly doped region.

7. The method according to claim 6, wherein the insulating structure comprises a local oxidation structure, a shallow trench insulating structure or a CVD oxide region.

8. The method of claim 6, wherein said first lightly doped region is not located directly under said spacer on said gate side near said source.

9. The method of claim 6, wherein the step of forming the first lightly doped region comprises: a first self-alignment process, using the conductive layer and the dielectric layer as a shield, implanting second conductive type impurities into the operation region in the form of accelerated ions with a first angle with the vertical direction.

10. The method of claim 6, wherein the step of forming the second lightly doped region comprises: a second self-alignment process, using the spacing layer and the conductive layer as a shield, making a second included angle between the second conductive type impurity in the form of accelerated ions and the vertical direction, and injecting the second conductive type impurity into the operation region through the spacing layer.

11. The method according to claim 6, wherein the steps of forming the semiconductor layer, the insulating structure, the well, the gate, the source, the drain and the first lightly doped region simultaneously form a symmetric element in the substrate, and the step of forming the second lightly doped region is not used to form the symmetric element; and in the same step of forming the first lightly doped region, forming a source side first lightly doped region in the symmetric element, wherein the source side first lightly doped region is located in the symmetric element, a symmetric element gate is close to a symmetric element spacer of one of the symmetric element sources and right below a part of a symmetric element dielectric layer and is connected with the symmetric element spacer and a part of the symmetric element dielectric layer, and in the channel direction, the source side first lightly doped region is adjacent to the symmetric element source and a symmetric element inversion current channel and separates the symmetric element source and the symmetric element inversion current channel.

Technical Field

The present invention relates to a metal oxide semiconductor device and a method for fabricating the same, and more particularly, to a metal oxide semiconductor device capable of improving threshold voltage roll-off and hot carrier effect and a method for fabricating the same.

Background

Fig. 1A is a schematic cross-sectional view of a conventional Metal Oxide Semiconductor (MOS) device 10 in which lightly doped regions 16a and 16b are formed. As shown in fig. 1A, the MOS device 10 is formed in the substrate 11, and first: semiconductor layer 12, well region 13, insulating structure 14, gate 15, and lightly doped regions 16a and 16 b. Wherein the insulating structure 14 defines an operation region 14a as a main active region of the MOS device 10 during operation. The step of forming the gate electrode 15 includes: the dielectric layer 151 and the conductive layer 152 are formed first, and then the spacer layer 153 is formed after the lightly doped regions 16a and 16B are formed (see fig. 1B). The step of forming lightly doped regions 16a and 16b includes implanting N-type impurities in the form of accelerated ions into the operation region 14 at an angle α to the vertical (as indicated by the solid arrows in fig. 1A) using the dielectric layer 151 and the conductive layer 152 as a mask. As shown in fig. 1A, the lightly doped region 16a is located under a portion of the dielectric layer 151 of the gate 15 near the source 17 (see fig. 1B), and after the source 17 is formed, the lightly doped region 16a is adjacent to between the source 17 and the well 13. The lightly doped region 16B is located under a portion of the dielectric layer 151 on the side of the gate 15 close to the drain 18 (see fig. 1B), and after the drain 18 is formed, the lightly doped region 16B is adjacent between the drain 18 and the well region 13.

Fig. 1B is a schematic cross-sectional view of a step of forming the source 17 and the drain 18 in the MOS device 10. As shown in fig. 1B, the step of forming the source 17 and the drain 18 includes implanting N-type impurities into the operation region 14 in the form of accelerated ions by using the spacer 153 as a mask.

When the MOS device 10 operates, the electronic characteristics of the MOS device 10 are unstable due to hot carrier effect (hot carrier effect) and threshold voltage roll-off (threshold voltage roll-off), which reduces the application range of the MOS device 10.

Accordingly, the present invention provides a MOS device capable of improving the threshold voltage roll-off without affecting the on-resistance and a method for manufacturing the same.

Disclosure of Invention

From one aspect, the present invention provides a MOS device comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other in a vertical direction; an insulating structure formed on and connected to the upper surface to define an operation region; a well region of a first conductivity type formed in the operating region of the semiconductor layer and located below and connected to the upper surface in the vertical direction; a gate formed in the operating region on the upper surface of the semiconductor layer, wherein in the vertical direction, a portion of the well region is located directly under the gate and connected to the gate to provide an inversion current path for the MOS device in a turn-on operation, wherein the gate comprises: a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the well region in the vertical direction; a conductive layer as an electrical contact of the gate electrode, formed on all the dielectric layers and connected to the dielectric layers; and a spacing layer formed outside two sidewalls of the conductive layer and connected to the conductive layer to serve as an electrical insulation layer of the gate; a source and a drain of a second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the source and the drain being respectively located in the well region under the outer portions of the two sides of the gate and adjacent to the gate, and the reverse current channel being interposed between the source and the drain in a channel direction and separating the source and the drain on the two sides of the gate; a first lightly doped region of the second conductivity type formed under the upper surface and connected to the operating region of the upper surface in the vertical direction, the first lightly doped region being located under the spacer layer and a portion of the dielectric layer of the gate adjacent to the drain and connected to the spacer layer and a portion of the dielectric layer, and being adjacent to the drain and the inversion current channel in the channel direction and separating the drain and the inversion current channel; and a second lightly doped region of the second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the second lightly doped region including: a first portion directly under and connected to the spacer on the gate side near the source side, the first portion abutting the source in the channel direction, and the first portion abutting between and separating the source and the inversion current channel in the channel direction; and a second portion located directly under the spacer layer on the side of the gate close to the drain and connected to the spacer layer, wherein the second portion is adjacent to the drain in the channel direction, and the second portion is adjacent to the drain and the first lightly doped region in the channel direction; wherein the depth of the first lightly doped region is greater than the depth of the second lightly doped region.

From another perspective, the present invention provides a method for manufacturing a MOS device, comprising: forming a semiconductor layer on a substrate, wherein the semiconductor layer has an upper surface and a lower surface opposite to each other in a vertical direction; forming an insulating structure on the upper surface and connecting to the upper surface to define an operation region; forming a well region in the operating region of the semiconductor layer in the vertical direction, the well region being located below and connected to the upper surface, the well region having a first conductivity type; forming a gate in the operating region on the upper surface of the semiconductor layer, wherein in the vertical direction, a portion of the well region is located right under the gate and connected to the gate to provide an inversion current path for the MOS device in a turn-on operation, wherein the gate comprises: a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the well region in the vertical direction; a conductive layer, which is used as an electrical contact of the gate electrode, formed on all the dielectric layers and connected to the dielectric layers; and a spacer layer formed outside two sidewalls of the conductive layer and connected to the conductive layer to serve as an electrical insulation layer of the gate; forming a first lightly doped region under the upper surface and connected to the operating region of the upper surface, the first lightly doped region having a second conductivity type and located under the spacer layer and a portion of the dielectric layer, the gate being close to a drain and connected to the spacer layer and a portion of the dielectric layer, and the first lightly doped region being adjacent to and between the drain and the inversion current channel in the channel direction and separating the drain and the inversion current channel; forming a source and a drain under the upper surface and connected to the operating region of the upper surface, the source and the drain having the second conductivity type and being respectively located in the well region under the outer portions of the two sides of the gate and adjacent to the gate, and the reverse current channel being interposed between the source and the drain in a channel direction and separating the source and the drain at the two sides of the gate; and forming a second lightly doped region under the upper surface and connected to the operating region of the upper surface, the second lightly doped region having the second conductivity type, the second lightly doped region comprising: a first portion directly under and connected to the spacer on the gate side adjacent to the source side, the first portion abutting the source in the channel direction, and the first portion abutting between the source and the inversion current channel in the channel direction and separating the source and the inversion current channel; and a second portion located directly under the spacer layer on the side of the gate close to the drain and connected to the spacer layer, wherein the second portion is adjacent to the drain in the channel direction, and the second portion is adjacent to the drain and the first lightly doped region in the channel direction; wherein the depth of the first lightly doped region is greater than the depth of the second lightly doped region.

In a preferred embodiment, the insulating structure includes a local oxidation of silicon (LOCOS) structure, a Shallow Trench Isolation (STI) structure, or a Chemical Vapor Deposition (CVD) oxide region.

In a preferred embodiment, the first lightly doped region is not located directly under the spacer layer on the gate side close to the source.

In a preferred embodiment, the first lightly doped region is formed by a first self-aligned process, which includes: the conductive layer and the dielectric layer are used as a shield, and second conductive type impurities in the form of accelerated ions and a first included angle between the second conductive type impurities and the vertical direction are implanted into the operation region.

In a preferred embodiment, the second lightly doped region is formed by a second self-aligned process, the second self-aligned process comprising: and using the spacing layer as a shield, and implanting second conductive type impurities into the operation region through the spacing layer in a manner of accelerating ions and forming a second included angle with the vertical direction.

In a preferred embodiment, the step of forming the semiconductor layer, the insulating structure, the well region, the gate, the source, the drain and the first lightly doped region simultaneously forms a symmetric element in the substrate, and the step of forming the second lightly doped region does not form the symmetric element; and in the same step of forming the first lightly doped region, forming a source side first lightly doped region in the symmetric element, wherein the source side first lightly doped region is located in the symmetric element, a symmetric element gate is close to a symmetric element spacing layer of one of the symmetric element sources and is directly below part of a symmetric element dielectric layer and is connected with the symmetric element spacing layer and part of the symmetric element dielectric layer, and in the channel direction, the source side first lightly doped region is adjacent to a position between the symmetric element source and a symmetric element inversion current channel and separates the symmetric element source and the symmetric element inversion current channel.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1A is a schematic cross-sectional view of a conventional Metal Oxide Semiconductor (MOS) device 10 illustrating steps for forming lightly doped regions 16a and 16 b;

fig. 1B is a schematic cross-sectional view of a step of forming a source 17 and a drain 18 in the MOS device 10;

FIG. 2 shows a first embodiment of the invention;

FIG. 3 shows a second embodiment of the present invention;

FIGS. 4A-4F illustrate a third embodiment of the present invention;

FIGS. 5A and 5B are electrical schematic diagrams respectively illustrating critical voltages and on-resistance values of N-type MOS devices according to the prior art and the present invention;

fig. 6A and 6B are electrical schematic diagrams respectively illustrating the threshold voltage and the on-resistance of a P-type MOS device according to the prior art and the present invention.

Description of the symbols in the drawings

10,20 MOS element

11,21 substrate

12,22,32 semiconductor layer

22a,32a upper surface

22b,32b lower surface

13,23,33 well region

14,24,34 insulation structure

14a,24a operating area

15,25,35 grid

151,251,351 dielectric layer

152,252,352 conductive layer

153,253,353 spacing layer

16a,16b,26b,36a,36b first lightly doped region

17,27,37 source

18,28,38 drain electrode

26 b' photoresist layer

29a first part

29b second part

30 symmetrical element

Alpha first angle

Beta second angle of inclination

Detailed Description

The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of preferred embodiments, which proceeds with reference to the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the relationship between the layers in the vertical order, and the shapes, thicknesses and widths are not drawn to scale.

Referring to FIG. 2, a first embodiment of the present invention is shown. Fig. 2 shows a schematic cross-sectional view of the MOS device 20. As shown in fig. 2, the MOS device 200 includes: semiconductor layer 22, well region 23, insulating structure 24, gate 25, first lightly doped region 26b, source 27, drain 28, and second lightly doped region (including first portion 29a and second portion 29 b). The semiconductor layer 22 is formed on the substrate 21, and the semiconductor layer 22 has an upper surface 22a and a lower surface 22b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 2, the same applies hereinafter). The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 22 is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 22. The manner of forming the semiconductor layer 22 is well known to those skilled in the art and will not be described herein.

Referring to fig. 2, an insulating structure 24 is formed on the upper surface 22a and connected to the upper surface 22a to define an operation region 24 a. The insulating structure 24 is not limited to a local oxidation of silicon (LOCOS) structure as shown in the figure, but may be a Shallow Trench Isolation (STI) structure or a Chemical Vapor Deposition (CVD) oxide region.

The well region 23 has the first conductivity type, is formed in the operation region 24a of the semiconductor layer 22, and is located under the upper surface 22a and connected to the upper surface 22a in the vertical direction. A gate 25 is formed in the operation region 24a on the upper surface 22a of the semiconductor layer 22, and a portion of the well region 23 is located right below the gate 25 and connected to the gate 25 in the vertical direction to provide a reverse current path (as indicated by the dashed line) for the MOS device 20 in the turn-on operation.

With continued reference to fig. 2, the gate includes: dielectric layer 251, conductive layer 252, and spacer layer 253. The dielectric layer 251 is formed on the upper surface 22a and connected to the upper surface 22a, and the dielectric layer 251 is connected to the well region 23 in the vertical direction. The conductive layer 252 is used as an electrical contact for the gate 25, is formed on all the dielectric layers 251 and is connected to the dielectric layers 251. Spacers 253 are formed on the outside of the sidewalls of the conductive layer 252 and connected to the conductive layer 252 to serve as an electrical insulation layer for the gate 25.

The source 27 and the drain 28 have a second conductivity type, and in the vertical direction, the source 27 and the drain 28 are formed under the upper surface 22a and connected to the operation region 24a of the upper surface 21a, and the source 27 and the drain 28 are respectively located in the well 23 under the gate 25 in the channel direction (as indicated by the dotted arrow in fig. 2, the same below), and adjacent to the gate 25, and in the channel direction, a reverse current channel is interposed between the source 27 and the drain 28 and separates the source 27 and the drain 28 at two sides of the gate 25.

The first lightly doped region 29b has the second conductivity type, and in the vertical direction, the first lightly doped region 29b is formed under the upper surface 22a and connected to the operation region 24a of the upper surface 22a, and the first lightly doped region 29b is located under the spacer 253 and a portion of the dielectric layer 251 of the gate 25 near the drain 28 and connected to the spacer 253 and a portion of the dielectric layer 251, and in the channel direction, the first lightly doped region 29b is adjacent to and separates the drain 28 from the inversion current channel.

The second lightly doped region (including the first portion 29a and the second portion 29b) has a second conductivity type in the vertical direction, is formed under the upper surface 22a and connected to the operation region 24a of the upper surface 22a, and includes the first portion 29a and the second portion 29 b. The first portion 29a is located right under the spacer 253 on the side of the gate 25 close to the source 27 and connects to the spacer 253, and the first portion 29a is adjacent to the source 27 in the channel direction, and the first portion 29a is adjacent between the source 27 and the inversion current channel in the channel direction and separates the source 27 from the inversion current channel. The second portion 29b is located right under the spacer 253 on the side of the gate 25 close to the drain 28 and connected to the spacer 253, and in the channel direction, the second portion 29b is adjacent to the drain 28 and the first lightly doped region 26 b. Wherein the depth of the first lightly doped region 26b in the vertical direction is greater than the depth of the second lightly doped region 29 b. In a preferred embodiment, as shown in fig. 2, the first lightly doped region 26b is not located directly under the spacer 253 on the side of the gate 25 close to the source 27.

It should be noted that the inversion current channel is a region where an inversion layer (inversion layer) is formed below the gate 25 to pass an on current due to a voltage applied to the gate 25 during the on operation of the MOS device 20, and is well known to those skilled in the art and will not be described herein.

Note that the upper surface 22a does not mean a completely flat plane, but means a surface of the semiconductor layer 22. In the present embodiment, for example, the portion of the upper surface 22a where the insulating structure 24 contacts the upper surface 22a has a depressed portion.

The above-mentioned "first conductivity type" and "second conductivity type" refer to that in the MOS device, impurities of different conductivity types are doped in the semiconductor composition region (for example, but not limited to, the well region, the source region, the drain region, and the like) so that the semiconductor composition region becomes the first or second conductivity type (for example, but not limited to, the first conductivity type is P-type, and the second conductivity type is N-type, or vice versa).

It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 2 as an example, compared to the MOS device 10 of the prior art, the first lightly doped region 26b of the MOS device 20 is only under the spacer 253 near the drain 28 and a portion of the dielectric layer 251, but not under the spacer 253 near the source 27, so that the breakdown protection voltage can be increased. And has a second lightly doped region (comprising a first portion 29a and a second portion 29 b). In addition, the MOS device 20 has a second lightly doped region (including the first portion 29a and the second portion 29b), and in a preferred embodiment, the second lightly doped region (including the first portion 29a and the second portion 29b) has a depth smaller than that of the first lightly doped region 26b, so as to reduce the on-resistance of the MOS device 20, and compensate for the increased on-resistance due to the absence of the spacer 153 and the first lightly doped region 16a under a portion of the dielectric layer 151 on the side close to the source 17 relative to the MOS device 10 of the prior art. Based on the above, the MOS device according to the present invention has a longer effective reverse current channel compared to the MOS device of the prior art; thus, the MOS device of the present invention can mitigate Short Channel Effect (SCE) such as drain-induced barrier (DIBL) and Hot Carrier Effect (HCE), and improve threshold voltage roll-off.

From another perspective, under the same required threshold voltage drop specification, according to the present invention, the on-resistance can be greatly reduced by selecting a MOS device with a smaller length (in the channel direction).

In a preferred embodiment, the first lightly doped region 29b is formed by a first self-aligned process, which includes: the conductive layer 252 and the dielectric layer 251 are used as a shield, and a second conductive type impurity in the form of accelerated ions having a first angle α with the vertical direction is implanted into the operation region to form a first lightly doped region 29 b. And in a preferred embodiment, the first lightly doped region 29b is not located directly under the spacer 253 on the side of the gate 25 near the source 27.

In a preferred embodiment, the second lightly doped region (including the first portion 29a and the second portion 29b) is formed by a second self-aligned process, which includes: using the spacer 253 as a mask, a second conductive type impurity in the form of accelerated ions having a second angle β with the vertical direction is implanted into the operation region 24a through the spacer 253 to form a second lightly doped region (including the first portion 29a and the second portion 29 b).

Referring to FIG. 3, a second embodiment of the present invention is shown. Fig. 3 shows that the MOS device 20 and the symmetric device 30 are formed simultaneously in the same substrate 21 by a number of common process steps. The steps of forming the semiconductor layer 22, the insulating structure 24, the well region 23, the gate 25, the source 27, the drain 28 and the first lightly doped region 26b simultaneously form the symmetric device semiconductor layer 32, the symmetric device insulating structure 34, the symmetric device well region 33, the symmetric device gate 35, the symmetric device source 37, the symmetric device drain 38, and the source-side first lightly doped region 36a and the drain-side first lightly doped region 36b of the symmetric device 30 in the substrate 21, respectively, and the steps of forming the second lightly doped region (including the first portion 29a and the second portion 29b) do not form the symmetric device 30. In the same step as the formation of the first lightly doped region 26b, a source side first lightly doped region 36a is formed in the symmetric device 30. The source side first lightly doped region 36a is located in the symmetric device gate 35, is located just below the symmetric device spacer 353 and a portion of the symmetric device dielectric 351 near the symmetric device source 37 and is connected to the symmetric device spacer 353 and a portion of the symmetric device dielectric 351, and in the channel direction, the source side first lightly doped region 36a is adjacent to and separates the symmetric device source 37 from the symmetric device inversion current channel (indicated by the dashed line).

Please refer to fig. 4A-4F, which illustrate a third embodiment of the present invention. This embodiment shows a schematic cross-sectional view of a method for manufacturing a MOS device 20 according to the present invention. As shown in fig. 4A, a substrate 21 is provided. Next, as shown in fig. 4B, a semiconductor layer 22 is formed on the substrate 21, and the semiconductor layer 22 has an upper surface 22a and a lower surface 22B facing each other in the vertical direction. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 22 is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 22. The manner of forming the semiconductor layer 22 is well known to those skilled in the art and will not be described herein. Next, for example, but not limited to, in an ion implantation process step, the first conductive type impurity is implanted into the operation region 24a in the form of accelerated ions, as indicated by the dashed arrow in fig. 4B, to form the well region 22 in the operation region 24a of the semiconductor layer 22, and the well region 23 is located under the upper surface 22a and connected to the upper surface 22a in the vertical direction. The well region 23 has a first conductivity type.

Referring to fig. 4C, an insulating structure 24 is formed on the upper surface 22a and connected to the upper surface 22 a. The insulating structure 24 is used to define an operation region 24 a. The insulating structure 24 can be, for example but not limited to, a local oxidation of silicon (LOCOS) structure as shown in the figure, a Shallow Trench Isolation (STI) structure or a Chemical Vapor Deposition (CVD) oxide region, which is well known to those skilled in the art and will not be described herein again. Wherein the upper surface 22a is indicated by the dashed broken line in the figure.

Next, referring to fig. 4D, a dielectric layer 251 and a conductive layer 252 of the gate 25 are formed in the operation region 24a on the upper surface 22a of the semiconductor layer 22. Wherein, in the vertical direction, a portion of the well 23 is located right under the dielectric layer 251 of the gate 25 and the conductive layer 252 and connected to the dielectric layer 251 of the gate 25 to provide an inversion current path (as indicated by the dashed line in fig. 4E) for the MOS device 20 in the turn-on operation. The dielectric layer 251 is formed on the upper surface 22a and connected to the upper surface 22a, and the dielectric layer 251 is connected to the well region 23 in the vertical direction. The conductive layer 252 is used as an electrical contact for the gate 25, is formed on all the dielectric layers 251 and is connected to the dielectric layers 251.

Next, with reference to fig. 4D, a first lightly doped region 26b is formed under the top surface 22a and connected to the operation region 24a of the top surface 22a, the first lightly doped region 26b has the second conductivity type, and the first lightly doped region 26b is located under the spacer 253 and a portion of the dielectric layer 251 of the gate 25 close to the drain 28 (see fig. 4F) and is connected to the spacer 253 and a portion of the dielectric layer 251, and in the channel direction, the first lightly doped region 26b is adjacent to and separates the drain 28 from the inversion current channel. The step of forming the first lightly doped region 26b is, for example, formed by a first self-aligned process including: by using the conductive layer 252 and the dielectric layer 251, and using the photoresist layer 26 b' formed by the photolithography process as a mask, a second conductive type impurity is implanted into the operation region 24a in the form of accelerated ions having a first angle α with the vertical direction. Then, for example, an ion implantation process step is used to implant the second conductive type impurity into the well region 23 in the form of accelerated ions to form the first lightly doped region 26 b.

Next, referring to fig. 4E, a source 27 and a drain 28 are formed under the top surface 22a and connected to the operation region 24a of the top surface 22 a. The source 27 and the drain 28 have the second conductivity type, and the source 27 and the drain 28 are respectively located in the well 23 under the outside of the two sides of the gate 25, and adjacent to the gate 25, and in the channel direction, the reverse current channel is between the source 27 and the drain 28, and separates the source 27 and the drain 28 on the two sides of the gate 25.

Next, referring to fig. 4F, a second lightly doped region (including the first portion 29a and the second portion 29b) is formed under the upper surface 22a and connected to the operation region 24a of the upper surface 22a, and the second lightly doped region (including the first portion 29a and the second portion 29b) has the second conductivity type. The second lightly doped region includes a first portion 29a and a second portion 29b, wherein the first portion 29a is located right under the spacer 253 on the side of the gate 25 close to the source 27 and connected to the spacer 253, and the first portion 29a is adjacent to the source 27 in the channel direction, and the first portion 29a is adjacent to between the source 27 and the inversion current channel in the channel direction and separates the source 27 and the inversion current channel. The second portion 29b is located directly below the spacer 253 on the side of the gate 25 closer to the drain 28 and connects to the spacer 253. The second portion 29b is adjacent to the drain 28 in the channel direction, and the second portion 29b is adjacent to the drain 28 and the first lightly doped region 26b in the channel direction. The depth of the first lightly doped region 26b in the vertical direction is greater than the depth of the second lightly doped region (including the first portion 29a and the second portion 29 b).

The step of forming the second lightly doped region (including the first portion 29a and the second portion 29b) is, for example, formed by a second self-aligned process, which includes: by using the spacer 253 and the conductive layer 252 as a mask, a second conductive type impurity in the form of accelerated ions having a second angle β with the vertical direction is implanted into the operation region 24a through the spacer 253 to form a second lightly doped region (including the first portion 29a and the second portion 29 b). In a preferred embodiment, the first included angle α is greater than the second included angle β.

Fig. 5A and 5B show electrical schematic diagrams of threshold voltage Vt (left ordinate) and on-resistance Ron (right ordinate) for different gate lengths (abscissa axis of coordinate axes) of a prior art and an N-type MOS device according to the present invention, respectively. As shown in fig. 5A, when the gate length of the N-type MOS device in the prior art is decreased from 0.6 to 0.4, the threshold voltage Vt is decreased from about 0.84 to about 0.18, which is a 0.66 unit drop, and the threshold voltage has a significant threshold voltage drop and a small application range. In contrast, as shown in fig. 5B, when the gate length of the N-type MOS device of the present invention is decreased from 0.6 to 0.4, the threshold voltage Vt is decreased from about 0.91 to about 0.85, which is only decreased by 0.06, so that the threshold voltage Vt is maintained not to drop down significantly, and the application range is wider. On the other hand, when it is required to select an element with a threshold voltage of more than 0.8 voltage unit, according to the prior art, only an N-type MOS element with a gate length of more than 0.6 length unit can be selected, but according to the present invention, an N-type MOS element with a gate length of 0.4 length unit (even less) can be selected, so according to the present invention, from another point of view, the on-resistance Ron can be greatly reduced, and the operation speed of the N-type MOS element can be improved. In the N-type MOS device according to the present invention, the on-resistance Ron is maintained to be approximately equal to the on-resistance Ron of the N-type MOS device of the prior art when the on-resistance Ron has the same gate length as the N-type MOS device of the prior art.

In contrast, fig. 6A and 6B show electrical schematic diagrams of threshold voltage Vt (left ordinate) and on-resistance Ron (right ordinate) for different gate lengths (abscissa axis of coordinate axes) of a prior art and a P-type MOS device according to the present invention, respectively. As shown in fig. 6A, when the gate length of the P-type MOS device of the prior art is decreased from 0.5 to 0.25, the absolute value of the threshold voltage Vt is decreased from about 0.89 to about 0.33, and is decreased by 0.56, which has a significant threshold voltage drop and a small application range. In contrast, as shown in fig. 6B, when the gate length of the P-type MOS device of the present invention is decreased from 0.5 to 0.25, the absolute value of the threshold voltage Vt is decreased from about 0.82 to about 0.63, and is decreased by only 0.19, so that the threshold voltage Vt is maintained not to drop down significantly, and the application range is wide. On the other hand, when it is necessary to select a device having an absolute value of the threshold voltage Vt of 0.7 voltage unit or more, only a P-type MOS device having a gate length of 0.35 length unit or more can be selected according to the prior art, whereas a P-type MOS device having a gate length of 0.3 length unit or less can be selected according to the present invention. Therefore, according to the present invention, from another perspective, the on-resistance Ron can be greatly reduced, and the operating speed of the P-type MOS device can be improved. And according to the P-type MOS device of the present invention, the on-resistance Ron still maintains approximately the same on-resistance when the gate length is the same as that of the P-type MOS device of the prior art.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. Further, the embodiments described are not limited to the single application, and may be combined, for example, but not limited to, a combination of both embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.