阅读说明：本技术 晶体管接触区域增强 (Transistor contact area enhancement ) 是由 R·梅汉德鲁 T·加尼 S·塞亚 于 2019-05-29 设计创作，主要内容包括：本公开内容涉及晶体管接触区域增强,一种半导体器件,包括：包含表面的半导体主体；形成在半导体主体中的第一区域和第二区域,其中沟道区位于第一区域和第二区域之间,并且其中第二区域包括包含毯覆掺杂物的子区域；在半导体主体的位于第一区域上方的表面上的第一导电接触部；位于第一区域的底部的绝缘体上半导体(SOI)；形成在沟道中的袋状沟道掺杂物(PCD),其中PCD的第一部分与SOI的第一部分相邻；以及在子区域的底部部分上的第二导电接触部,其中第二导电接触部的第一部分与SOI的第二部分相邻,并且第二导电接触部的第二部分与PCD的第二部分相邻。(The present disclosure relates to transistor contact area enhancement, a semiconductor device comprising: a semiconductor body comprising a surface; a first region and a second region formed in the semiconductor body, wherein the channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant; a first conductive contact on a surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) located at a bottom of the first region; a Pocket Channel Dopant (PCD) formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI and a second portion of the second conductive contact is adjacent to a second portion of the PCD.)

1. A semiconductor device, comprising:

a semiconductor body comprising a surface;

a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant;

a first conductive contact on a surface of the semiconductor body above the first region;

a semiconductor-on-insulator (SOI) located at a bottom of the first region;

a Pocket Channel Dopant (PCD) formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and

a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

2. The semiconductor device of claim 1, wherein the first region is a source region and the second region is a drain region.

3. The semiconductor device of claim 1, wherein the first region is a drain region and the second region is a source region.

4. The semiconductor device of claim 1, 2 or 3, wherein the blanket dopant is phosphorus.

5. The semiconductor device of claim 1, 2 or 3, wherein the blanket dopant is boron.

6. The semiconductor device of claim 1, 2, or 3, wherein the blanket dopant height is between 5 nanometers (nm) and 100 nm.

7. A semiconductor device according to claim 1, 2 or 3, wherein the height of the SOI is between 5nm and 115 nm.

8. A semiconductor device according to claim 1, 2 or 3, wherein the PCD is phosphorus.

9. A semiconductor device according to claim 1, 2 or 3, wherein the PCD is boron.

10. A semiconductor device, comprising:

a semiconductor body comprising a surface;

a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant;

a first conductive contact on a surface of the semiconductor body above the first region;

a leakage barrier layer; and

a second conductive contact on a bottom portion of the sub-region, wherein at least a portion of the second conductive contact is adjacent to at least a portion of the leakage barrier layer.

11. The semiconductor device of claim 10, wherein the first region is a source region and the second region is a drain region.

12. The semiconductor device of claim 10 or 11, wherein the blanket dopant is phosphorus or boron.

13. The semiconductor device of claim 10 or 11, wherein the leakage barrier layer is a semiconductor-on-insulator (SOI), wherein the SOI is located at a bottom of the first region.

14. A semiconductor device according to claim 10 or 11, wherein the leakage barrier is a Pocket Channel Dopant (PCD) formed in the channel.

15. The semiconductor device of claim 14, wherein the PCD is phosphorus or boron.

16. The semiconductor device of claim 10 or 11, wherein the leakage barrier layer comprises:

an SOI, wherein the SOI is located at the bottom of the first region; and

a PCD formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI, a second portion of the SOI is adjacent to a first portion of the second conductive contact, and a second portion of the PCD is adjacent to a second portion of the second conductive contact.

17. The semiconductor device of claim 16, wherein the PCD is phosphorus or boron.

18. A system, comprising:

a memory; and

a processor coupled with the memory, wherein the processor comprises a semiconductor device comprising:

a semiconductor body comprising a surface;

a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant;

a first conductive contact on a surface of the semiconductor body above the first region;

a semiconductor-on-insulator (SOI) located at a bottom of the first region;

a Pocket Channel Dopant (PCD) formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and

a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and

wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

19. The system of claim 18, wherein the first region is a source region and the second region is a drain region.

20. The system of claim 18 or 19, wherein the blanket dopant is phosphorus or boron.

21. The system of claim 18 or 19, wherein the PCD is phosphorus or boron.

22. A method, comprising:

forming a semiconductor body comprising a surface;

forming a first region and a second region in the semiconductor body, wherein a channel region is defined in the semiconductor body and between the first region and the second region;

providing a blanket dopant in a sub-region of the second region;

forming a first conductive contact on a surface of the semiconductor body above the first region;

forming a semiconductor-on-insulator (SOI) at a bottom of the first region;

disposing Pocket Channel Dopant (PCD) in a channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and

forming a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

23. The method of claim 22, wherein the first region is a source region and the second region is a drain region.

24. The method of claim 22 or 23, wherein the blanket dopant is phosphorus or boron.

25. The method of claim 22 or 23, wherein the PCD is phosphorus or boron.

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor devices and processing, and in particular to transistor contact area enhancement.

Background

Scaling of features in integrated circuits has been a driving force behind the growing semiconductor industry over the last decades. Scaling to smaller and smaller features enables an increase in the density of functional units over the limited active area (realate) of a semiconductor chip. For example, shrinking transistor size allows a greater number of memory devices to be incorporated on a chip, thereby facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

Further reductions in the scale of integrated circuit devices have required increased use of non-planar transistors. As device pitch becomes smaller and smaller, the contact area decreases. As the contact area decreases, the contact resistance becomes more and more important.

Drawings

The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For convenience of description, the same reference numerals denote the same structural elements or components. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Fig. 1A, 1B, and 1C illustrate semiconductor devices according to various embodiments, wherein:

fig. 1A shows a front view of a semiconductor device;

FIG. 1B illustrates a cross-sectional view of the semiconductor device taken along line AA of FIG. 1A; and

fig. 1C shows a cross-sectional view of the semiconductor device taken along line BB of fig. 1A.

Fig. 2A, 2B, 2C, 2D, 2E, and 2F illustrate various stages of formation of the semiconductor device depicted in fig. 1A, in accordance with various embodiments, wherein:

FIG. 2A illustrates a three-dimensional view of a starting structure for forming a semiconductor device;

FIG. 2B shows a cross-sectional view of the structure of FIG. 2A taken along line CC of FIG. 2A;

FIG. 2C shows the structure of FIG. 2B, including line AA';

FIG. 2D illustrates a cross-sectional view of the structure of FIG. 2C taken along line A-A' of FIG. 2C to illustrate sub-regions and blanket dopants (blanket dopants);

FIG. 2E shows the structure of FIG. 2B, which includes semiconductor-on-insulator (SOI) and Pocket Channel Dopant (PCD); and

fig. 2F shows the structure of fig. 2E, further including a second conductive contact.

Fig. 3 illustrates an operational flow for forming the semiconductor device shown in fig. 1A.

Fig. 4 illustrates a front view of another semiconductor device, in accordance with various embodiments.

Fig. 5 illustrates an example electronic device that may include the semiconductor device shown in fig. 1A or fig. 4, in accordance with various embodiments.

FIG. 6 illustrates a processor coupled with a memory that may include various embodiments of the semiconductor device shown in FIG. 1A.

Detailed Description

Transistor contact area enhancement is described. The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the claimed embodiments. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure that the various aspects of the embodiments claimed may be practiced in other examples that depart from these specific details. In some instances, descriptions of well-known devices, circuits, integrated circuit design layouts and methods are omitted or simplified in order not to obscure the description of the embodiments of the present disclosure with unnecessary detail. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. For example, the height, width, depth, thickness, etc. of a substrate, layer, region, etc. may be exaggerated for clarity. In addition, it should be understood that the various embodiments shown in the figures may include elements that are present but may be hidden in a particular figure or figures.

Various aspects of the illustrative embodiments may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations may be set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that alternative embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

The phrases "in an embodiment," "in embodiments," "in various embodiments," "in some embodiments," and the like are used repeatedly. The phrase generally does not refer to the same embodiment; however, one or more of the same or different embodiments may, and thus may, be referred to. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrase "A or B" means (A), (B) or (A and B).

The following description may use specific terminology for the purpose of reference only, and is therefore not intended to be limiting. For example, perspective-based descriptions such as "upper," "lower," "above," "below," and "below" may refer to directions in the drawings to which reference is made. As another example, terms such as "front," "back," "top," "bottom," "back," and "side" may describe the orientation and/or position of portions of the component within a consistent but arbitrary frame of reference, as clearly embodied by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import. These descriptions are merely used to facilitate the discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

The term "and.. or" coupled to "and derivatives thereof may be used herein. "coupled" may mean one or more of the following. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element or a surface of another element, it can be directly on the other element or the surface of the element, or intervening elements may also be present, for example. Further, it will be understood that when an element is referred to as being "on" another element or a surface of another element, it can be "on" the other element or the surface of the other element regardless of whether the element is in a vertical orientation, a horizontal orientation, or an angled orientation. Further, description of a first element being formed, deposited, or otherwise disposed on or above a second element may mean that the first element is formed, deposited, or disposed over the second element or a surface of the second element, and at least a portion of the first element may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., with one or more other elements between the first element and the second element) with at least a portion of the second element.

Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Furthermore, example embodiments may be described as a process or operational flow, which is illustrated as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process or operational flow, many of the operations can be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. A process or operational flow may be terminated when its operations are completed, but additional operations may be included. A process or operational flow may correspond to a method, a function, a process step, a subroutine, or the like. When a procedure or operational flow corresponds to a function, its termination may correspond to a return of the function to the calling function and/or the main function.

Fig. 1A, 1B, and 1C illustrate a semiconductor device according to various embodiments. Fig. 1A shows a front view of the semiconductor device 100. Semiconductor device 100 may be, for example, any type of non-planar transistor, such as, but not limited to, a tri-gate transistor, a fin field effect transistor (FINFET), a tunnel FET (tfet), an omega-FET, a double gate transistor, or a nanowire, for example. In an embodiment, the semiconductor device 100 may be a Metal Oxide Semiconductor Fet (MOSFET), which may be a three-dimensional MOSFET. The semiconductor device 100 may be an isolated device or may be one of a plurality of nested devices. In addition, additional interconnect wiring may be fabricated to integrate these devices into an integrated circuit.

The semiconductor device 100 may include a semiconductor body 104. The semiconductor body 104 may also be referred to as a fin. The semiconductor body 104 may include a first surface 106 and a second surface 108 (not shown in fig. 1A), wherein the first surface 106 is opposite the second surface 108. The first surface 106 or the second surface 108 may be referred to herein as a surface. For example, the first surface 106 may be a top surface and the second surface 108 may be a bottom surface vertically opposite the top surface, or, for example, the first surface 106 may be a bottom surface and the second surface 108 may be a top surface vertically opposite the bottom surface, or, for example, the first surface 106 may be a first side surface, such as, for example, a left side surface or a right side surface, and the second surface 108 may be a second side surface horizontally opposite the first side surface, such as, for example, a right side surface or a left side surface, or the first surface 106 may be a first angled surface and the second surface 108 may be a second angled surface, i.e., opposite the first angled surface. Further, the top surface of the device or element may be referred to as the front side, while the bottom of the device or element may be referred to as the back side. The semiconductor body 104 may be formed of any material that can be reversibly changed from an insulating state to a conductive state by applying external electrical controls. For example, the semiconductor body 104 may be formed of a semiconductor material such as, but not limited to, silicon, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium indium arsenide, gallium antimonide.

The semiconductor device 100 may further include a first region 110 formed in the semiconductor body 104 and a second region 120 formed in the semiconductor body 104. Accordingly, the semiconductor body 104 may include a first region 110 and a second region 120 formed in the semiconductor body 104. The second region 120 may be located at a side of the semiconductor body 104 opposite to the side of the semiconductor body 104 comprising the first region 110. For example, as described below and shown in fig. 1A, the first region 110 and the second region 120 (described below) may be formed in the semiconductor body 104 on opposite sides of the channel region 130. In an embodiment, the first region 110 may be a drain region, and the second region 120 may be a source region. In another embodiment, the first region 110 may be a source region and the second region 120 may be a drain region. In an embodiment, the material of the semiconductor body 104 may be removed and replaced with another semiconductor material, for example by epitaxial deposition, to form the first region 110 and the second region 120, wherein the first region 110 and the second region 120 may be formed of a material such as, but not limited to, silicon, germanium, silicon germanium, or another III-V material (as described below). In one embodiment, the starting material of the semiconductor body 104 in the first region 110 may be doped to form the first region 110 and may be doped in the second region 120 to form the second region 120.

The first region 110 and the second region 120 may be formed to have the same conductivity type, such as N-type or P-type conductivity. In an embodiment, the first region 110 and the second region 120 may have a thickness of about 1 × 10¹⁹Atom/cm³And about 1X 10²¹Atom/cm³With the doping concentration in between. The first and second regions 110 and 120 may be formed to have a uniform concentration, or may be sub-regions of different concentrations or doping profiles (profiles). For example, the semiconductor device 100 may be a symmetric transistor, in which case the first region 110 and the second region 120 may comprise the same doping concentration and compositionAnd (3) cloth. Alternatively, the semiconductor device 100 may be an asymmetric transistor, in which case the doping concentrations and profiles of the first region 110 and the second region 120 may be varied in order to obtain specific electrical characteristics.

The semiconductor device 100 may further include a first conductive contact 112 formed on the first surface 106 of the semiconductor body 104 over the first region 110. In an embodiment, the first conductive contact 112 may be formed on an exposed surface of the semiconductor body 104, wherein the exposed surface may be on the first region 110. In another embodiment, the first conductive contact 112 may be formed on an exposed surface of the first region 110. The exposed surface on the first region 110 or within the first region 110 on which the first conductive contact 112 may be formed may be referred to as a first contact region or contact region. The first contact region may be a location where the first region 110 may be coupled with the first conductive contact 112. In an embodiment, the first conductive contact 112 may be deposited on the first surface 106 of the semiconductor body 104 without etching. In another embodiment, the first conductive contact 112 may be formed after a recess etch of the semiconductor body 104 over at least a portion of the first region 110 and deposition of the first conductive contact 112 on an exposed surface of the first region 110.

As shown in fig. 1B, the second region 120 may include a sub-region 122. The sub-region 122 may include a blanket dopant 124, which may also be referred to as a blanket source-drain dopant. In an embodiment, the sub-region 122 may be located at the bottom of the second region 120. Although embodiments herein may describe the sub-region 122 as being located at the bottom of the second region 120, the sub-region 122 may be located at the top of the second region 120 or at one side of the second region 120 if the semiconductor device 100 is in a different orientation than shown in fig. 1A. In an embodiment, the sub-region 122 may be defined by a region including a region 122A and a region 122B, as shown in fig. 1B, wherein the region 122A may be a sub-fin region, and wherein the region 122B may be an epitaxial region. In addition, the area 122A of the sub-area 122 may have a height L', and the sub-area 122 may have a height H_SR. In an embodiment of the present invention,the height L' of the region 122A may be in the range of 5 nanometers (nm), including 5nm, to 40nm, including 40nm, as measured as shown in fig. 1B. Furthermore, H_SRMay be in the range of 5nm (including 5nm) to 100nm (including 100 nm). If semiconductor device 100 is in a different orientation than shown in FIGS. 1A and 1B, heights L' and H may be measured as if semiconductor device 100 were oriented as shown in FIGS. 1A and 1B_SR. Furthermore, although embodiments herein may be described with reference to L' and H_SRBut other heights are described below if the semiconductor device 100 is in a different orientation than shown in fig. 1A, such height may be a width, a depth, or a thickness.

In an embodiment, the blanket dopant 124 may be implanted into the second region 120 through the region 122A of the sub-region 122. Although the embodiments herein depict blanket dopant 124 in both region 122A and region 122B of sub-region 122, blanket dopant 124 may be concentrated in region 122B, or all or substantially all of blanket dopant 124 may be in region 122B. Furthermore, the blanket dopants 124 may extend beyond the sub-regions 122, for example by diffusion. For example, blanket dopant 124 may extend into second region 120. Although the sub-region 122 is depicted as including a rectangular shape and a diamond shape, the sub-region 122 may have any other shape that may result from forming or otherwise processing the sub-region 122 or the second region 120. For example, the sub-region 122 may have a mushroom shape or any other shape. Although embodiments herein may include blanket dopants 124 adjacent to second conductive contacts 170 (described below), embodiments herein may include blanket dopants 124 that may be at least partially within second conductive contacts 170.

Blanket dopant 124 may be an implant that may dope second region 120 to eliminate, prevent, attenuate, reduce, or mitigate sub-fin leakage, which may be, for example, current leakage between source and drain regions of a transistor in an off state. In an embodiment, blanket dopant 124 may be phosphorous if, for example, semiconductor device 100 is an NMOS transistor. Although phosphorous is described as blanket dopant 124 for NMOS transistors, blanket dopant 124 may comprise materials such as, for example, but not limited to, nitrogen, antimony, or any group V material (described below). In another embodiment, blanket dopant 124 may be boron if, for example, semiconductor device 100 is a PMOS transistor. Although boron is described as the blanket dopant 124 for the PMOS transistor, the blanket dopant 124 for the PMOS transistor may comprise other materials such as, for example, but not limited to, silicon, germanium, aluminum, gallium, indium, scandium, or any group III material (described below). Further, the group III and group V materials may be dopants for a group IV (described below) substrate, and the group IV material may be a dopant for a group III-V (described below) substrate. Blanket dopant 124 may be any material that may eliminate, prevent, attenuate, reduce, or mitigate sub-fin leakage based at least in part on the type of substrate used to form (as described below) semiconductor device 100 and the type of dopants used to create first region 110 and second region 120.

Blanket dopant 124 may be formed by any suitable deposition or implantation process, such as, for example, but not limited to, an epitaxial chemical vapor deposition process or other deposition process, such as, for example, but not limited to, Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), High Density Plasma (HDP) assisted Chemical Vapor Deposition (CVD), or low temperature CVD.

A portion of the semiconductor body 104 between the first region 110 and the second region 120 may define a channel region 130 of the semiconductor device 100. Accordingly, the first region 110 may be adjacent to the channel region 130 on one side of the channel region 130 (which may be referred to as a first side of the channel region 130), and the second region 120 may be adjacent to the channel region 130 on the other side of the channel region 130 (which may be referred to as a second side of the channel region 130), the second side of the channel region 130 being opposite to the first side of the channel region 130. The first side of the channel region 130 may be the left side of the channel region 130, and the second side of the channel region 130 may be the right side of the channel region 130. Alternatively, the first side of the channel region 130 may be the right side of the channel region 130 and the second side of the channel region 130 may be the left side of the channel region 130. Although the first region 110 and the second region 120 are described as being located on the left and right sides of the channel region 130 based on the orientation of the semiconductor device 100 in fig. 1A, the first region 110 and the second region 120 may be located above and below each other at opposite sides of the channel region 130 if the semiconductor device 100 is in a different orientation than shown in fig. 1A.

In an embodiment, the channel region 130 may be intrinsic or undoped monocrystalline silicon. In another embodiment, channel region 130 may be doped monocrystalline silicon. When the channel region 130 is doped, it may be doped to about 1 × 10¹⁶Atom/cm³To about 1X 10¹⁹Atom/cm³The level of conductivity in between. Further, when the channel region 130 is doped, it may be doped to opposite conductivity types of the first and second regions 110 and 120. For example, the first region 110 and the second region 120 may be N-type conductivity, in which case the channel region 130 may be doped to P-type conductivity. As a result, the semiconductor device 100 may be formed as a negative channel mos (nmos) transistor. Similarly, for example, the first region 110 and the second region 120 may be P-type conductivity, in which case the channel region 130 may be doped to N-type conductivity. As a result, the semiconductor device 100 may be formed as a positive channel (PMOS) transistor. The channel region 130 may be uniformly doped. Alternatively, the channel region 130 may be doped non-uniformly or at different concentrations to provide specific electrical and performance characteristics.

The semiconductor device 100 may further include a gate structure 140 formed over the channel region 130. A gate structure 140 may be formed over the first surface 106 and a pair of sidewalls of the portion of the semiconductor body 104 located over the channel region 130. Thus, the channel region 130 as described above may be defined as the region of the semiconductor body 104 surrounded by the gate structure 140. Although the channel region 130 is located between the first region 110 and the second region 120, the first region 110 and the second region 120 may extend under the gate structure 140 to define the channel region 130, which may be smaller than the width of the gate structure 140.

The gate structure 140 may include a gate electrode layer (not shown) and a gate dielectric layer (not shown). In embodiments, the gate electrode layer may be formed from a variety of suitable metals or metal alloys, including materials such as, for example, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium nitride, tantalum nitride, aluminum, tungsten, copper, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In an embodiment, the gate dielectric layer may be formed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicate, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanium oxide, strontium titanate, strontium titanium oxide, barium strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

The gate structure 140 may also include a pair of spacers 142, one on either side of the gate structure 140, wherein the spacers 142 are formed on sidewalls of the gate structure 140. The spacers 142 may be formed of any suitable electrical insulator, dielectric, oxide, or nitride material. For example, the spacer 142 may be formed of silicon dioxide, silicon oxynitride, or silicon nitride, but is not limited thereto. Although the spacer 142 is depicted as comprising a single layer, the spacer 142 may comprise more than one layer, for example, to adjust an electrical characteristic (e.g., dielectric constant) of the spacer 142 or to adjust one or more physical dimensions.

Thus, the first region 110 and the second region 120 may be disposed in the semiconductor body 104, and the first conductive contact 112 may be disposed on the first region 110. Furthermore, the semiconductor body 104 may include a channel region 130 of the semiconductor device 100 and may be arranged between the first region 110 and the second region 120. A gate structure 140 may be disposed on and over the semiconductor body 104, and a gate spacer 142 may be disposed on either side of the gate structure 140. Although the sidewalls of the first and second regions 110, 120 are depicted as being relatively straight and vertical, the sidewalls of the first and second regions 110, 120 may be faceted or curvilinear, or any other shape that may result from the processing of the first and second regions 110, 120. Furthermore, the first and second regions 110, 120 may extend under the respective spacer 142 or under the respective spacer 142 and gate structure 140.

The semiconductor device 100 may further include an SOI150 at the bottom of the first region 110. In an embodiment, at least a first portion of the SOI150 may be adjacent to at least a first portion of the PCD160 (as described below), and at least a second portion of the SOI150 may be adjacent to at least a first portion of the second conductive contact 170 (as described below). In another embodiment, at least a portion of the SOI150 may be adjacent to at least a portion of the PCD 170 and at least a portion of the second conductive contact 170. The SOI150 may be in direct physical contact with the PCD160 and/or the second conductive contact 170, or in direct physical contact with at least a portion of the PCD160 and/or the second conductive contact 170, or in indirect contact with at least a portion of the PCD160 and/or the second conductive contact 170 (e.g., having one or more other elements between the SOI150 and the second conductive contact 170), or not in contact with the PCD160 or the second conductive contact 170. Although embodiments herein may describe the SOI150 as being located at the bottom of the first region 110, the SOI150 may be located at the top or at one side of the first region 110 if the semiconductor device 100 is in a different orientation than shown in fig. 1A. In an embodiment, at least a portion of the SOI150 may extend into the channel region 130 provided that the semiconductor device 100 is capable of operating as intended, e.g., with current flow when the semiconductor device 100 is in an "on" state, as described below. In another embodiment, the SOI150 may extend into the channel region 130 and into the second region 120, provided that the semiconductor device 100 is capable of operating as intended, for example, with current flow when the semiconductor device 100 is in an "on" state, as described below. In an embodiment, the SOI150 may be within the first region 110. In another embodiment, the SOI150 may comprise a portion that is internal to the semiconductor body 104 and a portion that is external to the semiconductor body 104.

In an embodiment, the SOI150 may have a height between 2nm and 115nm, such as, for example, between 2nm and 3 nm. Further, the height of the SOI150 may be at least equal to, or at least approximately or substantially equal to, the height of the second conductive contact 170. The SOI150 may have a uniform height or the SOI150 may have a varying height, for example, the SOI150 may have a particular height at a portion adjacent to the conductive contact 170 and a different height or a plurality of different heights at a portion or portions not adjacent to the conductive contact 170. Accordingly, all or a portion of the SOI150 may be formed to a height at least equal, at least approximately equal, or at least substantially equal to the height of the second conductive contact 170.

The SOI150 may be composed of a semiconductor material and an insulating material suitable for semiconductor device fabrication. The semiconductor material may be formed of a material such as, for example and without limitation, a lower bulk substrate composed of a single crystalline material, which may include, without limitation, silicon, germanium, silicon germanium, or a group III-V (as defined below) compound semiconductor material. The insulating material may be formed of a material that may include, for example, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride disposed on a semiconductor material.

Semiconductor device 110 may also include PCD160 formed in channel 130. Fig. 1A and 1C illustrate a PCD 160. The PCD160 may be a doped region formed in the channel region 130. In an embodiment, the PCD160 may be implanted into the channel 130 via a region having a height L' previously described in connection with the sub-region 122. The PCD160 may have a height between 5nm and 100 nm.

Although the semiconductor device 100 is described as including both the SOI150 and the PCD160, embodiments herein may include a semiconductor device 100 that includes one or the other. For example, in an embodiment, the semiconductor device 100 may include the SOI150 but not the PCD 160. Also, for example, in another embodiment, the semiconductor device 100 may include PCD160 but not SOI 150. Further, the combination of both the SOI150 and PCD160, or the SOI150 itself, or the PCD160 itself, may be referred to as a leak barrier.

In an embodiment, if the semiconductor device 100 includes both the SOI150 and the PCD160, at least a first portion of the PCD160 may be adjacent to at least a first portion of the SOI 150. In another embodiment, if the semiconductor device 100 includes both SOI150 and PCD160, at least a portion of PCD160 may be adjacent to at least a portion of SOI 150. The PCD160 may be in direct physical contact with a first portion of at least a portion of the SOI150, or in indirect contact with a first portion of at least a portion of the SOI150 (e.g., having one or more other elements between the PCD160 and the SOI 150), or not in contact with the SOI 150. PCD160 may be formed within channel region 130. However, the PCD 130 may extend into the second region 120 and form at the junction between the channel region 130 and the second region 120. Further, the PCD160 may extend into the first region 110 and may be formed at a junction between the channel region 130 and the first region 110.

In an embodiment, at least a second portion of the PCD160 may be adjacent to at least a second portion of the second conductive contact 170 (described below). In another embodiment, at least a portion of the PCD160 may be adjacent to at least a portion of the second conductive contact 170. In an embodiment, the PCD160 may be over the second conductive contact 170. Although embodiments herein may describe the PCD160 as being located above the second conductive contact 170, if the semiconductor device 100 is in a different orientation than shown in fig. 1A, the PCD160 may be below the second conductive contact 170 or to one side of the second conductive contact 170. The PCD160 may be in direct physical contact with the second conductive contact 170, or in indirect contact with the second conductive contact 170 (e.g., with one or more other elements between the PCD160 and the second conductive contact 170), or not in contact with the second conductive contact 170. Although embodiments herein may include a PCD160 adjacent to the second conductive contact 170, embodiments herein may also include a PCD160 at least partially within the second conductive contact 170. The PCD160 may have the same conductivity as the channel region 130, but a higher concentration compared to the doping of the channel region 130. The PCD160 may be formed by ion implanting dopants under the gate structure 140 using, for example, a tilted ion implantation or a tilted dopant implantation technique, or, for example, an angled ion implantation or an angled dopant implantation technique.

The PCD160 may be phosphorus or boron. PCD160 may be any material that may eliminate, prevent, attenuate, reduce, or mitigate sub-fin leakage as described above, based at least in part on the type of substrate used to form (as described below) semiconductor device 100 and the type of dopants used to create first region 110 and second region 120. For example, if the semiconductor device 100 includes source and drain regions of N-type conductivity, the PCD160 may be phosphorus. Although phosphorous is described as blanket dopant 124 for NMOS transistors, blanket dopant 124 may comprise materials such as, for example, but not limited to, nitrogen, antimony, or any group V material (described below). Further, for example, if the semiconductor device 100 includes source and drain regions of P-type conductivity, the PCD160 may be boron. Although boron is described as the blanket dopant 124 for the PMOS transistor, the blanket dopant 124 for the PMOS transistor may comprise other materials such as, for example, but not limited to, silicon, germanium, aluminum, gallium, indium, scandium, or any group III material (described below).

The semiconductor device 100 may further include a second conductive contact 170 formed on the bottom of the sub-region 122. In an embodiment, the second conductive contact 170 may be formed on an exposed surface of a bottom portion of the sub-region 122. In another embodiment, the second conductive contact 170 may be formed on an exposed surface of the second region 120 below the sub-region 122. The exposed surface on the bottom portion of the sub-region 122 on which the second conductive contact 170 may be formed or the exposed surface on the second region 120 on which the second conductive contact 170 may be formed may be referred to as a second contact region or contact region. The second contact region may be a location where the sub-region 122 may be coupled with the second conductive contact 170.

In an embodiment, if the semiconductor device 100 includes the SOI150, at least a first portion of the second conductive contact 170 may be adjacent to at least a second portion of the SOI 150. Further, if the semiconductor device 100 includes the PCD160, at least a second portion of the second conductive contact 170 may be adjacent to at least a second portion of the PCD 160. In an embodiment, the second conductive contact 170 may be deposited on a bottom portion of the sub-region 122 without etching or polishing. In another embodiment, the second conductive contact 170 may be formed, for example, after etching (which may be, for example, but not limited to, dry etching, wet etching, or both) or polishing (which may be, for example, but not limited to, chemical polishing, mechanical polishing, or Chemical Mechanical Polishing (CMP)) the substrate within at least a portion of the semiconductor body 104 or the second region 120, and depositing the second conductive contact 170 on the exposed surface of the sub-region 122 or on the exposed surface of the second region 120.

In an embodiment, the first conductive contact 112 may be a drain contact and the second conductive contact 170 may be a source contact. In another embodiment, the first conductive contact 112 may be a source contact and the second conductive contact 170 may be a drain contact. The first and second conductive contacts 112, 170 may be formed from a pure metal, such as, for example, but not limited to, titanium, tungsten, nickel, copper, or cobalt, or any other suitable metal; or may be an alloy such as, for example, but not limited to, a metal-metal alloy or a metal-semiconductor alloy, such as, for example, a silicide that may be formed by, for example, reacting a metal with silicon or silicon germanium. Although the first conductive contact 112 is shown on the first surface 106 of the semiconductor body 104, the first conductive contact 112 may be located on the second surface 108 of the semiconductor body 104. For example, the SOI150 may be etched to create a contact area for depositing the first conductive contact 112.

The contact area of the second conductive contact 170 may be enhanced due to the presence of the blanket dopant 124, the SOI150, and the PCD160, or any combination thereof, or any of these elements themselves, for example, because the contact area of the second conductive contact 170 may be larger than that of a conventional non-planar transistor. Further, for example, the contact area of the second conductive contact 170 may be an enhanced contact area in that it may be larger than the contact area of the first conductive contact 112, or, for example, the contact area of the second conductive contact 170 may be larger than if the second conductive contact 170 were formed on the first surface 106 over the second region 120.

The first conductive contact 112 (which may be, for example, a drain contact) may be contacted from the front side, and the second conductive contact 170 (which may be, for example, a source contact) may be contacted from the back side. Blanket dopant 124 may dope sub-regions 122, which may be referred to as HSI, which may be, for example, the height of semiconductor body 104 as measured from first surface 106, and blanket dopant 124 may be disposed on the side of semiconductor body 104 including the source region (or drain region) to eliminate, attenuate, prevent, mitigate, or reduce sub-fin leakage. Accordingly, the contact area of the second conductive contact 170 may be increased by using the available active area on one side of the semiconductor device 100 (which may be the source side, for example) below HSI. As a result, the source side contact resistance, which may be the dominant resistance in the "on" state of the transistor, may be reduced. Although the contact area may be increased by using the available active area below the HSI under the source side of the semiconductor device 100, the contact area for contact at the drain side of the semiconductor device 100 may be enhanced, thereby reducing the drain side contact resistance.

Although the contact area of the second conductive contact 170 may not be large if the semiconductor device 100 includes SOI150 without PCD160 or PCD160 without SOI150 as compared to the case where the semiconductor device 100 includes both SOI150 and PCD160, the sub-fin leakage as described above may be eliminated, mitigated, prevented, mitigated, or reduced by the blanket dopant 124, SOI150, or PCD160, or a combination thereof, or any of these elements themselves. For example, blanket dopant 124 may enter the sub-fin at the source side of semiconductor device 100. Furthermore, if the sub-region 122 is at the bottom or below the side of the semiconductor body 104 comprising the source region, a mask may be used to form the SOI150 at the bottom or below the side of the semiconductor body 104 comprising the drain region (or if the sub-region 122 is at the bottom or below the side of the semiconductor body 104 comprising the drain region, the SOI150 may be provided at the bottom or below the side of the semiconductor device 100 comprising the source region), thus producing an SOI only at the drain side and not at the source side, or mainly at the drain side (or only at the source side and not at the drain side, or mainly at the source side if the sub-region 122 is at the bottom or below the side of the semiconductor body 104 comprising the drain region). In addition, the PCD160 may be formed by tilted or blanket source (or drain if the sub-regions 122 are under the side of the semiconductor body 104 that includes the drain region) doping implants, for example, phosphorous for NMOS devices and boron for PMOS devices. Furthermore, the conductive contact may be formed by contact metal deposition in a contact area, which is an enhanced contact area, which may be, for example, a source side contact area, or may be, for example, a drain side contact area, for example.

As a result, the SOI150 and/or PCD160 placement may be used to turn off drain-source leakage (or also source-drain leakage) under the active fin and the size of the contact area of the second conductive contact 170 may be increased or enhanced relative to a non-planar transistor that is not formed in the same manner as the semiconductor device 100. For example, depending on the amount of active area of the fin, e.g., on the backside, a significant improvement in the contact area may be achieved. For example, the contact area of the second conductive contact 170 may be doubled for a 25nm remaining fin on the backside, and if the frontside dimension is about 50nm, the 25nm additional fin on the backside will provide an increase of, for example, 50 nanometers of perimeter for the contact area. In an embodiment, for example, if region 122A of sub-fin region 122 has a height L', as shown in fig. 1B, the total contact area as a result of contact area enhancement may be, for example, L_CAEqual to twice L' (or L)_CA2 x L'), wherein L_CAMay be the total length of the contact area of the conductive contact 170, which may be L as shown in fig. 1B_CA1And L_CA2The sum of (a) and (b). Although embodiments may include L_CAIs equal to twice L' (or L)_CA2 x L '), embodiments herein may include a total contact area of about twice as much as L ' (or 2 x L '), or may include a total contact area of up to and including twice as much as L ' (or 2 x L '). Furthermore, although embodiments may include as L_CA1And L_CA2L of the sum of_CAEmbodiments may include L as the sum of the length of any portion of the sub-region 122 or any portion of the sub-region 122 in contact with the second conductive contact 170 or coupled with the second conductive contact 170_CA。

Off-current flow or off-leakage may occur if the sub-region 122 is not doped or doped with the same dopant as the second region 120. Further, based on the coarse resistance distribution, this may provide, for example, a linear region drain current (Idlin) gain of about 25% and a saturation region drain current (Idsat) gain of about 12.5%, which may be larger in smaller pitches. Although the contact area of the second conductive contact 170 is described as an enhanced contact area, the contact area of the first conductive contact 112 may be an enhanced contact area, or both the contact area of the first conductive contact 112 and the contact area of the second conductive contact 170 may be enhanced contact areas.

In embodiments herein, when the gate structure 140 is in the "on" state, the current flow of the semiconductor device 100 may be as follows. Current may flow from the second conductive contact 170 to the second region 120, across the channel region 130, to the first region 110, and to the first conductive contact 112. Although the current flow is described as from the second conductive contact 170 to the first conductive contact 112 when the gate structure 140 is in an "on" state, embodiments herein may include current flow from the first conductive contact 112 to the first region 110, across the channel region 130, to the second region 120 and the second conductive contact 170 when the gate structure 140 is in an "on" state.

Fig. 2A, 2B, 2C, 2D, 2E, and 2F illustrate stages in the formation of the semiconductor device shown in fig. 1A, in accordance with various embodiments. As shown in fig. 2A, a starting structure for forming semiconductor device 100 may include a substrate 102. Substrate 102 may be formed of any suitable material for semiconductor device fabrication. In some embodiments, the substrate 102 may be a bulk substrate, which may include a group IV semiconductor material (e.g., Si, Ge, SiGe), a group III-V semiconductor material, or any other suitable material or materials; an X-on-insulator (XOI) structure, where X is one of the above materials (e.g., group IV and/or III-V semiconductor materials), and the insulator material is an oxide material or a dielectric material or some other electrically insulating material, such that the XOI structure includes a layer of electrically insulating material between two semiconductor layers; or some other suitable multilayer structure in which the top layer includes one of the semiconductor materials described above (e.g., a group IV or III-V semiconductor material). The use of "group IV semiconductor materials" (or "group IV materials" or generally "IV") herein may include at least one group IV element (e.g., silicon, germanium, carbon, tin), such as, for example, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. The use of "III-V semiconductor materials" (or "III-V materials" or generally "III-V") herein may include at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as, but not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum indium arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and the like. The use of "group V semiconductor materials" (or "group V materials" or generally "V") herein may include at least one group V element, such as, for example, but not limited to, nitrogen, phosphorus, arsenic, antimony, bismuth, and the like.

For example, the substrate 102 may be formed from a crystalline substrate formed using, for example, silicon, or the substrate 102 may be formed using materials such as, for example, but not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V compound semiconductor materials. Although some examples of materials from which the substrate 102 may be formed are described herein, any material that may serve as a foundation upon which a semiconductor device may be built may be used.

As further shown in fig. 2A, the substrate 102 may include one or more semiconductor bodies 104 formed on the substrate 102. Although fig. 2A shows four semiconductor bodies 104, embodiments herein are not limited to semiconductor devices 100 that include four semiconductor bodies 104. The semiconductor device 100 may include any number of semiconductor bodies 104, whether one semiconductor body 104 or more than one semiconductor body 104. In an embodiment, the semiconductor body 104 may be formed of the same material as the substrate 102. In another embodiment, the semiconductor body 104 may be formed of a material different from the material used to form the substrate 102.

As shown in fig. 2A and 2B, the semiconductor device 100 may further include a first region 110, a first conductive contact 112, a second region 120, a channel region 130, a gate structure 140, and a spacer 142. The semiconductor body 104, the first region 110, the first conductive contact 112, the second region 120, the channel region 130, the gate structure 140 and the spacer 142 are described above in connection with fig. 1A. As shown in connection with fig. 2B-2F, the substrate 102 may be removed during formation of the semiconductor device 100. The substrate 102 may be removed by any technique, such as, for example, but not limited to, a grinding process, a polishing process, a wet etching process, a dry etching process, or a cleaving process. Although embodiments herein may include a semiconductor device 100 that does not include a substrate 102, embodiments herein may include a semiconductor device 100 that may include at least a portion of a substrate 102.

As shown in fig. 2C and 2D, the semiconductor device 100 may also include the structure of fig. 2B, which may include sub-regions 122 and blanket dopants 124. The sub-regions 122 and the blanket dopants 124 are described above in connection with fig. 1A and 1B.

As shown in fig. 2E, semiconductor device 100 may also include the structure of fig. 2C, which may include SOI150 and PCD 160. The SOI150 and PCD160 are described above in connection with FIGS. 1A and 1C.

As shown in fig. 2F, the semiconductor device 100 may also include the structure of fig. 2E, which may include a second conductive contact 170. The second conductive contact 170 is described above in connection with fig. 1A. Although embodiments herein may include semiconductor devices 100 that do not include the second surface 108, embodiments herein may include semiconductor devices 100 that may include at least a portion of the second surface 108.

Fig. 3 illustrates an operational flow for forming the semiconductor device shown in fig. 1A. The operational flow 300 may include forming a semiconductor body 104 including a first surface 106 at 302. The operational flow 300 may include forming a first region 110 and a second region 120 in the semiconductor body 104 at 304, wherein a channel region 130 is defined in the semiconductor body between the first region 110 and the second region 120. Operational flow 300 may include disposing a blanket dopant 124 in a sub-region 122 of the second region 120 at 306. The operational flow 300 may include forming a first conductive contact 112 on the first surface 106 over the first region 110 at 308. In an embodiment, the operational flow 300 may also include forming the gate structure 140 and the spacers 142.

The operational flow 300 may also include forming the SOI150 at the bottom of the first region 110 at 310. The operational flow 300 may also include disposing the PCD160 in the channel region 130 at 312, where a first portion of the PCD160 may be adjacent to a first portion of the SOI 150. The operational flow 300 may also include forming a second conductive contact 170 on a bottom portion of the sub-region 122 at 314, wherein a first portion of the second conductive contact 170 may be adjacent to a second portion of the SOI150 and a second portion of the second conductive contact 170 may be adjacent to a second portion of the PCD 160.

Fig. 4 illustrates another semiconductor device according to various embodiments. Like semiconductor device 100, semiconductor device 400 may be, for example, any type of non-planar transistor, such as, for example, but not limited to, a tri-gate transistor, a FINFET, a TFET, an omega-FET, a double-gate transistor, or a nanowire. In an embodiment, similar to the semiconductor device 100, the semiconductor device 400 may be a MOSFET, which may be a three-dimensional MOSFET. The semiconductor device 400 is the same as the semiconductor device 100 described above, except as described in connection with fig. 4.

Semiconductor device 400 may include a semiconductor body 404. Semiconductor device 400 may include any number of semiconductor bodies 404, whether one semiconductor body 404 or more than one semiconductor body 404. Semiconductor body 404 may include a first surface 406, a first region 410, a first conductive contact 412, a second region 420, a channel region 430, a gate structure 440, and a spacer 442. The semiconductor body 404, the first surface 406, the first region 410, the first conductive contact 412, the second region 420, the channel region 430, the gate structure 440, and the spacer 442 are the same as the corresponding elements semiconductor body 104, first surface 106, first region 110, first conductive contact 112, second region 120, channel region 130, gate structure 140, and spacer 142 described above in connection with fig. 1A.

The semiconductor device 400 may also include a SOI450 at the bottom of the first region 410, where at least a portion of the SOI450 may be adjacent to at least a portion of the PCD460 (as described below). At least a portion of the SOI450 may be in direct physical contact with the PCD460, or in indirect contact with at least a portion of the second electrically conductive contact 460 (e.g., with one or more other elements between the SOI450 and the PCD 460), or not in contact with the PCD 460. SOI450 is identical to the corresponding component SOI150 described above in connection with fig. 1A, except as described in connection with fig. 4.

The semiconductor device 400 may further include PCD 460. PCD460 may be a doped region formed in channel region 430. In an embodiment, PCD460 may be implanted into channel 430 via a region having a height L' previously described in connection with sub-region 122. Although the semiconductor device 400 is described as including both SOI450 and PCD460, embodiments herein may include a semiconductor device 400 that includes one or the other. Further, the combination of both SOI450 and PCD460, or the SOI450 itself, or the PCD460 itself, may be referred to as a leakage barrier.

If the semiconductor device 400 includes both SOI450 and PCD460, at least a portion of PCD460 may be adjacent to at least a portion of SOI 450. At least a portion of PCD460 may be in direct physical contact with at least a portion of SOI450, or in indirect contact with at least a portion of SOI450 (e.g., having one or more other elements between PCD460 and SOI 450), or not in contact with SOI 450. PCD460 may be formed within channel region 430. However, the PCD 430 may extend into the second region 420 and be formed at a junction between the channel region 430 and the second region 420. Further, the PCD460 may extend into the first region 410 and may be formed at a junction between the channel region 430 and the first region 410.

PCD460 may be adjacent to SOI450 on one side of PCD460, and PCD460 may be adjacent to second conductive contact 470 (described below) on an opposite side of PCD460, where at least a portion of PCD460 may be adjacent to at least a portion of second conductive contact 470. PCD460 may be in direct contact with at least a portion of SOI450, or at least a portion of second conductive contact 470, or both; or indirectly in contact with at least a portion of the SOI450, or at least a portion of the second conductive contact 470, or both (e.g., with one or more other elements between the SOI450 or the second conductive contact 470, or both); or not in contact with the SOI450, or the second conductive contact 470, or both. While embodiments herein may include a PCD460 adjacent to the second conductive contact 470, embodiments herein may include a PCD460 at least partially within the second conductive contact 470. The PCD460 is identical to the corresponding element PCD160 described above in connection with FIG. 1A, except as described in connection with FIG. 4.

The semiconductor device 400 may further include a second conductive contact 470 formed on a bottom portion of the sub-region 422. In an embodiment, if the semiconductor device 400 includes PCD460 and SOI450, at least a portion of the second conductive contact 470 may be adjacent to at least a portion of PCD 460. In another embodiment, if the semiconductor device 400 includes an SOI450 and does not include PCD460, at least a portion of the second conductive contact 470 may be adjacent to at least a portion of the SOI 450. The second conductive contact 470 is the same as the corresponding element second conductive contact 170 described above in connection with fig. 1A, except as described in connection with fig. 4.

FIG. 5 illustrates an example electronic device, in accordance with various embodiments. The electronic device 500 may be, for example, a mobile communication device, or a desktop, or a rack-based electronic device. Electronic device 500 may include a motherboard, such as motherboard 502, which may also be referred to as a board. The board 502 may include a number of components including, but not limited to, a processor 504, a storage device 506, and at least one communication chip 508.

Depending on its applications, computing system 500 may include one or more other components that may or may not be physically and electrically coupled to board 502. These other components may include, but are not limited to, a graphics processor, a digital signal processor, an encryption processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier (amp), a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.).

The processor 504 of the electronic device 500 may include one or more devices according to various embodiments described herein, such as the semiconductor device 100 or the semiconductor device 400 according to various embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The electronic device 500 may include a storage device 506. In some embodiments, storage 506 may include one or more solid state drives. Examples of storage devices that may be included in storage device 506 include, but are not limited to, volatile memory (e.g., Dynamic Random Access Memory (DRAM)), non-volatile memory (e.g., read only memory, ROM), flash memory, and mass storage devices (such as hard drives, Compact Discs (CDs), Digital Versatile Discs (DVDs), etc.). Fig. 6 illustrates a processor 602 coupled to a memory 604, wherein the processor 602 may include various embodiments of the semiconductor device 100. The processor 602 may also include various embodiments of the semiconductor device 400.

The communication chip 508 and the antenna may enable wireless communication for transferring data to and from the electronic device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wiring, although in some embodiments they may not. The communication chip 508 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project, and any revisions, updates, and/or revisions (e.g., LTE-advanced project, Ultra Mobile Broadband (UMB) project (also referred to as "3 GPP 2"), etc.). IEEE 802.16 compliant Broadband Wide Area (BWA) networks, commonly referred to as WiMAX (acronym for worldwide interoperability for microwave access) networks, are certification marks for products that pass conformance and interoperability tests for the IEEE 802.16 standard. The communication chip 508 may operate in accordance with a global system for mobile communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), evolved HSPA (E-HSPA), or LTE network. The communication chip 508 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 508 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), digital enhanced wireless telecommunications (DECT), evolution-data optimized (EV-DO), derivatives thereof, and other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, the communication chip 508 may operate according to other wireless protocols.

The electronic device 500 may include a plurality of communication chips 508. For example, the first communication chip 508 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 508 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and the like. In some embodiments, the communication chip 508 may support wired communication. For example, the electronic device 500 may include one or more wired servers.

In various implementations, the electronic device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, the electronic device 500 may be any other electronic device that processes data. In some embodiments, the recessed conductive contacts disclosed herein may be implemented in high performance electronic devices.

Some non-limiting examples are provided below.

Examples of the invention

Example 1 may include a semiconductor device comprising: a semiconductor body comprising a surface; a first region and a second region formed in the semiconductor body, wherein the channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant; a first conductive contact on a surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) located at a bottom of the first region; a Pocket Channel Dopant (PCD) formed in the channel, wherein the PCD is adjacent to the first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Example 2 may include the semiconductor device of example 1 or some other example herein, wherein the first region is a source region and the second region is a drain region.

Example 3 may include the semiconductor device of example 1 or some other example herein, wherein the first region is a drain region and the second region is a source region.

Example 4 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the blanket dopant is phosphorus.

Example 5 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the blanket dopant is boron.

Example 6 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the height of the blanket dopant is between 5 nanometers (nm) and 100 nm.

Example 7 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the SOI has a height between 5nm and 115 nm.

Example 8 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the PCD is phosphorus.

Example 9 may include the semiconductor device of examples 1, 2, or 3, or some other example herein, wherein the PCD is boron.

Example 10 may include a semiconductor device comprising: a semiconductor body comprising a surface; a first region and a second region formed in the semiconductor body, wherein the channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant; a first conductive contact on a surface of the semiconductor body above the first region; a leakage barrier layer; a second conductive contact on a bottom portion of the sub-region, wherein at least a portion of the second conductive contact is adjacent to at least a portion of the leakage barrier layer.

Example 11 may include the semiconductor device of example 10 or some other example herein, wherein the first region is a source region and the second region is a drain region.

Example 12 may include the semiconductor device of examples 10, 11, or some other example herein, wherein the blanket dopant is phosphorus or boron.

Example 13 may include the semiconductor device of claim 10, 11, or some other example herein, wherein the leakage barrier is a semiconductor-on-insulator (SOI), wherein the SOI is located at a bottom of the first region.

Example 14 may include the semiconductor device of examples 10, 11, or some other example herein, wherein the leakage barrier is a Pocket Channel Dopant (PCD) formed in the channel.

Example 15 may include the semiconductor device of example 14 or some other example herein, wherein the PCD is phosphorus or boron.

Example 16 may include the semiconductor device of claim 10, 11, or some other example herein, wherein the leakage barrier layer comprises: SOI, wherein the SOI is located at the bottom of the first region; a PCD formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI, a second portion of the SOI is adjacent to a first portion of the second conductive contact, and a second portion of the PCD is adjacent to a second portion of the second conductive contact.

Example 17 may include the semiconductor device of example 16 or some other example herein, wherein the PCD is phosphorus or boron.

Example 18 may include a system comprising: a memory; a processor coupled with the memory, wherein the processor includes a semiconductor device comprising: a semiconductor body comprising a surface; a first region and a second region formed in the semiconductor body, wherein the channel region is located between the first region and the second region, and wherein the second region comprises a sub-region comprising a blanket dopant; a first conductive contact on a surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) located at a bottom of the first region; a Pocket Channel Dopant (PCD) formed in the channel, wherein the PCD is adjacent to the first portion of the SOI; a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Example 19 may include the system of example 18 or some other example herein, wherein the first region is a source region and the second region is a drain region.

Example 20 may include the system of examples 18, 19, or some other example herein, wherein the blanket dopant is phosphorus or boron.

Example 21 may include the system of examples 18, 19, or some other example herein, wherein the PCD is phosphorus or boron.

Example 22 may include a method comprising: forming a semiconductor body comprising a surface; forming a first region and a second region in the semiconductor body, wherein a channel region is defined in the semiconductor body between the first region and the second region; providing a blanket dopant in a sub-region of the second region; forming a first conductive contact on a surface of the semiconductor body above the first region; forming a semiconductor-on-insulator (SOI) at a bottom of the first region; disposing a Pocket Channel Dopant (PCD) in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and forming a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Example 23 may include the method of example 22 or some other example herein, wherein the first region is a source region and the second region is a drain region.

Example 24 may include the methods of examples 22, 23, or some other example herein, wherein the blanket dopant is phosphorus or boron.

Example 25 may include the method of examples 22, 23, or some other example herein, wherein the PCD is phosphorus or boron.

Various embodiments may include any suitable combination of the above-described embodiments, including alternative (or) embodiments to the embodiments described above in combination (and) (e.g., "and" may be "and/or"). Further, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, result in the acts of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for performing various operations of the above-described embodiments.

The above description of illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to limit embodiments of the disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications can be made to the embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.