阅读说明：本技术 用于iii-v族金属氧化物半导体场效应晶体管（mosfet）的沟道层形成 (Channel layer formation for group III-V Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) ) 是由 S·马 N·米努蒂洛 C-y·黄 T·加尼 J·卡瓦利罗斯 A·默西 H·肯内尔 G· 于 2019-05-29 设计创作，主要内容包括：本文中的实施例说明了用于半导体器件的技术、系统和方法。半导体器件可以包括隔离区,其位于衬底上方以在隔离区之间形成沟槽。第一缓冲层位于衬底之上,与衬底接触并位于沟槽内。第二缓冲层位于沟槽内,在第一缓冲层之上并与第一缓冲层接触。沟道区位于第一缓冲层上方,位于第二缓冲层的在源极区或漏极区之下的部分上方,并且不竖直位于第二缓冲层的部分上方。另外,源极区或漏极区位于第二缓冲层上方,与第二缓冲层接触,并且与沟道区相邻。可以说明和/或要求保护其他实施例。(Embodiments herein describe techniques, systems, and methods for semiconductor devices. The semiconductor device may include isolation regions over the substrate to form trenches between the isolation regions. The first buffer layer is located above the substrate, in contact with the substrate, and within the trench. The second buffer layer is located in the trench, over and in contact with the first buffer layer. The channel region is located above the first buffer layer, above a portion of the second buffer layer that is below the source or drain region, and not vertically above a portion of the second buffer layer. In addition, a source or drain region is over the second buffer layer, in contact with the second buffer layer, and adjacent to the channel region. Other embodiments may be described and/or claimed.)

1. A semiconductor device, comprising:

isolation regions over a substrate to form trenches therebetween;

a first buffer layer over the substrate, in contact with the substrate and within the trench;

the second buffer layer in the groove is positioned above the first buffer layer and is in contact with the first buffer layer;

a channel region over the first buffer layer, over a portion of the second buffer layer under the source or drain region, and not vertically over a portion of the second buffer layer, wherein the channel region comprises a III-V material;

a high-k gate dielectric layer over the first buffer layer and completely surrounding the channel region;

a gate electrode over the first buffer layer without overlapping the second buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region;

a source region over the second buffer layer, in contact with the second buffer layer, and adjacent to a first end of the channel region; and

a drain region over the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel region opposite the first end of the channel region.

2. The semiconductor device of claim 1, further comprising:

a source electrode coupled to the source region; and

a drain electrode coupled to the drain region.

3. The semiconductor device of claim 1 or 2, wherein the second buffer layer is coplanar with a surface of the isolation region, and the channel region, the source region, and the drain region are located above the surface of the isolation region.

4. The semiconductor device according to claim 1 or 2, wherein a surface of the substrate in contact with the first buffer layer is a non-planar surface.

5. The semiconductor device of claim 1 or 2, wherein the channel region has a shape selected from the group consisting of a rectangular shape, a square shape, an oval shape, and a circular shape, and a width of the trench is substantially equal to a width of the channel region.

6. The semiconductor device of claim 1 or 2, wherein the channel region comprises a channel selected from the group consisting of a nanowire channel, a nanoribbon channel, and a full-halo gate channel.

7. The semiconductor device according to claim 1 or 2, wherein the channel region has a triangular shape.

8. The semiconductor device of claim 1 or 2, wherein the channel region has a 111 crystal orientation.

9. The semiconductor device of claim 1 or 2, wherein the III-V material of the channel region comprises a material selected from the group consisting of indium (In), phosphorus (P), gallium (Ga), and arsenic (As).

10. The semiconductor device of claim 1 or 2, wherein the source region or the drain region comprises an n-type dopant.

11. The semiconductor device of claim 1 or 2, wherein the source region or the drain region comprises a material selected from the group consisting of In, P, Ga, or As, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium antimonide (InSb), indium gallium antimonide (InGaSb), indium gallium arsenide antimonide (In), and gallium arsenide antimonide (In)_xGa_1-xAs_ySb_1-y) Indium gallium arsenide (In) phosphide_xGa_1-xAs_yP_1-y) Indium gallium phosphorus antimonide (In)_xGa_1-xP_ySb_1-y) Indium aluminum arsenic antimonide (In)_xAl_1-xAs_ySb_1-y) Indium aluminum arsenic phosphide (In)_xAl_1-xAs_yP_1-y) And narrow band gap group III-V materials, and any combination thereof, wherein x is 0. ltoreq. x.ltoreq.1, and y is 0. ltoreq. y.ltoreq.1.

12. The semiconductor device of claim 1 or 2, wherein the substrate comprises a material selected from the group consisting of a high resistivity p-type or n-type vicinal silicon material, germanium-on-silicon, gallium arsenide (GaAs), and a silicon-on-insulator substrate.

13. The semiconductor device of claim 1 or 2, wherein the first buffer layer comprises a material selected from the group consisting of gallium arsenide (GaAs), polycrystalline GaAs, InP, AlAs, GaP, AlAsSb, InAlAs, and In_xGa_1-xAs, wherein x is between 0 and 1.

14. The semiconductor device of claim 1 or 2, wherein the second buffer layer comprises a material having a different etch selectivity than the III-V material in the channel region.

15. The semiconductor device according to claim 1 or 2, wherein the first buffer layer comprises GaAs, and the second buffer layer comprises In_xGa_1-xAs, where x is between 0 and 1, and the III-V material in the channel region comprises InP.

16. A method for forming a semiconductor device, the method comprising:

forming isolation regions over a substrate and forming trenches between the isolation regions;

forming a first buffer layer over the substrate, in contact with the substrate and within the trench;

forming a second buffer layer over the first buffer layer, in contact with the first buffer layer and within the trench;

forming a channel region comprising InP over a portion of the second buffer layer;

removing a portion of the second buffer layer under the channel region while leaving the second buffer layer in a region not overlapping the channel region;

forming a high-k gate dielectric layer over the first buffer layer and completely around the channel region;

forming a gate electrode over the first buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region;

forming a source region over the second buffer layer, in contact with the second buffer layer and adjacent to the first end of the channel region; and

a drain region is formed over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region.

17. The method of claim 16, wherein removing the second buffer layer under the channel region comprises removing the second buffer layer under the channel region by selective etching.

18. The method of claim 16 or 17, wherein the second buffer layer is coplanar with a surface of the isolation region, and the channel region, the source region, and the drain region are located above the surface of the isolation region.

19. The method of claim 16 or 17, wherein the channel region has a triangular shape and has a 111 crystal orientation.

20. The method of claim 16 or 17, wherein the first buffer layer comprises a material selected from the group consisting of gallium arsenide (GaAs), polycrystalline GaAs, InP, AlAs, GaP, AlAsSb, InAlAs, and In_xGa_1-xAs, wherein x is between 0 and 1.

21. The method of claim 16 or 17, wherein the first buffer layer comprises GaAs and the second buffer layer comprises In_xGa_1-xAs, where x is between 0 and 1.

22. A computing device, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device or the processor comprises a transistor comprising:

isolation regions over a substrate to form trenches therebetween;

a first buffer layer over the substrate, in contact with the substrate and within the trench;

the second buffer layer in the groove is positioned above the first buffer layer and is in contact with the first buffer layer;

a channel region over the first buffer layer, over a portion of the second buffer layer under a source or drain region, and not vertically over a portion of the second buffer layer, wherein the channel region comprises a III-V material;

a high-k gate dielectric layer over the first buffer layer and completely surrounding the channel region;

a gate electrode over the first buffer layer without overlapping the second buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region;

a source region over the second buffer layer, in contact with the second buffer layer, and adjacent to a first end of the channel region; and

a drain region over the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel region opposite the first end of the channel region.

23. The computing device of claim 22, wherein a surface of the substrate in contact with the first buffer layer is a non-planar surface.

24. The computing device of claim 22 or 23, wherein the first buffer layer comprises GaAs and the second buffer layer comprises In_xGa_1-xAs, wherein x is between 0 and 1, and the III-V material in the channel region comprises InP.

25. The computing device of claim 22 or 23, wherein the computing device comprises a device selected from the group consisting of a wearable device or a mobile computing device comprising one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, a geiger counter, an accelerometer, a gyroscope, a speaker, and a camera coupled with the processor.

Technical Field

Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly, to group III-V Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

Background

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

Conventional integrated circuits, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), may be based on silicon. On the other hand, compounds of group III-V elements may have semiconductor properties that are superior to silicon, including higher electron mobility and saturation velocity, resulting in better performance of group III-V MOSFETs or, in short, III-V transistors. However, the manufacturing process of the III-V MOSFET is complicated and the product defect rate is high.

Drawings

The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Fig. 1(a) -1(c) schematically illustrate, in various views, an example III-V Metal Oxide Semiconductor Field Effect Transistor (MOSFET) including a channel region over a buffer layer within a trench, in accordance with some embodiments.

Fig. 2 schematically illustrates an example III-V MOSFET including a channel region over a buffer layer within a trench, in accordance with some embodiments.

Fig. 3 schematically illustrates an example process for forming a III-V MOSFET including a channel region over a buffer layer within a trench, in accordance with some embodiments.

Fig. 4(a) -4(f) schematically illustrate an exemplary process with more detail for forming a III-V MOSFET including a channel region over a buffer layer within a trench, according to some embodiments.

Fig. 5 schematically illustrates an interposer implementing one or more embodiments of the present disclosure, in accordance with some embodiments.

FIG. 6 schematically illustrates a computing device constructed in accordance with embodiments of the disclosure, in accordance with some embodiments.

Detailed Description

Compounds of group III-V elements, such as gallium arsenide (GaAs), indium antimonide (InSb), indium phosphide (InP), and indium gallium arsenide (InGaAs), have semiconductor properties superior to silicon, including higher electron mobility and saturation velocity. As a result, III-V Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may also have better performance than silicon transistors. A III-V MOSFET or simply a III-V transistor may include source and drain regions adjacent to a channel region. For the following description, the source and drain regions may be used interchangeably.

Sometimes, III-V transistors may be fabricated using Aspect Ratio Trapping (ART) trenches. However, III-V transistors fabricated using ART trenches may have low density states and high defect rates, such as stack dislocations formed during material growth in the confined channel in the ART trench. In addition, there may be a large lattice mismatch between the III-V material in the channel region and the material in the ART trench, which may lead to a large number of misfit dislocations and stack dislocations in the channel region. Some approaches may use lattice matched sub-fin epitaxial layers such as InAlAs to reduce the number of misfit dislocations in the channel region. However, such lattice matched sub-fin epitaxial layers may be difficult to fabricate in limited geometries such as ART trenches. As a result, more defects may be generated from the lattice matched sub-fin epitaxial layers that propagate into the channel region.

Embodiments herein may form a first buffer layer over the substrate within the ART trench and a second buffer layer over the first buffer layer, in contact with the first buffer layer and within the trench. A channel region may be formed over a portion of the second buffer layer. For example, the first buffer layer may include GaAs and the channel region may include InP, which may have a large lattice mismatch with GaAs in the first buffer layer. A second layer of InGaAs may be formed over the first buffer layer of GaAs. A channel region comprising InP may be formed by lattice matching over the second buffer layer of InGaAs. Thus, the channel region comprising InP may be virtually free of any misfit dislocations. Then, the second buffer layer of InGaAs may be removed below the channel region, and a gate dielectric layer and a gate electrode may be formed between the channel region and the first buffer layer, occupying the space that the second buffer layer had occupied prior to removal of the second buffer layer. Embodiments so formed using two buffer layers may reduce defects, i.e., misfit dislocations, in the channel region comprising InP and thus improve the performance of III-V transistors.

Embodiments herein may provide a semiconductor device. The semiconductor device may include isolation regions over the substrate to form trenches between the isolation regions. A first buffer layer is over, in contact with, and within the trench. The second buffer layer is located in the trench, over and in contact with the first buffer layer. The channel region is located above the first buffer layer, above a portion of the second buffer layer that is below the source or drain region, and not vertically above a portion of the second buffer layer. The channel region includes a group III-V material. A high-k gate dielectric layer is over the first buffer layer and completely surrounds the channel region. The gate electrode is located over the first buffer layer without overlapping the second buffer layer, completely surrounds the high-k gate dielectric layer, and completely surrounds the channel region. In addition, the source region is located above the second buffer layer, contacts the second buffer layer, and is adjacent to the first end of the channel region. The drain region is over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region.

Embodiments herein may present a method for forming a semiconductor device. The method may include forming isolation regions over a substrate and forming trenches between the isolation regions; forming a first buffer layer over the substrate, in contact with the substrate and within the trench; and forming a second buffer layer over the first buffer layer, in contact with the first buffer layer and within the trench. The method also includes forming a channel region comprising InP over a portion of the second buffer layer, and removing a portion of the second buffer layer under the channel region while leaving the second buffer layer in a region that does not overlap the channel region. Further, the method may include forming a high-k gate dielectric layer over the first buffer layer and completely around the channel region. Also, the method includes forming a gate electrode over the first buffer layer that completely surrounds the high-k gate dielectric layer and completely surrounds the channel region. In addition, the method includes forming a source region over the second buffer layer, in contact with the second buffer layer and adjacent to a first end of the channel region, and forming a drain region over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region.

Embodiments herein may be directed to a computing device. The computing device may include a processor; and a memory device coupled to the processor, wherein the memory device or the processor includes a transistor. The transistor may include isolation regions over the substrate to form trenches between the isolation regions. The first buffer layer is located over the substrate, in contact with the substrate, and within the trench. The second buffer layer is located in the trench, over and in contact with the first buffer layer. The channel region is located above the first buffer layer, above a portion of the second buffer layer that is below the source or drain region, and not vertically above a portion of the second buffer layer. The channel region includes a group III-V material. A high-k gate dielectric layer is over the first buffer layer and completely surrounds the channel region. The gate electrode is located over the first buffer layer without overlapping the second buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region. In addition, the source region is located above the second buffer layer, contacts the second buffer layer, and is adjacent to the first end of the channel region. The drain region is over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region.

In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without some of these specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, the operations may be performed out of the order presented.

For the purposes of this disclosure, the phrase "a and/or B" means (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The terms "above … …," "below … …," "between … …," "above … …," and "on … …" as used herein may refer to the relative position of one layer of material or component with respect to other layers or components. For example, one layer disposed above or below another layer may be directly in contact with the other layer, or may have one or more intervening layers. Also, one layer disposed between two layers may be directly in contact with the two layers, or may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, a feature disposed between two features may be in direct contact with adjacent features, or may have one or more intervening features, unless expressly stated otherwise.

The description may use the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with … …" and derivatives thereof may be used herein. "coupled" may mean one or more of the following. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and that one or more other elements are coupled or connected between the elements that are coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a portion of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., with one or more other features between the first feature and the second feature) with at least a portion of the second feature.

Where the disclosure recites "a" or "a first" element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Moreover, ordinal indicators (e.g., first, second or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor a particular position or order of such elements unless otherwise specifically stated.

As used herein, the term "circuitry" may refer to or include portions of: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop, a set-top box, a gaming console, and so forth.

Embodiments of the present disclosure may be formed or implemented on a substrate (e.g., a semiconductor substrate). In one embodiment, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials, which may or may not be bonded to silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), may be fabricated on a substrate. In various embodiments of the present disclosure, the MOS transistor may be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors, such as double-gate transistors and triple-gate transistors, and wrap-around or full-wrap gate transistors, such as nanoribbon and nanowire transistors. Although the embodiments described herein may only show planar transistors, it should be noted that the present disclosure may also be implemented using non-planar transistors.

Each MOS transistor includes a gate stack formed of at least two layers (a gate dielectric layer and a gate electrode layer). The gate dielectric layer may comprise a layer or a stack of layers. One or more layers may comprise silicon oxide, silicon dioxide (SiO)₂) And/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric layer to improve the quality of the high-k material when used.

The gate electrode layer is formed on the gate dielectric layer and may be composed of at least one P-type work function metal or N-type work function metal depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode layer may be comprised of a stack of two or more metal layers, wherein one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will be capable of forming a PMOS gate electrode with a workfunction between about 4.9eV and about 5.2 eV. For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will be capable of forming an NMOS gate electrode with a workfunction between about 3.9eV and about 4.2 eV.

In some embodiments, the gate electrode may be comprised of a "U" shaped structure comprising a bottom portion substantially parallel to the substrate surface, and two sidewall portions substantially perpendicular to the top surface of the substrate when the cross-section of the transistor is viewed in the source-channel-drain direction. In another embodiment, at least one of the metal layers forming the gate electrode may be only a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In further embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

In some embodiments of the present disclosure, a pair of sidewall spacers may be formed on opposite sides of the gate stack, sandwiching the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process operations. In alternative embodiments, multiple pairs of spacers may be used, for example, two, three or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

As is well known in the art, source and drain regions are formed in the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are typically formed using an implant/diffusion process or an etch/deposition process. In the former process, a dopant such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate to form the source and drain regions. The annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the location of the source and drain regions. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the source and drain regions. In some embodiments, the source and drain regions may be fabricated using a silicon alloy (e.g., silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternative semiconductor materials (e.g., germanium or a III-V material or alloy). Also, in further embodiments, the source and drain regions may be formed using one or more layers of metals and/or metal alloys.

One or more interlayer dielectrics (ILDs) are deposited over the MOS transistors. The ILD layer may be formed using dielectric materials known to be suitable for use in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO)₂) Carbon Doped Oxide (CDO), silicon nitride, organic polymers (e.g., perfluorocyclobutane or polytetrafluoroethylene), fluorosilicate glass (FSG), and organosilicates (e.g., silsesquioxane, siloxane) or organosilicate glass. The ILD layer may include voids or air gaps to further reduce its dielectric constant.

Fig. 1(a) -1(c) schematically illustrate, in various views, an example III-V MOSFET 100 including a channel region 107 over a buffer layer 102 within a trench 110, according to some embodiments. For example, figure 1(a) shows a cross-sectional view of a fin cut at a source or drain region of a III-V MOSFET 100. Figure 1(b) shows a cross-sectional view of a fin cut at the gate electrode of III-V MOSFET 100. Fig. 1(c) shows a cross-sectional view of a gate cut at an active channel region or fin of III-V MOSFET 100. For clarity, the features of III-V MOSFET 100, channel region 107, buffer layer 102, or trench 110, are described below as examples for understanding a III-V MOSFET that includes a channel region over a buffer layer within a trench. Further, it should be understood that one or more components of a III-V MOSFET including a channel region over a buffer layer within a trench may include additional and/or alternative features described below, and may include any device that one of ordinary skill in the art would recognize and/or refer to as a III-V MOSFET including a channel region over a buffer layer within a trench.

In an embodiment, the III-V MOSFET 100 includes a substrate 101. Isolation regions (e.g., isolation region 103 and isolation region 105) are located over substrate 101 to form trench 110 between isolation region 103 and isolation region 105. The trench 110 may be an ART trench. In some other embodiments, the trench 110 may be other kinds of trenches. The buffer layer 102 is located above the substrate 101, in contact with the substrate 101, and within the trench 110. The surface 112 of the substrate 101 in contact with the buffer layer 102 is a non-planar surface, such as a triangular surface. The buffer layer 104 is positioned within the trench 110, over the buffer layer 102, and in contact with the buffer layer 102. The buffer layer 104 is coplanar with the surface of the isolation region 103 and coplanar with the surface of the isolation region 105.

As shown in fig. 1(b), the channel region 107 is located above the buffer layer 102 and comprises a III-V material. The buffer layer 104 is removed below the channel region 107 so that the channel region 107 is vertically above the buffer layer 102, but not vertically above the buffer layer 104. The channel region 107 is located above the portion of the buffer layer 104 under the source region 113 or the drain region 123, as shown in fig. 1 (c). A gate dielectric layer 109 is located over the buffer layer 102 and completely surrounds the channel region 107. The gate dielectric layer may comprise a high-k dielectric material. The gate electrode 111 is located above the buffer layer 102, without overlapping the buffer layer 104, completely surrounding the gate dielectric layer 109 and completely surrounding the channel region 107.

As shown in fig. 1(c), the source region 113 is located above the buffer layer 104, in contact with the buffer layer 104 and adjacent to the first end of the channel region 107. The drain region 123 is positioned above the buffer layer 104, in contact with the buffer layer 104, and adjacent to a second end of the channel region 107 opposite to the first end of the channel region 107. Channel region 107, source region 113, and drain region 123 are located over the surfaces of isolation region 103 and isolation region 105. In addition, a second source electrode 114 is located above the source region 113, and a source electrode 115 is coupled to the second source region 114. A second drain region 124 is located above the drain region 123, and a drain electrode 125 is coupled to the second drain region 124. The spacer 131 separates the gate electrode 111 from the source electrode 115, and the spacer 133 separates the gate electrode 111 from the drain electrode 125. In some embodiments, there may be no second source region or second drain region. A source electrode 115 may be coupled to the source region 113 and a drain electrode 125 may be coupled to the drain region 123.

In an embodiment, the channel region 107 may be a FinFET channel, a nanowire channel, a vertical FET channel, a nanotube channel, a full ring gate channel, or a nanoribbon channel. Channel region 107 may have a width W1, and trench 110 may have a width W2, which may be substantially equal to W1. The channel region 107 includes a group III-V compound, which may be a binary group III-V compound, a ternary group III-V compound, or a quaternary group III-V compound. In detail, the III-V compound In the channel region 107 may include indium (In), phosphorus (P), gallium (Ga) or arsenic (As), SiGe, Al, GaAs, In_xGa_1-xAs、In_xGa_1-xP、GaAs_xSb_1-x(where x is between 0 and 1), InSb, InAs, GaP, InGaP, or InP. The channel region 107 may have a rectangular shape, a triangular shape, a square shape, an oval shape, a circular shape, or a polygonal shape.

In an embodiment, the buffer layer 102 may include gallium arsenide (GaAs), polycrystalline GaAs, InP, AlAs, GaP, AlAsSb, InAlAs, or In_xGa_1-xAs, where x is between 0 and 1. The buffer layer 104 may include a material having a different etch selectivity than the III-V material in the channel region 107. For example, buffer layer 102 comprises GaAs and buffer layer 104 comprises In_xGa_{1- x}As, where x is between 0 and 1, and the III-V material in the channel region 107 comprises InP.

In an embodiment, the source region 113 or the drain region 123 may include a material similar to that in the channel region 107, and may also include an n-type dopant or a p-type dopant. As an example, the source region 113 or the drain region 123 may include In, P, Ga, or As, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium antimonide (InSb), indium gallium antimonide (InGaSb), indium gallium arsenide antimonide (In)_xGa_1-xAs_ySb_1-y) Indium gallium arsenide (In) phosphide_xGa_1-xAs_yP_1-y) Indium gallium phosphorus antimonide (In)_xGa_1-xP_ySb_1-y) Indium aluminum arsenic antimonide (In)_xAl_1-xAs_ySb_1-y) And phosphatingIndium aluminum arsenic (In)_xAl_1-xAs_yP_1-y) (where 0. ltoreq. x. ltoreq.1, 0. ltoreq. y. ltoreq.1), narrow bandgap III-V materials, or any combination thereof.

In an embodiment, the substrate 101 may be a silicon substrate, a glass substrate (e.g., soda lime glass or borosilicate glass), a metal substrate, a plastic substrate, a polyimide substrate, or other suitable substrate. The substrate 101 may comprise silicon, sapphire, SiC, GaN, AlN, SiO₂Or Cu. The substrate 101 may comprise a high resistivity p-type or n-type vicinal silicon material, germanium-on-silicon, gallium arsenide (GaAs), or silicon-on-insulator substrate. For example, the substrate 101 may be a silicon substrate having a (111), (100), or (110) crystal plane as a principal plane.

In an embodiment, gate dielectric layer 109 may comprise a high-k dielectric material. For example, gate dielectric layer 109 may comprise a material having a dielectric constant of at least about 10. In detail, the gate dielectric layer 109 may include Al₂O₃Although other materials may be used in other embodiments, such as La₂O₃、HfO₂、ZrO₂Or such as LaAl_xO_y、Hf_xZr_yO_zThe ternary complex of (1).

In an embodiment, the source electrode 115, the drain electrode 125, or the gate electrode 111 may be formed as a single layer or a stacked layer using one or more conductive films including a conductive material. For example, the source electrode 115, the drain electrode 125, or the gate electrode 111 may include a metal material, a conductive polymer, polysilicon, titanium silicide, phosphorus (n +) doped Si, boron doped SiGe, or an alloy of a semiconductor material and a metal. For example, the source electrode 115, the drain electrode 125, or the gate electrode 111 may include gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), tantalum (Ta), tungsten (W), nickel (Ni), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO. The source electrode 115, the drain electrode 125, or the gate electrode 111 may include tantalum nitride (TaN), titanium nitride (TiN), iridium-tantalum alloy (Ir-Ta), Indium TiN Oxide (ITO), the like, and/or combinations thereof.

Fig. 2 schematically illustrates an example III-V MOSFET 200 that includes a channel region 207 over a buffer layer 202 within a trench 210, in accordance with some embodiments. In an embodiment, group III-V MOSFET 200, channel region 207, buffer layer 202, and trench 210 may be similar to group III-V MOSFET 100, channel region 107, buffer layer 102, and trench 110, respectively, as shown in fig. 1.

In an embodiment, the III-V MOSFET family 200 includes a substrate 201. Isolation regions (e.g., isolation region 203 and isolation region 205) are located over substrate 201 to form trench 210 between isolation region 203 and isolation region 205. The buffer layer 202 is located over the substrate 201, in contact with the substrate 201, and within the trench 210. A second buffer layer, not shown, may be located within the trench 210, over the buffer layer 202 and in contact with the buffer layer 202. Channel region 207 is located above buffer layer 202 and comprises a III-V material. The second buffer layer may be removed below channel region 207 so that channel region 207 is vertically above buffer layer 102, but not vertically above the second buffer layer. A gate dielectric layer 209 is located over buffer layer 202 and completely surrounds channel region 207. The gate dielectric layer may comprise a high-k dielectric material. Gate electrode 211 is situated over buffer layer 202, does not overlap the second buffer layer, completely surrounds gate dielectric layer 209 and completely surrounds channel region 207.

In an embodiment, the channel region 207 may have a triangular shape and have a 111 crystal orientation. Group III-V MOSFETs fabricated using current technology may include group III-V materials having a 111 crystal orientation. The 111 crystal oriented channel region 207 may reduce stacking faults, increase state and charge density, improve surface roughness of the channel region 207 and gate dielectric uniformity.

Fig. 3 schematically illustrates an example process 300 for forming a III-V MOSFET including a channel region over a buffer layer within a trench, in accordance with some embodiments. Fig. 4(a) -4(f) schematically illustrate an example process 300 with more detail for forming a III-V MOSFET including a channel region over a buffer layer within a trench, according to some embodiments. In an embodiment, process 300 may be used to form a III-V MOSFET 100 as shown in FIG. 1 or a III-V MOSFET 200 as shown in FIG. 2.

At block 301, the process 300 may include forming isolation regions over a substrate and forming trenches between the isolation regions; forming a first buffer layer over the substrate, in contact with the substrate and within the trench; and forming a second buffer layer over the first buffer layer, in contact with the first buffer layer and within the trench. For example, as shown in fig. 4(a), process 300 may include forming isolation regions, such as isolation region 403 and isolation region 405, over substrate 401 and forming trench 410 between isolation region 403 and isolation region 405; forming a first buffer layer 402 over the substrate 401, in contact with the substrate 401 and within the trench 410; a second buffer layer 404 is formed over the first buffer layer 402, in contact with the first buffer layer 402 and within the trenches 410.

At block 303, the process 300 may include forming a channel region comprising a III-V material (e.g., InP) over a portion of the second buffer layer. For example, as shown in fig. 4(b) -4(d), the process 300 may include forming a recess of the second buffer layer 404, as shown in fig. 4(b), forming a channel region 407 over the remaining second buffer layer 404, as shown in fig. 4(c), and removing portions of the isolation regions 403 and 405 to expose the second buffer layer 404, as shown in fig. 4 (d). The channel region 407 may comprise InP or some other III-V material, for example, as shown for the channel region 107 in fig. 1.

At block 305, the process 300 may include removing a portion of the second buffer layer under the channel region while leaving the second buffer layer in regions that do not overlap the channel region; forming a high-k gate dielectric layer over the first buffer layer and completely surrounding the channel region; a gate electrode is formed over the first buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region. For example, as shown in fig. 4(e), process 300 may include removing a portion of second buffer layer 404 under channel region 407. The second buffer layer 404 may not be removed in a region not overlapping with the channel region 407. Process 300 may further include forming a high-k gate dielectric layer 409 over first buffer layer 402 and completely around channel region 407; and forming a gate electrode 411 over first buffer layer 402 that completely surrounds high-k gate dielectric layer 409 and completely surrounds channel region 407.

At block 307, the process 300 may include forming a source region over the second buffer layer, in contact with the second buffer layer and adjacent to the first end of the channel region; and forming a drain region over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region. For example, as shown in fig. 4(f), process 300 may include forming source region 413 over second buffer layer 404. Which is in contact with the second buffer layer 404 and adjacent to the first end of the channel region 407. The process 300 may also include forming a drain region over the second buffer layer 404, in contact with the second buffer layer 404 and adjacent to a second end of the channel region 407 opposite the first end of the channel region.

Additionally, process 300 may include forming a source electrode in contact with the source region and forming a drain electrode in contact with the drain region, forming a spacer between the source electrode and the gate electrode 411, and forming a spacer between the drain electrode and the gate electrode 411.

Fig. 5 illustrates an interposer 500 that includes one or more embodiments of the present disclosure. Interposer 500 is an intervening substrate used to bridge a first substrate 502 to a second substrate 504. The first substrate 502 may be, for example, a substrate supporting a group III-V MOSFET 100 as shown in fig. 1, a group III-V MOSFET 200 as shown in fig. 2, or a group III-V MOSFET formed by the process 300 shown in fig. 3 or 4. The second substrate 504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 500 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 500 may couple an integrated circuit die to a Ball Grid Array (BGA)506, which may then be coupled to a second substrate 504. In some embodiments, first substrate 502 and second substrate 504 are attached to opposite sides of interposer 500. In other embodiments, first substrate 502 and second substrate 504 are attached to the same side of interposer 500. Also in further embodiments, three or more substrates are interconnected by interposer 500.

Interposer 500 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 508 and vias 510, including but not limited to Through Silicon Vias (TSVs) 512. Interposer 500 may also include embedded devices 514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 500.

According to embodiments of the present disclosure, the apparatus or processes disclosed herein may be used to fabricate interposer 500.

FIG. 6 illustrates a computing device 600 according to one embodiment of the disclosure. Computing device 600 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternative embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC for a mobile device. Components in computing device 600 include, but are not limited to, an integrated circuit die 602 and at least one communication logic unit 608. In some embodiments, communication logic 608 is fabricated within integrated circuit die 602, while in other embodiments, communication logic 608 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to integrated circuit die 602. The integrated circuit die 602 may include a processor 604 and an on-die memory 606 (typically used as cache memory), which may be provided by technologies such as embedded dram (edram) or SRAM. For example, the processor 604 or on-die memory 606 or other control circuitry in the integrated circuit die 602 may include a group III-V MOSFET 100 as shown in FIG. 1, a group III-V MOSFET 200 as shown in FIG. 2, or a group III-V MOSFET formed by the process 300 shown in FIG. 3 or FIG. 4.

In an embodiment, computing device 600 may include a display or touch screen display 624, and a touch screen display controller 626. The display or touch screen display 624 may include an FPD, an AMOLED display, a TFT LCD, a micro light emitting diode (μ LED) display, or the like.

Computing device 600 may include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 610 (e.g., Dynamic Random Access Memory (DRAM)), non-volatile memory 612 (e.g., ROM or flash memory), a graphics processing unit 614(GPU), a Digital Signal Processor (DSP)616, an encryption processor 642 (e.g., a special purpose processor that executes encryption algorithms within hardware), a chipset 620, at least one antenna 622 (two or more antennas may be used in some implementations), a battery 630 or other power source, power electronics 631, a voltage regulator (not shown), a Global Positioning System (GPS) device 628, a compass, a motion co-processor or sensor 632 (which may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 634, a resonator 635, a camera 636, a user input device 638 (e.g., a keyboard, mouse, stylus, and touchpad), And a mass storage device 640 (e.g., a hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.). In embodiments, the various components may include a III-V MOSFET 100 as shown in FIG. 1, a III-V MOSFET 200 as shown in FIG. 2, or a III-V MOSFET formed by the process 300 shown in FIG. 3 or FIG. 4.

Computing device 600 may contain other transport, telecommunications, or radio functions not described herein. In some implementations, the computing device 600 includes a radio for communicating over a distance by modulating and radiating electromagnetic waves in the air or space. In further implementations, the computing device 600 includes a transmitter and receiver (or transceiver) for communicating over a distance by modulating and radiating electromagnetic waves in the air or space.

The communication logic 608 enables wireless communication for data transfer to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication logic 608 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher generation. Computing device 600 may include a plurality of communication logic units 608. For example, a first communication logic 608 may be dedicated to short-range wireless communications, such as Wi-Fi, NFC, and Bluetooth, while a second communication logic 608 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

The processor 604 of the computing device 600 includes one or more devices, such as transistors. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication logic 608 may also include one or more devices, such as transistors.

In further embodiments, another component housed within the computing device 600 may contain one or more devices, such as power electronics 631, formed in accordance with embodiments of the present disclosure, for example, a group III-V MOSFET 100 as shown in fig. 1, a group III-V MOSFET 200 as shown in fig. 2, or a group III-V MOSFET formed by the process 300 shown in fig. 3 or 4.

In various embodiments, computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a non-smartphone, a tablet/laptop hybrid, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital camcorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Some non-limiting examples are provided below.

Example 1 may include a semiconductor device, comprising: isolation regions over the substrate to form trenches between the isolation regions; a first buffer layer over the substrate, in contact with the substrate and within the trench; the second buffer layer is positioned above the first buffer layer and is in contact with the first buffer layer; a channel region over the first buffer layer, over a portion of the second buffer layer under the source or drain region, and not vertically over a portion of the second buffer layer, wherein the channel region comprises a III-V material; a high-k gate dielectric layer located over the first buffer layer and completely surrounding the channel region; a gate electrode over the first buffer layer without overlapping the second buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region, a source region over the second buffer layer in contact with the second buffer layer and adjacent to the first end of the channel region; and a drain region over the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel region opposite the first end of the channel region.

Example 2 may include the semiconductor device of example 1 and/or some other example herein, further comprising: a source electrode coupled to the source region; a drain electrode coupled to the drain region.

Example 3 may include the semiconductor device of example 1 and/or some other example herein, wherein the second buffer layer is coplanar with a surface of the isolation region, and the channel region, the source region, and the drain region are over the surface of the isolation region.

Example 4 may include the semiconductor device of example 1 and/or some other example herein, wherein the surface of the substrate in contact with the first buffer layer is a non-planar surface.

Example 5 may include the semiconductor device of example 1 and/or some other example herein, wherein the channel region has a shape selected from the group consisting of a rectangular shape, a square shape, an oval shape, and a circular shape, and a width of the trench is substantially equal to a width of the channel region.

Example 6 may include the semiconductor device of example 1 and/or some other example herein, wherein the channel region comprises a channel selected from the group consisting of a nanowire channel, a nanoribbon channel, and a full-halo gate channel.

Example 7 may include the semiconductor device of example 1 and/or some other example herein, wherein the channel region has a triangular shape.

Example 8 may include the semiconductor device of example 1 and/or some other example herein, wherein the channel region has a 111 crystal orientation.

Example 9 may include the semiconductor device of example 1 and/or some other example herein, wherein the III-V material of the channel region comprises a material selected from the group consisting of indium (In), phosphorus (P), gallium (Ga), and arsenic (As).

Example 10 may include the semiconductor device of example 1 and/or some other example herein, wherein the source region or the drain region includes an n-type dopant.

Example 11 may include the semiconductor device of example 1 and/or some other example herein, wherein the source region or the drain region comprises a material selected from the group consisting of In, P, Ga, or As, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium antimonide (InSb), indium gallium antimonide (InGaSb), indium gallium arsenide antimonide (In), and gallium arsenide antimonide (In)_xGa_1-xAs_ySb_1-y) Indium gallium arsenide (In) phosphide_xGa_1-xAs_yP_1-y) Indium gallium phosphorus antimonide (In)_xGa_1-xP_ySb_1-y) Indium aluminum arsenic antimonide (In)_xAl_1-xAs_ySb_1-y) Indium aluminum arsenic phosphide (In)_xAl_1-xAs_yP_1-y) (where 0. ltoreq. x. ltoreq.1, 0. ltoreq. y. ltoreq.1), narrow bandgap group III-V materials, or any combination thereof.

Example 12 may include the semiconductor device of example 1 and/or some other example herein, wherein the substrate comprises a material selected from the group consisting of a high resistivity p-type or n-type vicinal silicon material, germanium-on-silicon, gallium arsenide (GaAs), and a silicon-on-insulator substrate.

Example 13 may include the semiconductor device of example 1 and/or some other example herein, wherein the first buffer layer comprises a material selected from gallium arsenide (GaAs), polycrystalline GaAs, InP, AlAs, GaP, AlAsSb, InAlAs, or In_xGa_1-xAs, wherein x is between 0 and 1.

Example 14 may include the semiconductor device of example 1 and/or some other example herein, wherein the second buffer layer comprises a material having a different etch selectivity than the III-V material in the channel region.

Example 15 may include the semiconductor device of example 1 and/or some other example herein, wherein the first buffer layer comprises GaAs and the second buffer layer comprises In_xGa_1-xAs, where x is between 0 and 1, and the III-V material in the channel region comprises InP.

Example 16 may include a method for forming a semiconductor device, the method comprising: forming isolation regions over the substrate and forming trenches between the isolation regions; forming a first buffer layer over the substrate, in contact with the substrate and within the trench; forming a second buffer layer on the first buffer layer, wherein the second buffer layer is in contact with the first buffer layer and is positioned in the groove; forming a channel region comprising InP over a portion of the second buffer layer; removing a portion of the second buffer layer under the channel region while leaving the second buffer layer in a region not overlapping the channel region; forming a high-k gate dielectric layer over the first buffer layer and completely surrounding the channel region; forming a gate electrode over the first buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region; forming a source region over the second buffer layer, in contact with the second buffer layer and adjacent to the first end of the channel region; and forming a drain region over the second buffer layer, in contact with the second buffer layer and adjacent to a second end of the channel region opposite the first end of the channel region.

Example 17 may include the method of example 16 and/or some other example herein, wherein removing the second buffer layer under the channel region includes removing the second buffer layer under the channel region by selective etching.

Example 18 may include the method of example 16 and/or some other example herein, wherein the second buffer layer is coplanar with a surface of the isolation region, and the channel region, the source region, and the drain region are over the surface of the isolation region.

Example 19 may include the method of example 16 and/or some other example herein, wherein the channel region has a triangular shape and has a 111 crystal orientation.

Example 20 may include the method of example 16 and/or some other example herein, wherein the first buffer layer comprises a material selected from gallium arsenide (GaAs), polycrystalline GaAs, InP, AlAs, GaP, AlAsSb, InAlAs, or In_xGa_1-xAs, wherein x is between 0 and 1.

Example 21 may include the method of example 16 and/or some other example herein, wherein the first buffer layer comprises GaAs and the second buffer layer comprises In_xGa_1-xAs, where x is between 0 and 1.

Example 22 may include a computing device comprising: a processor; and a memory device coupled to the processor, wherein the memory device or the processor comprises a transistor comprising: isolation regions over the substrate to form trenches between the isolation regions; a first buffer layer over the substrate, in contact with the substrate and within the trench; the second buffer layer is positioned above the first buffer layer and is in contact with the first buffer layer; a channel region over the first buffer layer, over a portion of the second buffer layer below the source or drain region, and not vertically over a portion of the second buffer layer, wherein the channel region comprises a III-V material; a high-k gate dielectric layer over the first buffer layer and completely surrounding the channel region; a gate electrode over the first buffer layer without overlapping the second buffer layer, completely surrounding the high-k gate dielectric layer and completely surrounding the channel region, a source region over the second buffer layer in contact with the second buffer layer and adjacent to the first end of the channel region; and a drain region over the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel region opposite the first end of the channel region.

Example 23 may include the computing device of example 22 and/or some other example herein, wherein the surface of the substrate in contact with the first buffer layer is a non-planar surface.

Example 24 may include the computing device of example 22 and/or some other example herein, wherein the first buffer layer comprises GaAs and the second buffer layer comprises In_xGa_1-xAs, where x is between 0 and 1, and the III-V material in the channel region comprises InP.

Example 25 may include the computing device of example 22 and/or some other example herein, wherein the computing device comprises a device selected from the group consisting of a wearable device or a mobile computing device, the wearable device or the mobile computing device comprising one or more of an antenna coupled with a processor, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, a geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.

Various embodiments may include any suitable combination of the above-described embodiments, including alternative (or) embodiments to the embodiments described above in conjunction (and) (e.g., "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, result in the operations of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for performing various operations of the above-described embodiments.

The above description of illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to limit embodiments of the disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications can be made to the embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.