阅读说明：本技术 半导体器件和方法 (Semiconductor device and method ) 是由 蔡济印 陈俊仁 郑培仁 李启弘 陈科维 杨育佳 于 2019-06-26 设计创作，主要内容包括：本公开涉及半导体器件和方法。在一个实施例中,一种器件包括：衬底；第一半导体区域,从衬底延伸,第一半导体区域包括硅；第二半导体区域,在第一半导体区域上,第二半导体区域包括硅锗,第二半导体区域的边缘部分具有第一锗浓度,第二半导体区域的中心部分具有小于第一锗浓度的第二锗浓度；栅极堆叠,在第二半导体区域上；以及源极和漏极区域,在第二半导体区域中,源极和漏极区域与栅极堆叠相邻。(The present disclosure relates to semiconductor devices and methods. In one embodiment, a device comprises: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region comprising silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region comprising silicon germanium, an edge portion of the second semiconductor region having a first germanium concentration, a central portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions adjacent to the gate stack.)

1. A semiconductor device, comprising:

a substrate;

a first semiconductor region extending from the substrate, the first semiconductor region comprising silicon;

a second semiconductor region located on the first semiconductor region, the second semiconductor region comprising silicon germanium, an edge portion of the second semiconductor region having a first germanium concentration, a central portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration;

a gate stack on the second semiconductor region; and

source and drain regions in the second semiconductor region, the source and drain regions adjacent to the gate stack.

2. The device of claim 1, wherein an edge portion of the first semiconductor region has a third germanium concentration and a central portion of the first semiconductor region has a fourth germanium concentration that is less than the third germanium concentration.

3. The device of claim 1, wherein the gate stack comprises:

a gate dielectric extending along the edge portion of the second semiconductor region and along a top surface of the second semiconductor region; and

a gate electrode on the gate dielectric.

4. The device of claim 1, wherein the first semiconductor region has a first width, the second semiconductor region has a second width, and the first width is greater than the second width.

5. The device of claim 4, wherein a first portion of the second semiconductor region has the first width and a second portion of the second semiconductor region has the second width.

6. The device of claim 1, further comprising:

an isolation region adjacent to the first and second semiconductor regions, portions of the first and second semiconductor regions in contact with the isolation region being damaged.

7. A method for forming a semiconductor device, comprising:

providing a substrate comprising silicon;

growing a semiconductor layer on the substrate, the semiconductor layer comprising silicon germanium;

etching trenches in the semiconductor layer and the substrate to form fins from portions of the semiconductor layer and the substrate between the trenches;

oxidizing the fin to form an oxide layer along sides of the fin, a germanium concentration of the fin at the sides of the fin increasing after oxidation;

removing the oxide layer from the sides of the fin; and

a metal gate stack is formed along a top surface and the side portions of the fin.

8. The method of claim 7, wherein the fin comprises a first portion and a second portion, the first portion comprising a portion of the substrate between the trenches, the second portion comprising a portion of the semiconductor layer between the trenches, and wherein oxidizing the fin reduces a width of the second portion of the fin.

9. The method of claim 8, wherein etching trenches in the semiconductor layer and the substrate damages sides of the first and second portions of the fin, and wherein the sides of the second portion of the fin are repaired after oxidation.

10. A method for forming a semiconductor device, comprising:

growing a semiconductor layer on a substrate, the substrate comprising silicon, the semiconductor layer comprising silicon germanium, the semiconductor layer having a uniform germanium concentration after the growing;

etching a trench in the semiconductor layer and the substrate;

oxidizing the semiconductor layer and sidewalls of the substrate exposed by the trench to form an oxide layer in the trench, the semiconductor layer having a non-uniform germanium concentration after the oxidizing, the germanium concentration at the sidewalls of the semiconductor layer after the oxidizing being greater than the germanium concentration at the sidewalls of the semiconductor layer before the oxidizing;

removing the oxide layer; and

an insulating material is deposited in the trench.

Technical Field

The present disclosure relates generally to semiconductor devices and methods.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited over a semiconductor substrate, and photolithography is used to pattern the various material layers to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a semiconductor device including: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region comprising silicon; a second semiconductor region located on the first semiconductor region, the second semiconductor region comprising silicon germanium, an edge portion of the second semiconductor region having a first germanium concentration, a central portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions adjacent to the gate stack.

According to another embodiment of the present disclosure, there is provided a method for forming a semiconductor device, including: providing a substrate comprising silicon; growing a semiconductor layer on the substrate, the semiconductor layer comprising silicon germanium; etching trenches in the semiconductor layer and the substrate to form fins from portions of the semiconductor layer and the substrate between the trenches; oxidizing the fin to form an oxide layer along sides of the fin, a germanium concentration of the fin at the sides of the fin increasing after oxidation; removing the oxide layer from the sides of the fin; and forming a metal gate stack along a top surface and the side portions of the fin.

According to still another embodiment of the present disclosure, there is provided a method for forming a semiconductor device, including: growing a semiconductor layer on a substrate, the substrate comprising silicon, the semiconductor layer comprising silicon germanium, the semiconductor layer having a uniform germanium concentration after the growing; etching a trench in the semiconductor layer and the substrate; oxidizing the semiconductor layer and sidewalls of the substrate exposed by the trench to form an oxide layer in the trench, the semiconductor layer having a non-uniform germanium concentration after the oxidizing, the germanium concentration at the sidewalls of the semiconductor layer after the oxidizing being greater than the germanium concentration at the sidewalls of the semiconductor layer before the oxidizing; removing the oxide layer; and depositing an insulating material in the trench.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET) in a three-dimensional view in accordance with some embodiments.

Fig. 2-20B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some embodiments.

Fig. 21-22 are cross-sectional views of intermediate stages of fabrication of a FinFET according to some other embodiments.

Fig. 23A-24B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some other embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, a substrate of a first semiconductor material (e.g., silicon) is provided, and a layer of a second semiconductor material (e.g., silicon germanium) is formed on the substrate. The second semiconductor material may have a low germanium concentration. The trench is etched to form a fin from the first and second semiconductor materials. An oxidation process is performed to form an oxide layer on the sidewalls of the fin. During oxidation, the germanium of the second semiconductor material is concentrated along the sidewalls of the fin. The oxide layer is then removed. By concentrating the germanium along the sidewalls of the fin, the germanium concentration in the channel region of the fin may be increased. Since the fins are initially formed with a low germanium concentration, they have a lower amount of compressive strain and therefore may reduce deformation of the fins during the trench etch.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments. The FinFET includes a fin 60 located on the substrate 50. Shallow Trench Isolation (STI) regions 72 are formed on substrate 50, and fins 60 protrude between and above adjacent STI regions 72. A gate dielectric layer 104 is along the sidewalls of fin 60 and over the top surface of fin 60, and a gate electrode 106 is located over gate dielectric layer 104. Source/drain regions 96 are disposed on an opposite side of fin 60 relative to gate dielectric layer 104 and gate electrode 106.

Fig. 1 also shows a reference cross section used in the following figures. Cross section a-a spans the channel of the FinFET, the gate dielectric layer 104, and the gate electrode 106. Cross-section B-B is perpendicular to cross-section a-a and along the longitudinal axis of fin 60, and in the direction of current flow between, for example, source/drain regions 96. Cross section C/D-C/D is parallel to cross section a-a and extends through source/drain region 96 of the FinFET. For clarity, the subsequent figures refer to these reference cross sections.

Some embodiments discussed herein are discussed in the context of finfets formed using a gate-last process. In other embodiments, a gate first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

Fig. 2-13 are cross-sectional views of intermediate stages of fabrication of a FinFET according to some embodiments. Fig. 2-13 are shown along the reference cross-section a-a shown in fig. 1, except for a plurality of fins/finfets.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, substrate 50 comprises silicon, for example, substrate 50 is a silicon substrate, such as a wafer. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.

One area of the substrate 50 is shown. The regions shown may be used to form n-type devices, e.g., NMOS transistors, such as n-type finfets, or p-type devices, e.g., PMOS transistors, such as p-type finfets. Some embodiments discussed herein are discussed in the context of forming a p-type device in the illustrated region. N-type devices may be formed in other areas of substrate 50. During the process of forming the p-type device, the regions used to form the n-type device may be covered by a mask, such as a photoresist.

In some embodiments, the substrate 50 is doped to have an appropriate doped region (sometimes referred to as a well region). In embodiments in which a p-type device is formed in the illustrated regions, n-type doped regions may be formed in the substrate 50. In some embodiments, the n-type doped region may be formed by implanting an n-type impurity in a region of the substrate 50. In some embodiments, the substrate 50 may be pre-doped with n-type impurities. The n-type impurity may be phosphorus, arsenic, or the like, and may be formed in the region to have a value of 10 or less¹⁸cm^-3E.g. from about 10¹⁷cm^-3To about 10¹⁸cm^-3. In embodiments in which an n-type device is formed in the illustrated regions, p-type doped regions may be formed in the substrate 50. In some embodiments, the p-type doped region may be formed by implanting a p-type impurity in a region of the substrate 50. In some embodiments, the substrate 50 may be pre-doped with a p-type impurity. The p-type impurity may be boron or BF₂Etc., and may be formed to have 10 or less in the region¹⁸cm^-3E.g. from about 10¹⁷cm^-3To about 10¹⁸cm^-3。。

In fig. 3, a semiconductor layer 52 is formed on a substrate 50. In some embodiments, semiconductor layer 52 is epitaxially grown on substrate 50. In some embodimentsSemiconductor layer 52 is a bulk semiconductor, e.g., a wafer, and is bonded to substrate 50 by, e.g., wafer bonding. In embodiments in which a p-type device is formed, semiconductor layer 52 is a semiconductor material including germanium, for example, silicon germanium (Si)_xGe_1-xWhere x may be in the range of 0 to 1). Semiconductor layer 52 may be formed to have a low germanium concentration, for example, a concentration from about 0 to about 50%, which may provide sufficient strain to increase mobility without creating dislocation defects when the thickness of semiconductor layer 52 reaches a desired channel height. It is understood that the target low germanium concentration may vary based on the fin design and desired parameters of the final device. Silicon and silicon germanium have different lattice constants. Thus, the semiconductor layer 52 and the substrate 50 have lattice constants that are mismatched. The lattice constant mismatch is dependent on the germanium concentration in semiconductor layer 52, with higher germanium concentrations resulting in a larger lattice constant mismatch. The lattice constant mismatch induces a compressive strain in semiconductor layer 52, which may increase carrier mobility of semiconductor layer 52, which may improve channel region mobility of subsequently formed p-type devices. Because of the low germanium concentration of semiconductor layer 52, the lattice constant mismatch and the amount of compressive strain is also low.

In some embodiments, the semiconductor layer 52 is in-situ doped during growth to have an appropriate doped region (sometimes referred to as a well region). The doped regions of semiconductor layer 52 may have the same doping type as the underlying doped regions of substrate 50. The doped regions of semiconductor layer 52 may have the same doping concentration as the underlying doped regions of substrate 50, or may have a different doping concentration.

In fig. 4, a mask 54 is formed on the semiconductor layer 52. The mask 54 may be formed by forming a mask layer on the semiconductor layer 52 and patterning the mask layer. The mask layer may be formed of a material including a metal, for example, titanium nitride, titanium, tantalum nitride, tantalum, or the like, and may be formed by Physical Vapor Deposition (PVD), radio frequency PVD (rfpvd), Atomic Layer Deposition (ALD), or the like. The mask layer may also be formed of a non-metallic material, such as SiN. After formation, the mask layer is patterned using an acceptable etch process. The etching process may be any acceptable etching process, for example, wet etching, dry etching, reactive ion etching, neutral beam etching, and the like. The remaining portions of the mask layer form a mask 54.

In fig. 5, trenches 56 are formed in semiconductor layer 52 corresponding to the pattern of mask 54. The trench 56 may be formed by one or more etching processes using the mask 54 as an etch mask. The etching process (es) may include wet etching, dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), combinations thereof, and the like, and may be anisotropic. The trench 56 may extend partially into the semiconductor layer 52 or may extend through the semiconductor layer 52 and into the substrate 50. The portion of semiconductor layer 52 (and optionally substrate 50) remaining between trenches 56 is referred to as fin 60. The fin 60 includes a first portion 60A having a portion of the substrate 50 and a second portion 60B having a portion of the semiconductor layer 52. Fin 60 is initially formed to a width W₁. In some embodiments, the width W₁From about 8nm to about 20 nm. It is to be understood that the width W₁May vary based on the layout or design of fin 60.

As a result of the etching process, the sidewalls of fin 60 exposed by trench 56 may be damaged. Damage may include atomic shifts, vacancies, etc., which are represented by the "X" symbol. In some embodiments, the etching process omits a cleaning process (e.g., Cl ashing or wet cleaning) for repairing the damage. In some embodiments, a cleaning process may be performed.

Fin 60 is a semiconductor strip. When semiconductor layer 52 is etched to form second portion 60B of fin 60, the sidewalls of fin 60 are exposed and free of lateral constraints, e.g., exposed to free space and not surrounded or supported by other structures or materials. As described above, the semiconductor layer 52 is strained. Since the sidewalls of fin 60 are unconstrained during the etch, the strain in semiconductor layer 52 is relieved during the etch. When the strain is relieved, the shape of the semiconductor material may change, deforming fins 60 such that they do not have the desired fin shape. In particular, fin 60 may deform such that the semiconductor strips are not straight strips in top view. The deformed fins 60 may bend or bow as they extend along the substrate 50. The amount of deformation of fin 60 depends on the amount of strain released from semiconductor layer 52. The risk of fin deformation may be exacerbated when fin 60 is formed to have a narrower width or a higher degree. Excessive deformation may reduce the yield of fin 60 and may also reduce the carrier mobility of fin 60. Since the semiconductor layer 52 is formed to have a low germanium concentration, the amount of strain released is low. By forming the semiconductor layer 52 with a low germanium concentration, the carrier mobility obtained by avoiding fin deformation may be greater than the carrier mobility lost by reducing the germanium concentration.

In fig. 6, an oxidation process 62 is performed to form an oxide layer 64. The oxide layer 64 extends along the exposed sidewalls of the fin 60, the exposed sidewalls of the mask 54, and the top surfaces of the mask 54 and the substrate 50. The oxidation process 62 may be a Rapid Thermal Oxidation (RTO) process, a chemical oxidation process, a raw stream generation (ISSG) process, an enhanced raw stream generation (EISSG) process, or the like. For example, the oxidation process 62 may include a Rapid Thermal Anneal (RTA) performed in an oxygen-containing ambient. Water vapor, molecular oxygen, ozone, or other sources of oxygen may be introduced into the environment to increase the oxygen content of the environment. The oxidation temperature may contribute to the thickness of oxide layer 64; the higher temperature of the oxidation process 62 may result in a thicker oxide layer 64. In some embodiments, the oxidation process 62 is performed at a temperature from about 600 ℃ to about 1200 ℃. The oxidation time span may also contribute to the thickness of oxide layer 64; the longer oxidation time span of the oxidation process 62 may produce a thicker oxide layer 64. In some embodiments, the oxidation process 62 is performed for a time span from a few seconds to a few hours, for example, from about 5 seconds to about 12 hours. It is understood that the duration of oxidation may vary based on the oxidation conditions and environment. Ambient pressure may also contribute to the thickness of oxide layer 64; the higher pressure level of the oxidation process 62 may result in a thicker oxide layer 64. In some embodiments, the oxidation process 62 is performed at a pressure from about 0.1Torr to about 20 atm.

Fig. 7 is a detailed view of region 10 in fig. 6, showing additional features of fin 60. As shown, oxidizing fin 60 consumes some of the semiconductor material of fin 60. The damaged sidewalls of fin 60 may be consumed by oxidation process 62. Thus, the remaining sidewalls of fin 60 (nowCovered by oxide layer 64) may not be damaged, or at least may be less damaged. The oxidation process 62 can be said to repair the damaged sidewalls of the fin 60. The oxide layer 64 will then be removed, as will be discussed further below. The portion of fin 60 remaining after oxide layer 64 is removed is thinner than the width of fin 60 prior to oxidation process 62. In this way, the final width of fin 60 may be controlled by varying the parameters of oxidation process 62. Furthermore, since silicon germanium has a higher oxidation rate than silicon, the second portion 60B of the fin 60 oxidizes more than the first portion 60A of the fin 60. Thus, after oxidation, second portion 60B of fin 60 has a second width W₂Second width W₂Is less than third width W of first portion 60A of fin 60₃. Final width W₂And W₃Are all smaller than the initial width W of fin 60₁. In some embodiments, the width W₂Less than about 20nm, and a width W₃From about 6nm to about 20 nm.

Further, a germanium-rich layer 66 is formed in the second portion 60B of the fin 60. The germanium rich layer 66 is formed by the oxidation process 62. Silicon and oxygen have a greater chemical affinity than germanium and oxygen. Thus, oxide layer 64 is primarily silicon oxide. Furthermore, germanium is not soluble in silicon oxide, and the germanium of second portion 60B of fin 60 is mostly expelled from germanium-rich layer 66. Thus, as sidewall portions of fin 60 are consumed to form oxide layer 64, germanium in these sidewall portions is driven away from oxide layer 64 toward the center of fin 60. Some of the germanium may also be driven down such that the germanium-rich layer 66 also extends into the first portion 60A of the fin 60. The resulting germanium-rich layer 66 is located in the sidewalls of the first portion 60A and the second portion 60B of the fin 60. As such, the edge regions of the first and second portions 60A, 60B of the fin 60 have a higher germanium concentration than the central regions of the first and second portions 60A, 60B of the fin 60. The germanium-rich layer 66 may have the same or different concentrations in the first and second portions 60A, 60B of the fin 60. In some embodiments, the germanium-rich layer 66 in the first portion 60A of the fin 60 has a lower germanium concentration than the germanium-rich layer 66 in the second portion 60B of the fin 60. The germanium-rich layer 66 in the second portion 60B of the fin 60 may have a germanium concentration of up to about 100%. The maximum germanium concentration that may be achieved before fin deformation is determined by the desired dimensions of fin 60, and embodiments may allow the concentration of germanium-rich layer 66 to approach this maximum level.

The width of the germanium-rich layer 66 depends on the width of the oxide layer 64. By varying the parameters of oxidation process 62, the width of germanium-rich layer 66 may vary from a few monolayers to substantially the entire width of fin 60. The germanium-rich layer 66 in the first portion 60A of the fin 60 is formed to a thickness T₁And the germanium-rich layer 66 in the second portion 60B of the fin 60 is formed to a thickness T₂Thickness T₂Less than thickness T₁. In some embodiments, the thickness T₁Up to a third width W₃About half of, and a thickness T₁Up to a second width W₂About half of. The germanium diffusion may be isotropic, so the germanium-rich layer 66 in the first portion 60A also extends a distance D toward the substrate₁. In some embodiments, distance D₁Up to a third width W₃Half of that.

Although semiconductor layer 52 (see fig. 6) is formed to have a low germanium concentration, forming germanium-rich layer 66 allows for an increase in the germanium concentration of fin 60. Forming fin 60 with a low initial germanium concentration may help avoid deformation of fin 60 during formation. Increasing the germanium concentration of fin 60 after formation may allow for increased carrier mobility of fin 60 without the disadvantage of increased fin deformation. Furthermore, because germanium-rich layers 66 are near the sidewalls of fin 60, they may be near the gates of subsequently formed p-type devices, allowing for increased channel region mobility of subsequently formed p-type devices. The final strain of fin 60 may also be higher than the initial strain of fin 60.

In fig. 8, oxide layer 64 is removed. The removal may be by dry etching or wet etching. May be used to include CHF₃、CF₄Etc., and may be wet etched with an etchant including hot or cold dHF acid, etc. The etch may be isotropic or anisotropic depending on whether the oxide layer 64 should be completely removed. In some embodiments, some of oxide layer 64 remains and may be removed after subsequent processing. In the embodiment shown, the oxidation is removed after the germanium-rich layer 66 is formed and before further processing is performedLayer 64. In some embodiments, other processes may be performed after forming the germanium-rich layer 66, and the oxide layer 64 may not be removed until after subsequent processes. The oxide layer 64 may serve as a protective layer during subsequent processing.

In fig. 9, an insulating material 70 is formed over substrate 50 and between adjacent fins 60. The insulating material 70 may be an oxide (e.g., silicon oxide), nitride, or the like, or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), Flowable Chemical Vapor Deposition (FCVD) (e.g., Chemical Vapor Deposition (CVD) -based material in a remote plasma system deposited and post-cured to convert it to another material, e.g., oxide), or the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 70 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, insulative material 70 is formed such that an excess portion of insulative material 70 covers fin 60.

In fig. 10, a planarization process is applied to insulating material 70. In some embodiments, the planarization process includes a Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like. The planarization process exposes the fins 60, removing the mask 54. The top surfaces of fin 60 and insulating material 70 are horizontal after the planarization process.

In fig. 11, insulating material 70 is recessed to form STI regions 72. Insulating material 70 is recessed such that second portion 60B of fin 60 protrudes from between adjacent STI regions 72. Further, the top surface of STI region 72 may have a flat surface, a convex surface, a concave surface (e.g., a depression), or a combination thereof, as shown. The top surface of STI region 72 may be formed flat, convex, and/or concave by appropriate etching. STI regions 72 may be recessed using an acceptable etch process, for example, an etch process that is selective to the material of insulating material 70. For example, chemical oxide removal using a hydrogen source (e.g., ammonia) with a fluorine source (e.g., nitrogen trifluoride), or chemical oxide removal using dilute hydrofluoric acid (dHF) acid may be used.

In fig. 12, a dummy dielectric layer 74 is formed over fin 60. Dummy dielectric layer 74 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 76 is formed over dummy dielectric layer 74 and a mask layer 78 is formed over dummy gate layer 76. Dummy gate layer 76 may be deposited over dummy dielectric layer 74 and then planarized, for example by CMP. The dummy gate layer 76 may be a conductive material and may be selected from the group consisting of polysilicon (polysilicon), poly-silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. Dummy gate layer 76 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. Dummy gate layer 76 may be made of other materials that have a high etch selectivity from the etching of the isolation regions. A mask layer 78 may be deposited over dummy gate layer 76.

Fig. 13 is a detailed view of region 12 of fig. 12 showing additional features. It can be seen that the second portion 60B of the fin 60 protrudes from between adjacent STI regions 72, and the first portion 60A of the fin 60 remains buried. Furthermore, the interface of the first portion 60A and the second portion 60B is located below the top surface of the STI region 72.

Fig. 14A-20B are cross-sectional views of an intermediate stage of further fabrication of a FinFET according to some embodiments. The figure ending with the "a" label is shown along the reference cross section a-a shown in fig. 1, except for a plurality of fins/finfets. The figure ending with the "B" label is shown along the reference cross section B-B shown in fig. 1, except for a plurality of fins/finfets. The figure ending with the "C" or "D" label is shown along the reference cross section C/D-C/D shown in fig. 1, except for a plurality of fins/finfets.

In fig. 14A and 14B, mask layer 78 is patterned using acceptable photolithography and etching techniques to form mask 80. The pattern of mask 80 may then be transferred to dummy gate layer 76 and dummy dielectric layer 74 by acceptable etching techniques to form dummy gate 82 and dummy gate dielectric layer 84, respectively. Dummy gate 82 and dummy gate dielectric layer 84 cover the respective channel regions of fin 60. The pattern of the mask 80 may be used to physically separate each dummy gate 82 from adjacent dummy gates. The dummy gate 82 may also have a length direction substantially perpendicular to a length direction of the corresponding epitaxial fin.

In fig. 15A, 15B, 15C, and 15D, gate seal spacers 90 may be formed on exposed surfaces of dummy gate 82 and/or fin 60. The gate seal spacer 90 may be formed by an anisotropic etch after thermal oxidation or deposition. In some embodiments, the gate seal spacers may be formed of nitride (e.g., silicon nitride), silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. The gate seal spacers 90 seal the sidewalls of the subsequently formed gate stack and may serve as additional gate spacers.

In addition, an implant for lightly doping the source/drain (LDD) region 92 may be performed. An appropriate type (e.g., n-type or p-type) of impurity may be implanted into the exposed fin 60. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source/drain regions may have a thickness of from about 10¹⁵cm^-3To about 10¹⁶cm^-3The impurity concentration of (1). Annealing may be used to activate the implanted dopants.

In addition, gate spacers 94 are formed on the gate seal spacers 90 along the sidewalls of the dummy gate 82 and over the LDD regions 92. The gate spacers 94 may be formed by conformally depositing a material and then anisotropically etching the material. The material of the gate spacer 94 may be silicon nitride, SiCN, combinations thereof, or the like. The etch may be selective to the material of the gate spacers 94 so that the LDD regions 92 are not etched during the formation of the gate spacers 94.

In addition, epitaxial source/drain regions 96 are formed in fin 60. Epitaxial source/drain regions 96 are formed in fin 60 such that each dummy gate 82 is disposed between a respective adjacent pair of epitaxial source/drain regions 96. In some embodiments, epitaxial source/drain regions 96 may extend through LDD regions 92. In some embodiments, the gate seal spacers 90 and gate spacers 94 are used to separate the epitaxial source/drain regions 96 from the dummy gate 82 by an appropriate lateral distance so that the epitaxial source/drain regions 96 do not short the gates of subsequently formed resulting finfets.

Epitaxial source/drain regions 96 may be formed by etching source/drain regions of fin 60 to form recesses in fin 60. Epitaxial source/drain regions 96 are then epitaxially grown in the recesses. The epitaxial source/drain regions 96 may comprise any acceptable material, such as a material suitable for p-type or n-type finfets. For example, in embodiments where a p-type device is formed, epitaxial source/drain regions 96 may include SiGe, SiGeB, Ge, GeSn, and the like. Epitaxial source/drain regions 96 may also have surfaces that are raised from respective surfaces of fin 60, and may have facets.

The epitaxial source/drain regions 96 are doped in-situ during growth to form source/drain regions. The epitaxial source/drain regions 96 have the same doping type as the corresponding LDD regions 92 and may be doped with the same or different dopants. The epitaxial source/drain regions 96 may have a thickness between about 10 a¹⁹cm^-3And about 10²¹cm^-3Impurity concentration in between. The n-type and/or p-type impurities of the source/drain regions may be any of the impurities discussed previously. Because the epitaxial source/drain regions 96 are doped in-situ during growth, they are not doped by implantation. However, the doping profile and concentration of LDD regions 92 produced according to some embodiments may be similar to that which would be produced if epitaxial source/drain regions 96 were doped by implantation. Improving the doping profile and concentration of LDD regions 92 may improve the performance and reliability of the resulting semiconductor device.

As a result of the epitaxial process used to form epitaxial source/drain regions 96, the upper surfaces of the epitaxial source/drain regions have facets that extend laterally outward beyond the sidewalls of fin 60. In some embodiments, these facets cause adjacent epitaxial source/drain regions 96 of the same FinFET to merge, as shown in the embodiment of fig. 15C. In other embodiments, the adjacent epitaxial source/drain regions 96 remain separated after the epitaxial process is completed, as shown in the embodiment of fig. 15D.

In fig. 16A and 16B, an interlayer dielectric (ILD)100 is deposited over fin 60. The ILD100 may be formed of a dielectric material and may be deposited by any suitable method, for example, CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL) is disposed between the ILD100 and the epitaxial source/drain regions 96, gate spacers 94, gate seal spacers 90, and mask 80.

In fig. 17A and 17B, a planarization process (e.g., CMP) may be performed to make the top surface of the ILD100 flush with the top surfaces of the dummy gate 82 and the gate seal spacer 90. The planarization process may also remove the mask 80 over the dummy gate 82, as well as portions of the gate seal spacers 90 and gate spacers 94 along the sidewalls of the mask 80. After the planarization process, the top surfaces of the dummy gate 82, gate seal spacer 90, gate spacer 94 and ILD100 are horizontal. Thus, the top surface of dummy gate 82 is exposed through ILD 100.

In fig. 18A and 18B, dummy gate 82 and the portion of dummy gate dielectric layer 84 directly underlying exposed dummy gate 82 are removed in an etch step(s), forming recess 102. In some embodiments, the dummy gate 82 is removed by an anisotropic dry etch process that does not remove the dummy gate 82, the gate seal spacer 90, or the material(s) of the ILD 100. For example, the etching process may include a dry etching process using reactive gas (es) that selectively etch the dummy gate 82 without etching the ILD100 or the gate spacers 94. Each recess 102 exposes a channel region of a respective fin 60. Each channel region is disposed between an adjacent pair of epitaxial source/drain regions 96. During removal, dummy gate dielectric layer 84 may act as an etch stop layer when dummy gate 82 is etched. Dummy gate dielectric layer 84 may then be removed after dummy gate 82 is removed.

In fig. 19A and 19B, a gate dielectric layer 104 and a gate electrode 106 are formed in the recess 102. An interfacial layer is formed conformally over the fin 60 and in the recess 102. An interfacial layer may also cover the upper surface of the ILD 100. The interfacial layer may be formed by a deposition process, such as a CVD process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, and the like. A gate dielectric layer 104 is formed over the interfacial layer. A gate dielectric layer 104 may be conformally deposited in the recess 102, e.g., on the top surface and sidewalls of the fin 60. A gate dielectric layer 104 may also be formed along the top surface of the ILD 100. Gate dielectric layer 104 may be a high-k dielectric material having a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 104 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like. A gate electrode layer is then deposited over gate dielectric layer 104 and in recess 102. The gate electrode layer may be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. The gate electrode layer may include any number of work function tuning layers. A planarization process, such as CMP, is performed to remove excess portions of the gate dielectric layer 104 and the gate electrode layer, which are above the top surface of the ILD 100. The remaining portion of the gate electrode layer forms the gate electrode 106, which in combination with other layers forms the replacement gate of the resulting FinFET. The gate dielectric layer 104 and the gate electrode 106 may be collectively referred to as a "gate" or "gate stack" of the resulting FinFET. The gate stack may extend along sidewalls of the channel region of fin 60.

In fig. 20A and 20B, an ILD 110 is formed over the gate stack and ILD 100. In an embodiment, the ILD 110 is a flowable film formed by a flowable CVD process. In some embodiments, the ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and the like, and may be deposited by any suitable method, for example, CVD and PECVD.

In addition, source/drain contacts 112 and gate contacts 114 are formed through the ILDs 100 and 110. Openings for source/drain contacts 112 are formed through the ILDs 100 and 110, and openings for gate contacts 114 are formed through the ILD 110. The openings may be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (e.g., CMP) may be performed to remove excess material from the surface of ILD 110. The remaining liner and conductive material form source/drain contacts 112 and gate contacts 114 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source/drain regions 96 and the source/drain contacts 112. Source/drain contacts 112 are physically and electrically coupled to the epitaxial source/drain regions 96, and gate contacts 114 are physically and electrically coupled to the gate electrodes 106. The source/drain contacts 112 and the gate contact 114 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it is understood that each of the source/drain contacts 112 and the gate contact 114 may be formed in a different cross-section, which may avoid shorting of the contacts.

In the above embodiment, the oxidation process 62 (see fig. 5-6) is performed after etching the trench 56. However, it should be understood that the oxidation process 62 may be performed after other steps of the process used to form the p-type devices.

Fig. 21-22 are cross-sectional views of intermediate stages of fabrication of a FinFET according to some other embodiments. Similar details regarding this embodiment as the previous embodiment are not repeated herein.

In the embodiment of fig. 21-22, the oxidation process 62 is performed after the STI regions 72 are formed. After etching the trench 56, an STI region 72 is formed in the trench 56 (see fig. 21). An oxidation process 62 (see fig. 22) is then performed. Thus, oxide layer 64 may extend along the top surface of STI region 72. Furthermore, the region of fin 60 extending only over STI region 72 has a second width W₂. Other regions of fin 60 (e.g., below the top surface of STI region 72) may maintain first width W₁. Oxide layer 64 is then removed.

Fig. 23A-24B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some other embodiments. Similar details regarding this embodiment as the previous embodiment are not repeated herein.

In the embodiment of fig. 23A-24B, oxidation process 62 is performed after dummy gate 82 and dummy gate dielectric layer 84 are removed. After forming the recess 102, the damaged sides and top of the fin 60 are exposed (see fig. 23A and 23B). Specifically, the portion of fin 60 extending above the top surface of STI region 72 is exposed. An oxidation process 62 is then performed (see fig. 24A and 24B). Thus, oxide layer 64 may extend only along the portion of fin 60 exposed by recess 102. Furthermore, only the region of the fin 60 exposed by the recess 102 has the second width W₂. Other regions of fin 60 (e.g., below the top surface of STI region 72) may maintain first width W₁. Oxide layer 64 is then removed.

In some embodiments, the oxidation process 62 is performed several times and at different stages of manufacture. For example, the oxidation process 62 may be performed after forming the trench 56 (see fig. 5 and 6), after forming the STI regions 72 (see fig. 21 and 22) in the trench 56, and after forming the recess 102 (see fig. 23A-24B). Some subset of fins 60 may be masked during various iterations of oxidation process 62. Thus, substrate 50 may have multiple fins 60, and different subsets of fins 60 may have different widths and different germanium concentrations.