阅读说明：本技术 一种碳化硅mosfet功率器件及其制备方法 (Silicon carbide MOSFET power device and preparation method thereof ) 是由 王谦 柏松 杨勇 于 2019-10-22 设计创作，主要内容包括：本发明提供一种碳化硅MOSFET功率器件及其制备方法,制备方法包括：提供第一掺杂类型重掺杂的衬底,并于第一表面上形成第一掺杂类型轻掺杂的外延层；于外延层内形成阱区；于阱区内形成环绕JFET区的源区,并于环绕源区的阱区内形成接触区；于定义的JFET区进行所述第一掺杂类型的掺杂,形成JFET埋层式掺杂区；于外延层表面形成栅结构,并于所述栅结构表面沉积表面钝化层；形成与栅结构电连接的栅金属电极,于源区表面形成源金属电极,于衬底的第二表面形成漏金属电极。本发明在常规平面栅MOSFET功率器件的JFET区域进行N型离子注入后形成埋层式掺杂区,在降低JFET区电阻的同时,又可避免栅氧内电场强度提升,降低其击穿风险。(The invention provides a silicon carbide MOSFET power device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate with heavily doped first doping type, and forming a lightly doped epitaxial layer with the first doping type on the first surface; forming a well region in the epitaxial layer; forming a source region surrounding the JFET region in the well region, and forming a contact region in the well region surrounding the source region; doping the first doping type in the defined JFET region to form a JFET buried layer type doping region; forming a gate structure on the surface of the epitaxial layer, and depositing a surface passivation layer on the surface of the gate structure; and forming a gate metal electrode electrically connected with the gate structure, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate. According to the invention, the buried layer type doped region is formed after N-type ion implantation is carried out on the JFET region of the conventional planar gate MOSFET power device, so that the resistance of the JFET region is reduced, the electric field intensity in the gate oxide is prevented from being improved, and the breakdown risk of the gate oxide is reduced.)

1. A preparation method of a silicon carbide MOSFET power device is characterized by comprising the following steps:

s1: providing a substrate with heavily doped first doping type, wherein the substrate is provided with a first surface and a second surface, and an epitaxial layer with lightly doped first doping type is formed on the first surface;

s2: determining a JFET area in the epitaxial layer, and doping the second doping type in the area surrounding the JFET area in the epitaxial layer to form a well area;

s3: heavily doping the first doping type in the well region to form a source region surrounding the JFET region, and heavily doping the second doping type in the region surrounding the source region in the well region to form a contact region;

s4: doping the JFET region with a first doping type to form a JFET buried layer type doping region;

s5: forming a gate structure on the surface of the epitaxial layer, wherein the gate structure at least covers the JFET buried layer type doped region, depositing a surface passivation layer on the surface of the gate structure, and forming a first window corresponding to the gate structure in the surface passivation layer;

s6: forming a source region ohmic contact metal layer on the surfaces of the source region and the protection region, and forming a drain region ohmic contact metal layer on the second surface of the substrate;

s7: and forming a gate metal electrode electrically connected with the gate structure in the first window, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate.

2. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: when the first doping type is N type, the second doping type is P type; and when the first doping type is P type, the second doping type is N type.

3. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in step S3, the depth of the contact region is greater than the depth of the source region, and the depth of the contact region is less than the depth of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

4. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in the step S4, the forming the JFET buried layer type doped region includes the following steps:

s4-1: depositing an injection shielding layer on the surface of the epitaxial layer;

s4-2: forming an injection mask layer on the surface of the injection shielding layer, etching the injection mask layer through a photoetching process to form an injection mask pattern, wherein the injection mask pattern at least covers the well region;

s4-3: taking the implantation mask pattern as an implantation mask, and performing ion implantation in the JFET area;

s4-4: and activating the implanted ions to form a JFET buried layer type doped region.

5. The method of manufacturing a silicon carbide MOSFET power device of claim 4, wherein: in the step S4-1, the thickness of the injection shielding layer is 30-50 nm; in the step S4-3, the number of times of ion implantation is 3-5, the implantation energy is 150-450 keV, and the implantation dose is 3e¹¹～8e¹¹cm^-2(ii) a In the step S4-4, the temperature of the activation treatment is 1650-1750 ℃, and the time of the activation treatment is 20-40 min.

6. The method of fabricating a silicon carbide MOSFET power device as claimed in claim 1, wherein: in step S5, the forming of the gate structure and the surface passivation layer includes the following steps:

s5-1: forming a gate dielectric material layer on the surface of the epitaxial layer by adopting a dry thermal oxidation technology;

s5-2: forming a polycrystalline silicon layer on the surface of the gate dielectric material layer;

s5-3: forming a surface passivation material layer on the surfaces of the polycrystalline silicon layer and the exposed gate dielectric material layer;

s5-4: and etching the surface passivation material layer and the gate dielectric material layer to expose at least the second window corresponding to the source region, and forming a gate structure and a surface passivation layer.

7. A silicon carbide MOSFET power device, comprising:

a substrate heavily doped with a first doping type, having a first surface and a second surface;

a lightly doped epitaxial layer of a first doping type on a first surface of the substrate;

the JFET buried layer type doped region doped with the first doping type is positioned in the epitaxial layer;

the well region doped with the second doping type is positioned in the epitaxial layer and surrounds the JFET buried layer type doping region;

the source region is heavily doped with the first doping type, is positioned in the well region and surrounds the JFET buried layer type doping region;

the contact region with the heavily doped second doping type is positioned in the well region and surrounds the source region;

the gate structure is positioned on the surface of the JFET buried layer type doped region;

a gate metal electrode;

a source metal electrode;

a drain metal electrode;

the source region is in ohmic contact with the metal layer;

the drain region is in ohmic contact with the metal layer;

the grid metal electrode is electrically connected with the grid structure, the source metal electrode is electrically connected with the source region, and the drain metal electrode is electrically connected with the second surface of the substrate;

the source region ohmic contact metal layer is positioned on the surfaces of the source region and the contact region and is positioned below the source metal electrode; the drain ohmic contact metal layer is positioned between the second surface of the substrate and the drain metal electrode.

8. The silicon carbide MOSFET power device of claim 7, wherein: when the first doping type is N type, the second doping type is P type; and when the first doping type is P type, the second doping type is N type.

9. The silicon carbide MOSFET power device of claim 7, wherein: the depth of the JFET buried layer type doped region is 0.2-0.3 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.5 mu m, and the ion doping concentration of the JFET buried layer type doped region is 5e¹⁶～1e¹⁷cm^-3。

10. The silicon carbide MOSFET power device of claim 7, wherein: the depth of the contact region is greater than that of the source region and less than that of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

Technical Field

The invention belongs to the technical field of semiconductor device structures and preparation, and particularly relates to a silicon carbide MOSFET power device and a preparation method thereof.

Background

With the continuous development of power electronic technology towards high energy efficiency, high power density and miniaturization, higher requirements are put on the power consumption and the switching speed of the power switching device. SiC (silicon carbide) as a third-generation semiconductor material has a series of excellent characteristics such as large forbidden band width, high critical breakdown electric field strength, high thermal conductivity and the like, and is very suitable for manufacturing high-temperature, high-frequency and high-power electronic devices. The SiC power switch device can simultaneously realize excellent performances of high breakdown voltage, low on-resistance, high switching speed, easy heat dissipation and the like, has obvious competitiveness in the power electronic technology with high energy efficiency, high power and high temperature, and becomes a research hotspot of the current power semiconductor technology. Particularly, the SiC MOSFET has the performance advantages that the Si MOSFET is incomparable with the IGBT, such as wide forbidden band width, high breakdown voltage, low on-resistance, high switching speed, high energy conversion efficiency, easy heat dissipation, radiation resistance and the like. SiC MOSFETs are rapidly being studied and commercialized as a new generation of power switching devices that have attracted attention. However, compared with foreign countries, the research on the SiC MOSFET power device in China is in the primary stage, the product is mainly imported from foreign countries, and the research and development process of the SiC MOSFET power device is urgently needed to be accelerated.

The on-resistance is one of the most important performance indexes of the power device, and how to reduce the on-resistance of the device is a technical difficulty. Particularly in a planar gate type SiC MOSFET, due to the presence of the parasitic JFET region, a resistance is imparted to the device at the JFET region, thereby increasing the on-resistance of the device. In addition, the dielectric constant of the SiC material is close to that of the SiO gate dielectric₂3 times of the material, and the SiC material has higher critical breakdown electric field intensity (3 MV/cm). Therefore, when the device is operated in the blocking state, it will be in SiO₂High electric field intensity is introduced, so that the breakdown of the high electric field intensity is damaged, and the device fails. Chinese patent No. cn201710678411.x discloses a box-like heavily doped SiC MOSFET device in a JFET region and a method for manufacturing the same, wherein the heavily doped JFET region can not only improve the doping concentration of the region, but also reduce the depletion effect of p-wells on both sides of the region, thereby reducing the parasitic resistance of the JFET region of the device. However, the structure reduces the resistance of the JFET region, and simultaneously increases the electric field intensity in the gate oxide when the device is in a blocking state, so that the gate oxide breakdown risk is increased.

Therefore, it is necessary to provide a SiC MOSFET power device and a method for manufacturing the same, which can effectively reduce the resistance of the JFET region and simultaneously reduce the electric field strength in the gate oxide.

Disclosure of Invention

In order to solve the problems, the invention provides a silicon carbide MOSFET power device and a preparation method thereof, which are used for solving the problems that in the prior art, due to the existence of JFET (junction field effect transistor) area resistance, the on-resistance of the device is large, and the electric field intensity in gate oxide is large.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a preparation method of a silicon carbide MOSFET power device comprises the following steps:

s1: providing a substrate with heavily doped first doping type, wherein the substrate is provided with a first surface and a second surface, and an epitaxial layer with lightly doped first doping type is formed on the first surface;

s2: determining a JFET area in the epitaxial layer, and doping the second doping type in the area surrounding the JFET area in the epitaxial layer to form a well area;

s3: heavily doping the first doping type in the well region to form a source region surrounding the JFET region, and heavily doping the second doping type in the region surrounding the source region in the well region to form a contact region;

s4: doping the JFET region with a first doping type to form a JFET buried layer type doping region;

s5: forming a gate structure on the surface of the epitaxial layer, wherein the gate structure at least covers the JFET buried layer type doped region, depositing a surface passivation layer on the surface of the gate structure, and forming a first window corresponding to the gate structure in the surface passivation layer;

s6: forming a source region ohmic contact metal layer on the surfaces of the source region and the protection region, and forming a drain region ohmic contact metal layer on the second surface of the substrate;

s7: and forming a gate metal electrode electrically connected with the gate structure in the first window, forming a source metal electrode on the surface of the source region, and forming a drain metal electrode on the second surface of the substrate.

In this technical solution, preferably, when the first doping type is an N type, the second doping type is a P type; when the first doping type is P type, the second doping type is N type.

Preferably, in step S1, a buffer layer is formed in advance of the first surface of the substrate, and then an epitaxial layer is formed on the buffer layer.

Preferably, in step S3, the depth of the contact region is greater than that of the source region, and the depth of the contact region is less than that of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

Preferably, in step S4, the forming the JFET buried layer type doped region includes the following steps:

s4-1: depositing an injection shielding layer on the surface of the epitaxial layer;

s4-2: forming an injection mask layer on the surface of the injection shielding layer, etching the injection mask layer through a photoetching process to form an injection mask pattern, wherein the injection mask pattern at least covers the well region;

s4-3: taking the implantation mask pattern as an implantation mask, and performing ion implantation in the JFET area;

s4-4: and activating the implanted ions to form a JFET buried layer type doped region.

Preferably, in step S4-1, the thickness of the injection shielding layer is 30 to 50 nm; in step S4-3, the number of times of ion implantation is 3-5, the implantation energy is 150-450 keV, and the implantation dose is 3e¹¹～8e¹¹cm^-2(ii) a In the step S4-4, the temperature of the activation treatment is 1650-1750 ℃, and the time of the activation treatment is 20-40 min.

Preferably, in step S5, the forming the gate structure and the surface passivation layer includes the following steps:

s5-1: forming a gate dielectric material layer on the surface of the epitaxial layer by adopting a dry thermal oxidation technology;

s5-2: forming a polycrystalline silicon layer on the surface of the gate dielectric material layer;

s5-3: forming a surface passivation material layer on the surfaces of the polycrystalline silicon layer and the exposed gate dielectric material layer;

s5-4: and etching the surface passivation material layer and the gate dielectric material layer to expose at least the second window corresponding to the source region, and forming a gate structure and a surface passivation layer.

Preferably, a silicon carbide MOSFET power device, comprising:

a substrate heavily doped with a first doping type, having a first surface and a second surface;

a lightly doped epitaxial layer of a first doping type on the first surface of the substrate;

the JFET buried layer type doped region doped with the first doping type is positioned in the epitaxial layer;

the well region doped with the second doping type is positioned in the epitaxial layer and surrounds the JFET buried layer type doping region;

the source region with the heavily doped first doping type is positioned in the well region and surrounds the JFET buried layer type doping region;

the contact region with the heavily doped second doping type is positioned in the well region and surrounds the source region;

the gate structure is positioned on the surface of the JFET buried layer type doped region;

a gate metal electrode;

a source metal electrode;

a drain metal electrode;

the source region is in ohmic contact with the metal layer;

the drain region is in ohmic contact with the metal layer;

the grid metal electrode is electrically connected with the grid structure, the source metal electrode is electrically connected with the source region, and the drain metal electrode is electrically connected with the second surface of the substrate;

the source region ohmic contact metal layer is positioned on the surfaces of the source region and the contact region and is positioned below the source metal electrode; the drain ohmic contact metal layer is positioned between the second surface of the substrate and the drain metal electrode.

Preferably, when the first doping type is N-type, the second doping type is P-type; when the first doping type is P type, the second doping type is N type.

Preferably, the depth of the JFET buried layer type doped region is 0.2-0.3 mu m below the surface of the epitaxial layer, the depth range is 0.3-0.5 mu m, and the ion doping concentration of the JFET buried layer type doped region is 5e¹⁶～1e¹⁷ cm^-3。

Preferably, the depth of the contact region is greater than the depth of the source region and less than the depth of the well region; the distance between the inner side wall of the source region and the inner side wall of the well region is 0.5-1 mu m.

Preferably, the silicon carbide MOSFET power device further comprises a buffer layer located between the substrate and the epitaxial layer; the epitaxial layer is made of 4H-SiC, and the crystal orientation of the substrate deviates from the (11-20) direction by an inclination angle of 4 +/-0.5 degrees.

Preferably, the surface of the gate structure further comprises a surface passivation layer, and the thickness of the surface passivation layer is 0.6-1.0 μm.

Advantageous effects

The invention optimizes the structure of the device, and particularly forms a buried layer type heavily doped structure after n-type ion implantation is carried out in a JFET (junction field effect transistor) area of a conventional planar gate MOSFET (metal-oxide-semiconductor field effect transistor) power device. The structure can improve the doping concentration of the JFET region, increase the carrier concentration of the JFET region and increase the current transmission capability; the depletion effect of the double-side well region on the JFET region can be reduced, so that more carriers can participate in conduction. Accordingly, the buried layer type heavily doped structure can reduce the JFET region resistance of the SiC MOSFET device, preferably reducing the on-resistance of the device. In addition, the buried layer type heavily doped structure does not increase the doping concentration of a JFET (junction field effect transistor) region below the gate oxide, so that the increase of the electric field intensity in the gate oxide can be avoided, the gate oxide breakdown risk is reduced, and the gate oxide reliability is improved.

The device structure and the preparation process are simple, the effect is obvious, and the device structure and the preparation method have wide application prospects in the novel MOSFET power device structure and the preparation method.

Drawings

The invention is further illustrated with reference to the following figures and examples.

Fig. 1 is a flow chart of a method for manufacturing a silicon carbide MOSFET power device according to the present invention.

Fig. 2 to 14 are schematic structural views of steps in the preparation of the silicon carbide MOSFET power device of the present invention:

FIG. 2 is a schematic diagram of a structure for providing a substrate in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 3 is a schematic diagram of the structure of the epitaxial layer formed in the preparation of the silicon carbide MOSFET power device of the present invention;

FIG. 4 is a schematic diagram of the structure of the buffer layer formed in the fabrication of the silicon carbide MOSFET power device of the present invention;

FIG. 5 is a schematic diagram of a well region formed in the fabrication of a silicon carbide MOSFET power device according to the present invention;

FIG. 6 is a schematic diagram of the structure for forming source and contact regions in the fabrication of a silicon carbide MOSFET power device of the present invention;

FIG. 7 is a schematic structural diagram of a buried doped region for forming a JFET in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 8 is a schematic structural diagram of a gate dielectric material layer formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 9 is a schematic diagram of a polysilicon layer formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 10 is a schematic diagram of a structure for forming a surface passivation layer in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 11 is a schematic diagram of a gate structure and a second window formed in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

FIG. 12 is a schematic structural diagram of a source and drain ohmic contact metal layer formed during fabrication of a silicon carbide MOSFET power device in accordance with the present invention;

fig. 13 is a schematic diagram of a first window formation in the fabrication of a silicon carbide MOSFET power device in accordance with the present invention.

Fig. 14 is a schematic diagram of the structure of the electrode formed in the preparation of the silicon carbide MOSFET power device of the present invention.

In the drawings:

101. substrate 102, buffer layer 103, epitaxial layer 104, well region

105. Source region 106, contact region 107, JFET buried layer type doped region 108, and gate dielectric material layer

109. Polysilicon layer 110, surface passivation material layer 111, gate dielectric layer 112, and surface passivation layer

113. Second window 114, source ohmic contact metal layer 115, drain ohmic contact metal layer 116, first window

117. Source metal electrode 118, gate metal electrode 119, drain metal electrode 120, gate structure

1011. First surface 1012 and second surface

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.