阅读说明：本技术 双层材料异质栅介质层柔性硅薄膜晶体管及其制造方法 (Double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor and manufacturing method thereof ) 是由 秦国轩 裴智慧 于 2019-09-27 设计创作，主要内容包括：本发明属于柔性器件领域,为提出一种柔性双层材料作为栅介质层的底栅结构晶体管,丰富晶体管作为电路元器件的用处,使得该柔性器件在大规模集成电路和光电器件的应用提供了可能,本发明双层材料异质栅介质层柔性硅薄膜晶体管及其制造方法,采用磁控溅射工艺在PET衬底上形成ITO底栅电极以及TiO<Sub>2</Sub>/Ta<Sub>2</Sub>O<Sub>5</Sub>栅介质膜,随后在SOI上采用光刻工艺形成掺杂区图案以及离子注入的方式形成掺杂区,采用光刻以及离子刻蚀的方式形成方孔层,采用湿法HF刻蚀的方式形成硅纳米膜层,通过转移技术将硅纳米薄膜转移到PET衬底上,最后通过光刻以及真空电子束蒸镀的方式形成源漏电极,完成晶体管的制备。本发明主要应用于设计制造场合。(The invention belongs to the field of flexible devices, and provides a bottom gate structure transistor with a flexible double-layer material as a gate dielectric layer, which enriches the use of the transistor as a circuit component and makes the application of the flexible device in large-scale integrated circuits and photoelectric devices possible 2 /Ta 2 O 5 A gate dielectric film, subsequent patterning of doped regions on the SOI by photolithography and ion implantationThe method comprises the steps of forming a doped region, forming a square hole layer by adopting a photoetching and ion etching mode, forming a silicon nano film layer by adopting a wet HF etching mode, transferring the silicon nano film to a PET substrate by a transfer technology, and finally forming a source electrode and a drain electrode by adopting a photoetching and vacuum electron beam evaporation mode to finish the preparation of the transistor. The invention is mainly applied to design and manufacture occasions.)

1. A manufacturing method of a double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor is characterized in that an Indium Tin Oxide (ITO) bottom gate electrode and titanium oxide (TiO) are formed on a polyethylene glycol terephthalate (PET) substrate by adopting a magnetron sputtering process₂Ta/tantalum oxide₂O₅And then forming a doped region pattern on the SOI by adopting a photoetching process and forming a doped region by adopting an ion implantation mode, forming a square hole layer by adopting a photoetching and ion etching mode, forming a silicon nano film layer by adopting a wet HF (high frequency) etching mode, transferring the silicon nano film to a PET (polyethylene terephthalate) substrate by adopting a transfer technology, and finally forming a source electrode and a drain electrode by adopting a photoetching and vacuum electron beam evaporation mode to finish the preparation of the transistor.

2. The manufacturing method of the double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor as claimed in claim 1, characterized in that the specific manufacturing process is as follows:

selecting a polyethylene terephthalate (PET) flexible material as a substrate, firstly putting PET into a beaker filled with an acetone solution, then cleaning the PET in an ultrasonic cleaner for 5 minutes, and then cleaning the acetone in the ultrasonic cleaner by using an isopropanol solution to obtain a cleaner substrate;

plating titanium oxide ITO film and titanium oxide TiO on PET substrate by adopting magnetron sputtering₂And tantalum oxide Ta₂O₅As a bottom dielectric gate layer film;

selecting an SOI material, cleaning the SOI material by using acetone in an ultrasonic cleaner, cleaning acetone residues by using isopropanol, and drying the SOI material;

coating 1813 positive photoresist on the surface of the SOI, using a spin coater to uniformly spin the photoresist, then using a photoetching machine and a manufactured mask plate to carry out photoetching to form a specific doped region pattern, then carrying out N-type injection in an ion injection mode to generate a source drain doped region, and removing the photoresist in an acetone solution after carrying out rapid thermal annealing for 10s at the temperature of 750 ℃;

according to the mark made on the mask, carrying out alignment photoetching on the source-drain doped region and a square hole layer arranged on the mask at a distance of 5um, forming a square hole layer arranged at a distance of 5um on the SOI after developing, and then removing silicon on the square hole layer by adopting an ion etching mode;

putting the prepared SOI into hydrofluoric acid HF solution with the ratio of 3:1, etching an oxygen buried layer on the SOI after two hours, then enabling a silicon nano film layer to fall off, transferring the silicon nano film layer onto a flexible PET substrate plated with ITO and a gate dielectric layer, and drying;

and gluing the silicon nano film transferred to the PET, aligning photoetching to form photoetching patterns of the source and drain electrodes, forming a metal source and drain electrode layer by adopting a vacuum electron beam evaporation mode, and removing the glue to finish the preparation of the device.

The double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor comprises a PET (polyethylene terephthalate) plastic substrate, and an Indium Tin Oxide (ITO) gate electrode layer and a titanium oxide (TiO) gate electrode layer which are sequentially arranged on the PET plastic substrate₂And tantalum oxide Ta₂O₅The double-layer material is used as a grid dielectric layer and an N-type doped silicon nano film, and a metal source drain electrode layer is arranged on the N-type doped silicon nano film.

3. A flexible silicon thin film transistor with a double-layer material heterogeneous gate dielectric layer is characterized in that a certain bias voltage is applied to an ITO bottom gate electrode, when the applied voltage is small or no bias voltage exists, a silicon nano film layer does not generate an inversion layer, even if voltage is added between a source and a drain, current cannot be generated between the source and the drain, and a device is turned off; when the voltage is large enough, the silicon nano film layer generates an electron inversion layer on the surface contacted with the gate oxide layer, the silicon nano film with more holes in the original transistor generates a surface inversion region with the number of electrons larger than that of the holes on the surface close to the gate dielectric layer, the region is called as a channel region of the device, and then bias voltage is applied to the N-type doped source and drain electrodes to generate current between the source and drain electrodes, so that the device is conducted.

Technical Field

The invention belongs to the field of flexible devices, and particularly relates to a structural design and a preparation method of a bottom gate thin film transistor taking a double-layer material based on a silicon nano-film as a gate dielectric layer.

Background

Flexible electronics is a new electronic technology for manufacturing organic and inorganic electronic devices on flexible and ductile plastic or thin metal substrates, and has wide application in the fields of information, energy, medical treatment, national defense and the like. Such as printed radio frequency identification tags (RFID), electronic surface stickers, organic light emitting diodes OLEDs, flexible electronic displays, and the like. As with conventional Integrated Circuit (IC) technology, the primary driver for the development of flexible electronic technology is the fabrication process and equipment. It is critical to manufacture flexible electronic devices with smaller feature sizes at lower cost on larger substrates. The invention adopts a novel process based on silicon nano-film preparation, adopts magnetron sputtering to form a bottom gate electrode, adopts the technologies of ion etching after photoetching and hydrofluoric acid (HF) wet etching to strip and transfer the silicon nano-film on silicon-on-insulator (SOI) to a flexible and bendable polyethylene terephthalate (PET) substrate, and then forms a metal source drain electrode through photoetching and vacuum electron beam evaporation technology, thereby being expected to be widely applied in the aspects of wearable electronics, large-scale flexible integrated circuits and the like.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to design and prepare a bottom gate structure transistor taking a double-layer material based on a flexible PET substrate as a gate dielectric layer, adopts a low-temperature magnetron sputtering process, designs and prepares a bottom-driven flexible thin film transistor in a simpler process, greatly enriches the use of the transistor as a circuit component, and provides possibility for the application of the flexible device in large-scale integrated circuits and photoelectric devices. Therefore, the invention adopts the technical scheme that the manufacturing method of the double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor adopts the magnetron sputtering process to form an Indium Tin Oxide (ITO) bottom gate electrode and titanium oxide (TiO) on a polyethylene glycol terephthalate (PET) substrate₂Ta/tantalum oxide₂O₅Forming a gate dielectric film, forming a doped region pattern on the SOI by photolithography and ion implantation, forming a square hole layer by photolithography and ion etching, and forming a gate electrode on the SOI by ion implantationAnd forming a silicon nano film layer by using a wet HF etching mode, transferring the silicon nano film to a PET substrate by using a transfer technology, and finally forming a source electrode and a drain electrode by using photoetching and vacuum electron beam evaporation modes to finish the preparation of the transistor.

The specific manufacturing process is as follows:

a. selecting a polyethylene terephthalate (PET) flexible material as a substrate, firstly putting PET into a beaker filled with an acetone solution, then cleaning the PET in an ultrasonic cleaner for 5 minutes, and then cleaning the acetone in the ultrasonic cleaner by using an isopropanol solution to obtain a cleaner substrate;

b. plating titanium oxide ITO film and titanium oxide TiO on PET substrate by adopting magnetron sputtering₂And tantalum oxide Ta₂O₅As a bottom dielectric gate layer film;

c. selecting an SOI material, cleaning the SOI material by using acetone in an ultrasonic cleaner, cleaning acetone residues by using isopropanol, and drying the SOI material;

d. coating 1813 positive photoresist on the surface of the SOI, using a spin coater to uniformly spin the photoresist, then using a photoetching machine and a manufactured mask plate to carry out photoetching to form a specific doped region pattern, then carrying out N-type injection in an ion injection mode to generate a source drain doped region, and removing the photoresist in an acetone solution after carrying out rapid thermal annealing for 10s at the temperature of 750 ℃;

e. according to the mark made on the mask, carrying out alignment photoetching on the source-drain doped region and a square hole layer arranged on the mask at a distance of 5um, forming a square hole layer arranged at a distance of 5um on the SOI after developing, and then removing silicon on the square hole layer by adopting an ion etching mode;

f. putting the prepared SOI into hydrofluoric acid HF solution with the ratio of 3:1, etching an oxygen buried layer on the SOI after two hours, then enabling a silicon nano film layer to fall off, transferring the silicon nano film layer onto a flexible PET substrate plated with ITO and a gate dielectric layer, and drying;

g. and gluing the silicon nano film transferred to the PET, aligning photoetching to form photoetching patterns of the source and drain electrodes, forming a metal source and drain electrode layer by adopting a vacuum electron beam evaporation mode, and removing the glue to finish the preparation of the device.

The double-layer material heterogeneous gate dielectric layer flexible silicon thin film transistor comprises a PET (polyethylene terephthalate) plastic substrate, and an Indium Tin Oxide (ITO) gate electrode layer and a titanium oxide (TiO) gate electrode layer which are sequentially arranged on the PET plastic substrate₂And tantalum oxide Ta₂O₅The double-layer material is used as a grid dielectric layer and an N-type doped silicon nano film, and a metal source drain electrode layer is arranged on the N-type doped silicon nano film.

A certain bias voltage is applied to the ITO bottom gate electrode, when the applied voltage is small or no bias voltage exists, the silicon nano film layer does not generate an inversion layer, and even if voltage is added between the source and the drain, current cannot be generated between the source and the drain, and the device is turned off; when the voltage is large enough, the silicon nano film layer generates an electron inversion layer on the surface contacted with the gate oxide layer, the silicon nano film with more holes in the original transistor generates a surface inversion region with the number of electrons larger than that of the holes on the surface close to the gate dielectric layer, the region is called as a channel region of the device, and then bias voltage is applied to the N-type doped source and drain electrodes to generate current between the source and drain electrodes, so that the device is conducted.

The invention has the characteristics and beneficial effects that:

the transistor designed by the invention has a high-dielectric-constant grid dielectric layer, can be made to be very thin under the same condition, thereby meeting the trend of gradually reducing the size of an integrated circuit, has better performance, higher working frequency and stronger grid control force, and has wide application prospect in the fields of manufacturing, intelligent wearing and photoelectric devices of flexible integrated circuits.

Description of the drawings:

fig. 1 is a cross-sectional view of a flexible bottom-gate thin film transistor.

Fig. 2 is a working principle diagram of the invention.

Detailed Description

The invention discloses a double-layer heterogeneous gate dielectric layer transistor prepared on a polyethylene terephthalate (PET) plastic substrate based on a silicon film transfer technology on a flexible substrateThe main structure of the transistor comprises a PET plastic substrate, an Indium Tin Oxide (ITO) gate electrode layer and titanium oxide (TiO)₂) And tantalum oxide (Ta)₂O₅) The double-layer material is used as a grid dielectric layer, an N-type doped silicon nano film and a metal source drain electrode layer. The method adopts a novel preparation process, and two layers of grid dielectric layers, namely TiO dielectric layers are coated on a PET substrate deposited with an ITO conductive layer by adopting a magnetron sputtering method₂And Ta₂O₅And as a bottom gate oxide layer, forming an N-type doped region on a silicon-on-insulator (SOI) through photoetching and ion implantation technology to serve as a source/drain active region, and transferring a top silicon film onto ITO/PET sputtered with a gate dielectric layer through a silicon film transfer technology. And then, a source electrode and a drain electrode are prepared by designing and preparing a mask plate through photoetching, so that the preparation of a bottom gate structure transistor working under higher frequency is realized. The transistor has a gate dielectric layer with high dielectric constant, can be made very thin under the same condition, thereby meeting the trend of gradually reducing the size of an integrated circuit, has better performance, higher working frequency and stronger gate control force, and has wide application prospect in the fields of manufacture, intelligent wearing and photoelectric devices of flexible integrated circuits.

The technical scheme of the invention is that an ITO bottom gate electrode and TiO are formed on a PET substrate by adopting a magnetron sputtering process₂/Ta₂O₅Forming a gate dielectric film, forming a doped region pattern on the SOI by adopting a photoetching process and forming a doped region by adopting an ion injection mode, forming a square hole layer by adopting a photoetching and ion etching mode, forming a silicon nano film layer by adopting a wet HF etching mode, transferring the silicon nano film to a PET substrate by a transfer technology, and finally forming a source electrode and a drain electrode by adopting a photoetching and vacuum electron beam evaporation mode, thereby completing the preparation of the transistor.

The main working principle of the grid dielectric layer thin film transistor made of the flexible bottom grid double-layer material lies in that an electronic inversion layer is formed at a position, close to a grid dielectric layer, of a source-drain doped region by applying bias voltage on a bottom grid electrode and is used as a conductive channel of a device, the device is conducted, then the bias voltage is applied between the source-drain electrode, the device starts to work, whether the device is conducted or not and current between the source and the drain of the device are controlled through grid voltage, in addition, the parasitic effect of the traditional silicon-based substrate transistor can be reduced by the flexible substrate, the flexible substrate can work under different bending degrees, and the possibility is provided for large-scale integration of a high-performance flexible circuit and wide application of wearable electronic equipment.

And a certain bias voltage is applied to the ITO bottom gate electrode, and when the applied voltage is small or no bias voltage is applied, the silicon nano thin film layer does not generate an inversion layer, so that current cannot be generated between the source and the drain even if voltage is added between the source and the drain, and the device is turned off. When the voltage is large enough, the silicon nano film layer generates an electron inversion layer at the surface contacted with the gate oxide layer, the silicon nano film with more holes in the transistor generates a surface inversion region with the number of electrons larger than that of the holes at the position close to the surface of the gate dielectric layer, the region is called as a channel region of the device, and then bias voltage is applied to the N-type doped source and drain electrodes, so that current between the source and drain electrodes is generated, and the device is conducted. The device in the invention has higher integration level and wider application. In addition, the invention is a transistor device integrated on the plastic substrate, when the plastic substrate is bent, the normal operation of the device can be still met, and the transistor device can be widely applied to the aspects of intelligent wearing, artificial skin, biomedical treatment, photoelectric devices and the like.

The specific manufacturing process is as follows:

a. selecting a PET flexible material as a substrate, firstly putting PET into a beaker filled with an acetone solution, then cleaning the PET in an ultrasonic cleaner for 5 minutes, and then cleaning the acetone in the ultrasonic cleaner by using an isopropanol solution to obtain a cleaner substrate.

b. Plating 200nm thick ITO film and 50nm thick TiO film on PET substrate by magnetron sputtering₂And 50nm of Ta₂O₅As a bottom dielectric gate layer film.

c. Selecting an SOI material, cleaning the SOI material by using acetone in an ultrasonic cleaner, then cleaning acetone residues by using isopropanol, and drying the SOI.

d. Coating 1813 positive type on SOI surfacePhotoresist is uniformly thrown by a photoresist spin coater with the set rotating speed of 4000rpm and the set rotating time of 30s, then a photoetching machine and a manufactured mask plate are used for photoetching to form a specific doped region pattern, and then N-type implantation is carried out by adopting an ion implantation mode with the parameters of implantation energy of 40Kev and the dosage of 4 x 10¹⁵cm^-2And generating a source drain doped region, and removing the photoresist in an acetone solution after rapid thermal annealing for 10s at the temperature of 750 ℃.

e. According to the mark made on the mask, the source-drain doping area and the square hole layer arranged on the mask at the interval of 5um are aligned and photoetched, the square hole layer arranged at the interval of 5um is formed on the SOI after development, and then the silicon on the square hole is removed by adopting an ion etching mode.

f. Putting the SOI into hydrofluoric acid (HF) solution with the ratio of 3:1, etching an oxygen buried layer on the SOI after two hours, then peeling off a silicon nano film layer, transferring the silicon nano film layer onto a flexible PET substrate plated with ITO and a gate dielectric layer, and drying.

g. Gluing the silicon nano film transferred to the PET, aligning photoetching to form photoetching patterns of source and drain electrodes, forming a metal source and drain electrode layer of 100nm in a vacuum electron beam evaporation mode, and removing the glue to finish the preparation of the device.