阅读说明：本技术 电子器件和电路 (Electronic device and circuit ) 是由 全祐哲 P·文凯特拉曼 于 2019-07-02 设计创作，主要内容包括：本公开涉及电路和电子器件。本发明公开了一种电子器件和电路。该电子器件可以包括沟道层和覆盖沟道层的阻挡层。在一个实施方案中,电子器件可以包括沿栅极端子与第一晶体管的栅极电极之间的电流路径设置的部件。在另一个实施方案中,电子器件可以包括第二晶体管,其中该第二晶体管的源极电极和栅极电极耦接到第一晶体管的栅极电极,并且第二晶体管的漏极电极耦接到栅极端子。所述电路可以包括晶体管和二极管。所述晶体管可以包括漏极、栅极和源极,其中漏极耦接到漏极端子,并且源极耦接到源极端子。二极管可以具有耦接到栅极端子的阳极以及耦接到晶体管的栅极的阴极。(The present disclosure relates to circuits and electronic devices. The invention discloses an electronic device and a circuit. The electronic device may include a channel layer and a barrier layer overlying the channel layer. In one embodiment, an electronic device may include a component disposed along a current path between a gate terminal and a gate electrode of a first transistor. In another embodiment, an electronic device may include a second transistor, wherein a source electrode and a gate electrode of the second transistor are coupled to a gate electrode of the first transistor, and a drain electrode of the second transistor is coupled to a gate terminal. The circuit may include a transistor and a diode. The transistor may include a drain, a gate, and a source, where the drain is coupled to the drain terminal and the source is coupled to the source terminal. The diode may have an anode coupled to the gate terminal and a cathode coupled to the gate of the transistor.)

1. An electronic device, comprising:

a channel layer covering a substrate;

a barrier layer overlying the channel layer;

a gate electrode of a first transistor overlying the channel layer, wherein the first transistor is an enhancement mode transistor;

a gate terminal; and

a first component having a threshold voltage, wherein the first component is disposed along a current path between the gate terminal and the gate electrode.

2. The electronic device of claim 1, wherein the first component is a first diode having an anode and a cathode, wherein the anode is coupled to the gate terminal and the cathode is coupled to the gate electrode.

3. The electronic device of claim 2, further comprising a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode.

4. The electronic device of claim 3, wherein a threshold voltage of the second diode is less than a threshold voltage of the first transistor.

5. The electronic device of claim 2, further comprising a second transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the cathode of the first diode and the drain electrode of the second transistor is coupled to the anode of the first diode.

6. The electronic device of claim 2, further comprising a second component, wherein:

the channel layer includes a GaN layer, and the channel layer includes,

the barrier layer comprises Al_xGa_(1-x)N, wherein 0<x≤0.4，

The first transistor is an enhancement mode high electron mobility transistor,

the gate electrode comprises a p-type semiconductor material,

the second component is:

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode, or

A second transistor as a depletion mode high electron mobility transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the cathode of the first diode and the drain electrode of the second transistor is coupled to the anode of the first diode,

a threshold voltage of the second component is less than a threshold voltage of the first transistor, and

the first transistor and the first and second components are located on the same die.

7. An electronic device, comprising:

a channel layer covering a substrate;

a barrier layer overlying the channel layer;

a gate electrode of a first transistor, the gate electrode overlying the channel layer;

a gate terminal; and

a second transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the gate electrode of the first transistor, and the drain electrode of the second transistor is coupled to the gate terminal.

8. The electronic device of claim 7, wherein the first transistor is an enhancement-mode transistor and the second transistor is a depletion-mode transistor.

9. A circuit, comprising:

a drain terminal, a gate terminal, and a source terminal;

a first transistor as an enhancement mode transistor including a drain, a gate, and a source, wherein the drain is coupled to the drain terminal and the source is coupled to the source terminal; and

a first diode having an anode and a cathode, wherein the anode is coupled to the gate terminal and the cathode is coupled to the gate of the first transistor.

10. The circuit of claim 9, further comprising a component, wherein the component is:

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode, or

A second transistor having a source, a gate, and a drain, wherein the source electrode and the gate electrode of the second transistor are coupled to the cathode of the first diode and the drain electrode of the second transistor is coupled to the anode of the first diode,

wherein the first transistor is an enhancement mode high electron mobility transistor.

Technical Field

The present disclosure relates to circuits and electronic devices, and more particularly, to circuits and electronic devices including enhancement mode transistors.

Background

The high electron mobility transistor may include an enhancement type transistor. One type of such transistor may include a p-type GaN gate electrode. The high electron mobility transistor having the p-type GaN gate electrode may have a threshold voltage of about 1.5V. In an attempt to increase the threshold voltage, a component may be added between the gate terminal and the p-type GaN gate electrode. The component may include a schottky diode between a metal gate interconnect and a p-type GaN gate electrode, wherein the metal gate interconnect is coupled to a cathode of the schottky diode and the p-type GaN gate electrode is coupled to an anode of the schottky diode. In another structure, an n-type GaN layer may be disposed between the metal gate interconnect and the p-type GaN gate electrode. The pn junction diode is formed at an interface between the n-type GaN layer and the p-type GaN gate electrode. In another structure, a dielectric layer may be disposed between a p-type GaN gate electrode and an interconnect connected to a source electrode of a transistor. Such attempts to increase the threshold voltage may result in the threshold voltage being too high, the threshold may become unstable and may shift over time, or control of the transistor may be compromised. It would be desirable to further improve enhancement mode high electron mobility transistors without the aforementioned disadvantageous complications.

Disclosure of Invention

The problem to be solved by the invention relates to increasing the voltage of the transistor needed to turn on the transistor while maintaining substantially the same or a lower on-state resistance and gate current of the transistor.

According to an aspect of the present invention, an electronic device is provided. The electronic device may include: a channel layer covering the substrate; a barrier layer covering the channel layer; a gate electrode of a first transistor, the gate electrode overlying the channel layer, wherein the first transistor is an enhancement mode transistor; a gate terminal; and a first component having a threshold voltage, wherein the first component is disposed along a current path between the gate terminal and the gate electrode.

In one embodiment, the first component may be a first diode having an anode and a cathode, wherein the anode is coupled to the gate terminal and the cathode is coupled to the gate electrode.

In a particular embodiment, the electronic device may further include a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode.

In a more specific embodiment, the threshold voltage of the second diode may be less than the threshold voltage of the first transistor.

In another particular embodiment, the electronic device may further include a second transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the cathode of the first diode and the drain electrode of the second transistor is coupled to the anode of the first diode.

In further embodiments, the electronic device may further comprise a second component. The channel layer may include GaN and the barrier layer includes Al_xGa_(1-x)N, wherein 0<x ≦ 0.4, the first transistor may be an enhancement mode high electron mobility transistor, and the gate electrode may include a p-type semiconductor material. The second component may be a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode, or a second transistor that is a depletion mode high electron mobility transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the cathode of the first diode and the drain electrode of the second transistor is coupled to the anode of the first diode. The threshold voltage of the second component may be less than the threshold voltage of the first transistor, and the first transistor and the first and second components may be located on the same die.

In another aspect, an electronic device is provided. The electronic device may include: a channel layer covering the substrate; a barrier layer covering the channel layer; a gate electrode of the first transistor, the gate electrode covering the channel layer; a gate terminal; and a second transistor having a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the gate electrode of the second transistor are coupled to the gate electrode of the first transistor, and the drain electrode of the second transistor is coupled to the gate terminal.

In one embodiment, the first transistor is an enhancement transistor and the second transistor is a depletion transistor.

In a further aspect, a circuit is provided. The circuit may include: a drain terminal, a gate terminal, and a source terminal; a first transistor as an enhancement mode transistor including a drain, a gate, and a source, wherein the drain is coupled to the drain terminal and the source is coupled to the source terminal; and a first diode having an anode and a cathode, wherein the anode is coupled to the gate terminal and the cathode is coupled to the gate of the first transistor.

In one embodiment, the circuit may further include a component, wherein the component is a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the cathode of the first diode and the cathode of the second diode is coupled to the anode of the first diode, or a second transistor having a source, a gate, and a drain, wherein a source electrode and a gate electrode of the second transistor are coupled to the cathode of the first diode and a drain electrode of the second transistor is coupled to the anode of the first diode, wherein the first transistor is an enhanced high electron mobility transistor.

The technical effect achieved by the invention is the realization of an electronic device and a circuit with a first component coupled between a gate terminal and a gate of a transistor. The first component may help to increase the voltage required to be applied at the gate terminal to turn on the transistor. In a particular embodiment, a second component may be coupled to a terminal of the first component, where the second component may help to more quickly dissipate charge that may otherwise accumulate between the first component and the gate electrode of the transistor.

Drawings

Embodiments are shown by way of example in the drawings and the embodiments are not limited thereto.

Fig. 1 includes a schematic diagram of a circuit including a transistor and a diode according to one embodiment.

Fig. 2 includes a schematic diagram of a circuit including transistors and back-to-back diodes according to another embodiment.

Fig. 3 includes a schematic diagram of a circuit including a transistor and a combination of a diode and another transistor connected in parallel according to further embodiments.

Fig. 4 includes a schematic diagram of a circuit including a transistor and a set of diodes connected in series and another diode connected in parallel with the set of diodes according to yet another embodiment.

Fig. 5 includes an illustration of a cross-sectional view of a portion of a workpiece including a substrate and several layers after patterning a gate electrode layer.

Fig. 6 includes an illustration of a top view, as shown in fig. 5, after patterning the gate electrode layer.

FIG. 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after forming a source electrode, a drain electrode, and a set of interconnects.

Fig. 8 includes an illustration of a top view of the workpiece after forming the source and drain electrodes and a set of interconnects, as shown in fig. 7.

Fig. 9 includes an illustration of a cross-sectional view of the workpiece of fig. 7 after forming another level of interconnect.

Fig. 10 includes an illustration of a cross-sectional view of another portion of the workpiece of fig. 9, where such other portion includes one of the diodes shown in fig. 2.

FIG. 11 includes an illustration of a cross-sectional view of another portion of the workpiece of FIG. 10 where such other portion includes a transistor connected in parallel with a diode, as shown in FIG. 3.

Fig. 12 includes plots of drain current and gate current as a function of gate voltage for the comparison circuit and the circuit of fig. 2.

Fig. 13 includes a plot of drain current as a function of drain voltage for the circuit of fig. 2.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

The following description, in conjunction with the drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to help describe the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings as disclosed in this application.

III-V material is intended to mean a material comprising at least one group 13 element and at least one group 15 element. III-N material is intended to mean a semiconductor material comprising at least one group 13 element and nitrogen.

The term "metal" or any variation thereof is intended to mean a material comprising the following elements: elements within any one of groups 1 to 12, and elements within groups 13 to 16, are along the line defined by atomic numbers 13(Al), 31(Ga), 50(Sn), 51(Sb), and 84(Po) and the elements thereunder. The metal does not include Si or Ge.

The term "pn-junction diode" is intended to mean a diode formed at the junction of a p-type semiconductor material and an n-type semiconductor material. A comparison was made between a pn junction diode and a schottky diode with relatively low to moderate dopant concentrations (such as up to 1 x 10) in metallic materials¹⁸Atom/cm³) Is formed at the interface of the semiconductor material.

The term "semiconductor base material" refers to the predominant material within a semiconductor substrate, region, or layer, and does not refer to any dopant within a semiconductor substrate, region, or layer. The boron-doped Si layer has Si as a semiconductor base material, and the C-doped GaN layer has GaN as a semiconductor base material.

The term "threshold voltage" with respect to a component is intended to mean the voltage at which a significant current (greater than leakage current) flows through such a component. For a diode, the threshold voltage corresponds to the forward bias voltage at which significant current begins to flow through the diode. For many diodes, such forward voltages are in the range of 1V to 2V. For an n-channel depletion transistor, a voltage just above the pinch-off voltage corresponds to the threshold voltage.

The terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" means an inclusive or, rather than an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

In addition, "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. The description is to be construed as including one, at least one, or the singular also includes the plural and vice versa unless it is explicitly stated that the contrary is intended. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.

The use of the words "about", "about" or "substantially" is intended to mean that the value of a parameter is close to a specified value or location. However, a slight difference may prevent the value or position from being exactly as specified. Thus, from an ideal target as fully described, a difference of at most ten percent (10%) for the value is a reasonable difference.

The group numbers corresponding to the columns in the periodic table are based on the IUPAC periodic table, 2016, 11, 28, th edition.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronics arts, without being described herein.

The circuits and electronics may include enhancement mode transistors that allow for more stable increased threshold voltages over time while maintaining acceptably low gate currents. The circuits and electronic devices are well suited for use in enhancement mode High Electron Mobility Transistors (HEMTs). In one embodiment, a diode may be used between the gate terminal and the gate of the HEMT. An anode of the diode is coupled to the gate terminal, and a cathode of the diode is coupled to the gate of the transistor. Thus, when the circuit is conducting, the diode is forward biased. Thus, the threshold of the circuit may be a function of the sum of the forward biased on-state voltage of the diode and the threshold voltage of the transistor. This circuit is compared with a conventional circuit in which the diode has a reverse configuration, and specifically, the cathode of the diode is coupled to the gate terminal and the anode is coupled to the gate of the transistor. The threshold of conventional circuits may be a function of the sum of the reverse bias breakdown voltage of the diode and the threshold voltage of the transistor. The new circuits and electronic devices may provide better control over the threshold voltage of the circuit, which is more stable over time. Circuits and electronic devices are well suited for HEMTs and all of the components in the circuits and electronic devices can be integrated into a single die without any additional masking or other processing operations or increasing the total area occupied by the circuits and devices.

In one aspect, an electronic device may include: a channel layer covering the substrate; a barrier layer covering the channel layer; a gate electrode of the transistor, the gate electrode covering the channel layer; a gate terminal; and a component having a threshold voltage. The component is disposed along a current path between the gate terminal and the gate electrode.

In another aspect, an electronic device may include: a channel layer covering the substrate; a barrier layer covering the channel layer; a gate electrode of the first transistor, the gate electrode covering the channel layer; a gate terminal; and a second transistor having a source electrode, a gate electrode, and a drain electrode. A source electrode and a gate electrode of the second transistor are coupled to the gate electrode of the first transistor, and a drain electrode of the second transistor is coupled to the gate terminal.

In another aspect, a circuit may include drain, gate, and source terminals, a transistor, and a diode. The transistor may include a drain, a gate, and a source, where the drain is coupled to the drain terminal and the source is coupled to the source terminal. The diode may have an anode and a cathode, wherein the anode is coupled to the gate terminal and the cathode is coupled to the gate of the transistor.

Fig. 1 includes a circuit 100 according to one embodiment. Circuit 100 includes a source terminal 102, a gate terminal 104, and a drain terminal 106. The circuit 100 includes a transistor 122 having a source, a gate, and a drain. A source is coupled to source terminal 102 and a drain is coupled to drain terminal 106. In one embodiment, the transistor is a HEMT, and in a particular embodiment is an enhancement mode HEMT. Circuit 100 also includes a diode 142 having an anode and a cathode, where the anode is coupled to gate terminal 104 and the cathode is coupled to the gate of transistor 122. Diode 142 may be a schottky diode or a pn junction diode. Although not shown, other components may be used, such as a gate controller to control a gate signal for turning on and off transistor 122, a gate driver to provide a sufficient gate voltage to operate transistor 122, another suitable component, or any combination thereof.

Diode 142 helps to increase the voltage at gate terminal 104 required to turn on circuit 100. In one non-limiting embodiment, diode 142 may double the voltage required at gate terminal 104 to turn on transistor 122. When the transistor 122 is turned on and off infrequently, charge may accumulate between the diode 142 and the gate of the transistor 122 after the transistor 122 is turned on. When transistor 122 is off, source terminal 102 and gate terminal 104 may be at substantially the same voltage. The accumulated charge causes the diode 142 to be reverse biased because the cathode of the diode 142 is at a higher voltage than the anode of the diode 142. The accumulated charge may be dissipated as a leakage current through the diode 142.

In another embodiment, transistor 122 may be turned on and off more frequently. Accordingly, charge accumulated between the diode 142 and the gate of the transistor 122 may need to dissipate more quickly. Fig. 2 and 3 include embodiments in which additional components may be used to help dissipate the accumulated charge without significantly disturbing the circuit operation when transistor 122 is turned on.

In fig. 2, circuit 200 includes diodes 142 and 252 in a back-to-back diode configuration. In particular, diode 252 includes an anode and a cathode, where the anode of diode 252 is coupled to the cathode of diode 142 and the cathode of diode 252 is coupled to the anode of diode 142. In one embodiment, the on-state forward bias voltage (a particular type of threshold voltage) of diode 252 is less than the threshold voltage of transistor 122. Accordingly, the charge accumulated at the node between the gate of the transistor 122 and the diodes 142 and 252 can be made smaller than the threshold voltage of the transistor 122. Similar to diode 142, diode 252 may be a schottky diode, a pn junction diode, or a junction barrier diode. Junction barrier diodes are a mixture of patterned schottky diodes and pn junction diodes and are well known structures for reducing the turn-on voltage in SiC diodes. Diodes 142 and 252 may be of the same type (e.g., both schottky diodes or both pn junction diodes) or different types (e.g., one diode is a schottky diode and the other diode is a pn junction diode), and may have the same or different characteristics (e.g., on-state forward bias voltage, area, resistance between gate electrode and terminal of the diode (e.g., cathode of diode 142 and anode of diode 252)).

In fig. 3, circuit 300 includes a transistor 352 having a source, a gate, and a drain. A gate and source of transistor 352 are coupled to the cathode of diode 142, and a drain of transistor 352 is coupled to the anode of diode 142. In one embodiment, the transistor 352 is a depletion transistor, and in a particular embodiment is a depletion HEMT. In another embodiment (not shown), the transistor 352 may be an enhancement mode transistor. When an enhancement transistor is used for the transistor 352, the threshold voltage of the transistor 352 is less than the threshold voltage of the transistor 122. Accordingly, the charge accumulated at the gate of the transistor 122 and the node between the diode 142 and the transistor 352 can be made smaller than the threshold voltage of the transistor 122.

Fig. 4 includes a circuit 400 that includes a series-connected set of diodes 441, 442, 443, … … 44 n. As used herein, the branch of circuit 400 that includes diodes 441 through 44n is referred to as the accumulation branch, and the branch of circuit 400 that includes diode 252 is referred to as the dissipation branch. In this embodiment, the additional diodes along the accumulation branch help to further increase the voltage at the gate terminal 104 for the turn-on transistor 122. Within the accumulation branch, a skilled person may perform circuit simulations to determine the number of diodes that should be connected in series within the accumulation branch. Fig. 4 also shows diode 252, and in another embodiment, transistor 352 may be used in the dissipation branch in place of diode 252. In a specific embodiment, more than one diode or transistor may be used in the dissipation branch. When more than one component is used within a dissipation branch, such components may be connected in parallel with each other. Thus, the number of diodes in the accumulation branch may be different from the number of components in the dissipation branch.

Attention is now directed to the physical structure and process flow for implementing the previously described circuits. The focus will be on the circuits in fig. 1 to 3. After reading this description, the skilled person will be able to modify the physical components and the process flow in order to implement the circuit as shown in fig. 4.

Fig. 5 includes a cross-sectional view of a portion of a workpiece 500 where a HEMT is being formed. Referring to the foregoing circuit, the workpiece 500 includes a portion 522 in which a transistor structure corresponding to the transistor 122 is formed, and a portion 542 in which a feature structure corresponding to a feature between the gate terminal 104 and the gate of the transistor 122 is formed. The workpiece may include a substrate 502, a buffer layer 504, a channel layer 506, a barrier layer 508, a gate electrode 524, and a semiconductor member 544. The substrate 502 may comprise silicon, sapphire (single crystal Al)₂O₃) Silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga)₂O₃) Spinel (MgAl)₂O₄) Another suitable substantially single crystal material, etc. Specific materials and crystals along the major surfaceThe choice of bulk orientation can be chosen according to the composition of the overlying semiconductor layer.

The buffer layer 504 may comprise a III-N material, and in a particular embodiment, Al_aGa_(1-a)N, wherein a is more than or equal to 0 and less than or equal to 1. The composition of the buffer layer 504 may depend on the composition of the channel layer 506 and the design operating voltage of the HEMT. The composition of the buffer layer 504 may vary depending on the thickness such that the buffer layer 504 has a relatively higher aluminum content closer to the substrate 502 and a relatively higher gallium content closer to the channel layer 506. In a particular embodiment, the cation (metal atom) content in the buffer layer 504 near the substrate 502 may be 10 atomic% to 100 atomic% Al, the remainder being Ga, and the cation content in the buffer layer 504 near the channel layer 506 may be 0 atomic% to 50 atomic% Al, the remainder being Ga. In another embodiment, the buffer layer 504 may include a plurality of films. The buffer layer 504 may have a thickness in the range of about 1 micron to 5 microns.

The channel layer 506 may include a semiconductor base material such as Al_zGa_(1-z)N, wherein 0 ≦ z ≦ 0.1 and has a thickness in a range of about 20nm to 4000 nm. In a specific embodiment, the channel layer 506 is a GaN layer (z ═ 0). The channel layer 506 may be inadvertently doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. In one embodiment, the concentration of acceptor (when the carrier is an electron) or donor (when the carrier is a hole) can be kept as low as reasonably possible.

In a particular embodiment, when Metal Organic Chemical Vapor Deposition (MOCVD) is used to form channel layer 506, the acceptor may comprise a source gas (e.g., Ga (CH))₃)₃) Carbon (c) of (a). In a particular embodiment, the lowest trap concentration is desired, but may be limited by growth or deposition conditions and precursor purity. Thus, as channel layer 506 grows, some carbon may become incorporated, and such carbon may lead to unintentional doping. The carbon content can be controlled by controlling deposition conditions such as deposition temperature and flow rate. In one embodiment, the carrier impurity concentration of the channel layer 506 is greater than 0 atoms/cm³And at most 1X 10¹⁴Atom/cm³At most 1X 10¹⁵Atom/cm³Or at most 1X 10¹⁶Atom/cm³. In a specific embodiment, the carrier impurity concentration is 1X 10¹³Atom/cm³To 1X 10¹⁶Atom/cm³Within the range of (1).

In one embodiment, the channel layer 506 has a thickness of at least 50 nm. When the thickness is less than 50nm, 2DEG may be more difficult to generate, maintain, or both. In another embodiment, the channel layer 506 has a thickness of at most 5000 nm. In a particular embodiment, a thickness in the range of 50nm to 300nm may provide a sufficiently thick channel layer 506 to allow proper generation and maintenance of a 2DEG, and still obtain a reasonable on-state resistance (R)_DSON)。

The barrier layer 508 may comprise a III-V semiconductor material, such as a III-N semiconductor material. In a particular embodiment, the barrier layer may comprise Al_bIn_cGa_(1-b-c)N, wherein 0<b is less than or equal to 1 and c is less than or equal to 0 and less than or equal to 0.3. Barrier layer 508 may comprise a single film or multiple films. When barrier layer 508 includes multiple films, the aluminum content may remain substantially the same or increase with increasing distance from channel layer 506. As the aluminum content in barrier layer 508 increases, the thickness of barrier layer 508 may be relatively thin. In one embodiment, barrier layer 508 has a thickness of at least 10nm, and in another embodiment, barrier layer 508 has a thickness of at most 150 nm. In a particular embodiment, barrier layer 508 has a thickness in the range of 20nm to 90 nm.

In one embodiment, the gate electrode 524 and the semiconductor member 544 may be formed of a gate electrode layer. The resulting transistor structure (corresponding to transistor 122) is an enhancement mode HEMT. The gate electrode 524 and the semiconductor member 544 may include a p-type semiconductor material. In a particular embodiment, the gate electrode 524 and the semiconductor member 544 may comprise p-type GaN. The p-type dopant may comprise Mg, Zn, Cd, etc. The gate electrode 524 and the semiconductor member 544 may have a thickness in a range of 10nm to 300 nm. In another embodiment, the gate electrode 524 and the semiconductor member 544 may be thicker, if needed or desired.

The skilled artisan may select one of several techniques to form the gate electrode 524 and the semiconductor component 544 from the gate electrode layer. For example, a gate electrode layer may be deposited on barrier layer 508, or a patterned layer may be formed prior to forming the gate electrode layer. In one embodiment, the patterned layer may include a sacrificial layer that is removed after forming the gate electrode 524 and the semiconductor member 544. In another embodiment (not shown), the patterned layer may include access regions for source and drain electrodes formed over the channel layer. In this embodiment, the patterned layer may remain within the completed transistor structure. For simplicity, gate electrode 524 and semiconductor member 544 are shown as being located on barrier layer 508. In another embodiment, gate electrode 524, semiconductor member 544, or both may be recessed within barrier layer 508 or contact channel layer 506. After reading this description, skilled artisans will be able to select the process techniques for forming the gate electrode 524 and the semiconductor member 544 to meet the needs or desires of a particular application. In further embodiments (not shown), a spacer layer is formed between channel layer 506 and barrier layer 508.

Fig. 6 includes an exemplary layout of an electronic device. Portion 522 includes gate electrode 524 and portion 542 includes semiconductor component 544. It should be noted that the gate electrode 524 and the semiconductor member 544 are spaced apart and do not contact each other. The semiconductor member 544 may have a shape corresponding to a gate terminal interconnect, and the semiconductor member 544 may have a portion 644 corresponding to a subsequently formed gate pad and a portion 648 corresponding to a gate runner, where the gate pad and the gate runner are formed at a higher level interconnect to be subsequently formed. The source and drain electrodes have not yet been formed and are therefore not shown in fig. 6.

Fig. 7 includes the workpiece after forming the insulating layer 700, the source and drain electrodes 722, 725, the gate electrode interconnect 724, the gate terminal interconnect 742, and the further interconnect 744. An insulating layer 700 may be formed over barrier layer 508, gate electrode 524, and semiconductor member 544. The insulating layer 700 may include an oxide, nitride, or oxynitride. The insulating layer 700 may have a thickness in the range of 50nm to 500 nm. The insulating layer 700 can be patterned to define contact openings for the source and drain electrodes 722, 726 and the interconnects 724, 742, and 744. In one embodiment, a contact opening may extend through insulating layer 700 and fall on barrier layer 508, gate electrode 524, and semiconductor member 544. In another embodiment, the contact openings for the source and drain electrodes 722, 726 and the interconnect 744 may extend through a portion, but not all, of the thickness of the barrier layer 508, or through the entire thickness of the barrier layer 508 and contact the channel layer 506.

A conductive layer is formed over the insulating layer 700 and within the contact opening. The conductive layer may comprise a single film or multiple films. The conductive layer may include an adhesive film and a barrier film. Such films may comprise Ta, TaSi, Ti, TiW, TiSi, TiN, etc. The conductive layer may further include a conductive film. The body film may comprise Al, Cu, or another material that is more conductive than other films within the conductive layer. In one embodiment, the body film can comprise at least 90 wt.% Al or Cu. The body film can have a thickness at least as thick as the other films within the conductive layer. In one embodiment, the thickness of the body film is in the range of 20nm to 900nm, and in a more specific embodiment, in the range of 50nm to 500 nm. More or fewer films may be used in the conductive layer. The number and composition of the films within the conductive layer may depend on the needs or desires of a particular application. After reading this specification, the skilled person will be able to determine the composition of the conductive layer modulated to suit his device. The conductive layer is patterned to form a source electrode 722 and a drain electrode 726, and interconnects 724, 742, and 744.

The contact openings for the source and drain electrodes 722 and 726 and the interconnect 744 and the contact openings for the interconnects 724 and 742 may be defined using the same process sequence or different process sequences. The source and drain electrodes 722 and 726 and the interconnect 744 and the interconnects 724 and 742 may be formed using the same process sequence or different process sequences. Further, the source and drain electrodes 722 and 726 and the interconnect 744 may be formed at one interconnect level, and the interconnects 724 and 742 may be formed at a different interconnect level. Fig. 8 includes a top view of a portion of the workpiece at this point in the process.

Fig. 9 includes the workpiece after forming the insulating layer 900 and the interconnect 924. The combination of interconnects 744 and 924 corresponds to the node between diode 142 and the gate of transistor 122 in fig. 1-3. Insulating layer 900 includes any of the compositions and thicknesses previously described with respect to insulating layer 700. The insulating layer 900 may have the same composition or a different composition than the insulating layer 700, and the insulating layer 900 may have the same thickness or a different thickness than the insulating layer 700. The insulating layer 900 can be patterned to define via openings for the interconnects 924. A conductive layer is formed over the insulating layer 900 and within the via opening. The conductive layer for the interconnect 924 includes any composition and thickness as previously described with respect to the source and drain electrodes 722, 726 and the interconnects 724, 742, and 744. The conductive layer of interconnect 924 can have the same composition or a different composition than the conductive layer for the underlying electrodes and interconnects 722, 724, 726, 742, and 744, and the conductive layer of interconnect 924 can have the same thickness or a different thickness than the conductive layer for the underlying electrodes and interconnects 722, 724, 726, 742, and 744. The conductive layer is patterned to form interconnects 924.

One or more interconnect levels and passivation layers may be formed over the workpiece. Each interconnect level may include an interlevel dielectric layer and an interconnect. A conductive layer may be used at each interconnect level. The conductive layer may be the same as or different from other conductive layers previously described in this specification. Substantially finished electronic devices have been formed, including enhancement mode HEMTs. The 2DEG910 is discontinuous under the gate electrode 524 and the semiconductor member 544. When an appropriate voltage is applied, the 2DEG becomes continuous, including under the gate electrode 524 and the semiconductor member 544. As will be discussed later in this specification with reference to fig. 12, the threshold voltage for turning on the circuit 100 may be increased to more than 3V.

The structure shown in fig. 9 may be used for the diode 142 and the transistor 122 shown in fig. 1, 2, and 3. The circuits in fig. 2 and 3 include additional components. Fig. 10 shows an exemplary structure that may be used for diode 252. In fig. 10, the semiconductor member 1042 may be formed simultaneously with the semiconductor member 542. The semiconductor member 1042 may be formed during a different process sequence than the gate electrode 524, or at least one operation in the process sequence for forming the gate electrode 524 may be shared with the process sequence for forming the semiconductor member 1042. For example, in order to make the threshold voltage lower than that of the diode including the semiconductor member 1042, the semiconductor member 1042 may be patterned to be narrower than the gate electrode 524. In another embodiment, the semiconductor member 1042 may be formed using a thinner p-type GaN layer than the p-type GaN layer used to form the gate electrode 524. The diode 252 may be formed at the interface of the semiconductor member 1042 and the barrier layer 508.

The interconnection 1052 may be formed simultaneously with the gate terminal interconnection 742. Another portion of interconnect 924 is electrically connected to interconnect 1052 and contacts interconnect 1052. Accordingly, interconnect 1052 may also be part of a node between the anode of diode 252, the cathode of diode 142, and the gate of transistor 122 (see fig. 2). The interconnect 1062 may be formed at the same time as the gate terminal interconnect 742, and the interconnect 1064 may be formed at the same time as the interconnect 924. Although not shown, the interconnect 1064 or possibly another interconnect may be connected to the gate terminal 104. Accordingly, interconnects 742, 1062, and 1064 may be part of a node between gate terminal 104, the cathode of diode 252, and the anode of diode 142.

In another embodiment (not shown), the semiconductor member 1042 may not be present and the interconnect 1052 may contact the barrier layer 508 to form a schottky diode. In this embodiment, the interconnect 1052 may be formed simultaneously with the source electrode 722 and the drain electrode 726. In another embodiment, the interconnect 1052 may be formed of a metal having a lower work function than the source and drain electrodes 722, 726. In further embodiments, junction barrier diodes may be used.

Fig. 11 includes an exemplary transistor structure that may be used for transistor 352 (in fig. 3). In fig. 11, gate electrode 1124 may be formed simultaneously with gate electrode 524. The source electrode 1122 and the drain electrode 1126 may be formed simultaneously with the source electrode 722 and the drain electrode 726. The interconnect 1134 may be formed simultaneously with the gate electrode interconnect 724. The source electrode 1122 and interconnects 1134 and 924 may be part of a node between the gate and source of transistor 352, the cathode of diode 142, and the gate of transistor 122 (see fig. 3). The interconnects 1164 may be formed simultaneously with the interconnects 924. Although not shown, the interconnect 1164 or possibly another interconnect may be connected to the gate terminal 104. Accordingly, the drain electrode 1126 and the interconnects 742 and 1164 may be part of a node between the gate terminal 104, the cathode of the diode 252, and the anode of the diode 142.

For circuits 200 and 300, a gate voltage in the range of-0.5V to-1V may be used to open the circuit and take the voltage on gate electrode 724 of transistor 122 to 0V.

Fig. 12 includes a simulation of the comparison circuit and the circuit 200 in fig. 2. The comparison circuit may be the same as circuit 200 except that diodes 142 and 252 are not present. Thus, the gate terminal 104 is directly connected to the gate of the transistor 122. When the drain current (the current flowing from the drain terminal 106 to the source terminal 102, or Ids) is greater than 0A, the circuit is on. As shown in fig. 12, the threshold voltage (Vth) of the comparator circuit is about 1.5V (voltage difference between the gate terminal 104 and the source terminal 102, or Vgs ≈ 1.5V), and Vth of the circuit 200 is about 3.1V (Vgs ≈ 3.1V). Thus, the addition of diode 142 increases Vth, and in one embodiment, this increase is twice the Vth of the comparison circuit. Fig. 12 also includes a plot of gate current (current flowing from gate terminal 104 to source terminal 102, or Igs) as a function of Vgs. In the range of about 3.1V to 5.3V, the Igs of circuit 200 is lower than the comparison circuit. At higher Vgs, the Igs of both circuits is approximately the same.

Fig. 13 includes a simulation of the circuit 200 in fig. 2 to ensure that the circuit 200 has acceptable performance when Vgs is in the range of-20V to 20V. When Vgs is about 8V, a saturation current of Ids is reached, and for certain simulations, the saturation current is about 0.33A. The skilled person will understand that the actual value of the saturation currentIs a function of the particular transistor structure (e.g., the channel width of the transistor structure) used for transistor 122 and is less affected by the presence or absence of diodes 142 and 252. Igs is about 1 × 10 when Vgs is 10V^-5A, and does not reach 1 × 10 until Vgs reaches about 19V^-3A. Thus, the circuit 200 has acceptable performance when Vgs varies from-20V to 20V.

Embodiments described herein may help provide circuitry that allows for threshold voltage modulation to be tailored to the needs or desires of a particular application. The gate of the enhancement mode transistor may be coupled to one or more diodes that may be used to increase the voltage between the source and gate terminals for conducting the circuit. The geometry and number of the one or more diodes may be designed to achieve a desired threshold voltage of the circuit. The circuit has good drain current characteristics and acceptably low gate current.

In some embodiments, another diode or transistor may be connected in parallel with one or more diodes to facilitate faster dissipation of charge than if such other diodes or transistors were not present. In a particular embodiment, a back-to-back diode configuration may be used. As the gate voltage of the circuit increases, current flows through one or more diodes along the charge accumulation branch to the gate of the enhancement transistor. When the circuit is open, the charge at the gate of the enhancement transistor can dissipate through another diode along the charge dissipation branch of the circuit.

In another particular embodiment, a configuration may include transistors along a dissipating branch of a circuit. The circuit 300 conducts in a manner similar to the back-to-back configuration (circuit 200). When the circuit is open, the voltage on the source and the gate of the transistor is higher than the voltage on the drain. Charge will dissipate through the transistor along the charge dissipation branch of the transistor.

The embodiments described herein provide better control of the threshold voltage of the circuit than conventional circuits having diodes with a reverse configuration (a single diode with the cathode coupled to the gate terminal and the anode coupled to the gate of the enhancement mode transistor). Implementations may also provide a more stable threshold voltage over time for the circuit.

These embodiments are well suited for enhancement mode transistors, and in particular enhancement mode HEMTs. The components of the circuit may be formed on the same die and within or over the same channel layer. In a particular embodiment, components along the conductive path between the gate terminal and the gate of the enhancement mode transistor may be located below the gate pad or gate runner, and therefore, the components do not increase the area occupied by the circuit. The formation of the features does not require any additional masking or other processing operations. Existing masking layers may be modified to provide features of the component.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only, and do not limit the scope of the invention. Implementations may be in accordance with any one or more of the items listed below.