阅读说明：本技术 半导体元件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 李一凡 苏柏青 刘承佳 易延才 蔡纬撰 吴志强 陈俤彬 曾景助 于 2018-07-02 设计创作，主要内容包括：本发明公开一种半导体元件及其制造方法。半导体元件的结构包括:栅极结构设置在基板上。间隙壁设置在所述栅极结构的侧壁,其中所述间隙壁是l-状结构。第一掺杂区域位于所述基板中,在所述栅极结构的两边。第二掺杂区域位于所述基板中,在所述栅极结构的两边,与所述第一掺杂区域重叠。硅化物层设置在所述基板上,且在所述第二掺杂区域内,与所述间隙壁分离一距离。介电层覆盖过所述第二掺杂区域以及具有所述间隙壁的所述栅极结构。(The invention discloses a semiconductor element and a manufacturing method thereof. The structure of the semiconductor element comprises a grid structure arranged on a substrate. Spacers are disposed on sidewalls of the gate structure, wherein the spacers are l-shaped structures. The first doped regions are located in the substrate on both sides of the gate structure. The second doped region is located in the substrate, and is overlapped with the first doped region at two sides of the gate structure. The silicide layer is disposed on the substrate and separated from the spacer by a distance in the second doped region. A dielectric layer covers the second doped region and the gate structure with the spacer.)

1. A structure of a semiconductor device, comprising:

a gate structure disposed on the substrate;

a spacer on a sidewall of the gate structure, wherein the spacer is an l-shaped structure;

first doped regions in the substrate on both sides of the gate structure;

a second doped region in the substrate at both sides of the gate structure, overlapping the first doped region;

a silicide layer disposed on the substrate and in the second doped region, separated from the spacer by a distance; and

and the dielectric layer covers the second doping area and the gate structure with the gap wall.

2. The semiconductor device structure of claim 1, wherein the spacer on the gate structure is silicon nitride or silicon carbonitride.

3. The structure of a semiconductor element according to claim 1, wherein a plurality of the gate structures are provided over the substrate.

4. The semiconductor device structure of claim 1, wherein the gate structure comprises:

a gate insulating layer on the substrate; and

a gate layer on the gate insulating layer, the gate layer being stacked by a plurality of layers.

5. The semiconductor device structure of claim 1, wherein the first doped region in the substrate is used as a lightly doped drain region and the second doped region in the substrate is used as a source/drain region.

6. The semiconductor device structure of claim 1, wherein the silicide layer is nickel silicide, cobalt silicide or titanium silicide, wherein the silicon material of the silicide layer is provided by the substrate separated from the spacer by the distance.

7. The semiconductor device of claim 6, wherein the distance is determined based on a width of a transient spacer temporarily disposed on the spacer of the gate structure after the transient spacer is removed.

8. The structure of claim 1, wherein the dielectric layer is a contact etch stop layer, an inter-layer dielectric layer, or a contact etch stop layer and an inter-layer dielectric layer.

9. A method of manufacturing a semiconductor device, comprising:

forming a gate structure on a substrate;

forming a first gap wall on the side wall of the gate structure;

forming first doped regions in the substrate on both sides of the gate structure;

forming a second spacer on the first spacer and the substrate, wherein the second spacer comprises a liner spacer on the first spacer and an outer spacer on the liner spacer, wherein the liner spacer and the outer spacer are different dielectric materials;

forming second doped regions in the substrate on both sides of the gate structure;

forming a silicide layer on the substrate in the second doped region adjacent to the second spacer;

removing the outer spacer and the liner spacer of the second spacer; and

and forming a dielectric layer to cover the second doped region and the gate structure with the first gap wall.

10. The method of claim 9, wherein the first spacer is a nitride, the liner spacer is a silicon oxide, and the outer spacer is a silicon nitride.

11. The method of manufacturing a semiconductor device according to claim 9, wherein a plurality of the gate structures are formed over the substrate.

12. The method of claim 9, wherein forming the gate structure comprises:

forming a gate insulating layer on the substrate; and

a gate layer is formed on the gate insulating layer, the gate layer being stacked by a plurality of layers.

13. The method as claimed in claim 9, wherein the first doped region in the substrate is used as a lightly doped drain region, and the second doped region in the substrate is used as a source/drain region.

14. The method as claimed in claim 9, wherein the silicide layer is nickel silicide, cobalt silicide or titanium silicide, wherein the silicon material of the silicide layer is provided by the substrate adjacent to the outer spacer of the second spacer.

15. The method as claimed in claim 9, wherein the outer spacer and the liner spacer are sequentially removed according to the etching selectivity of the material, wherein the first spacer remains.

16. The method of manufacturing a semiconductor device according to claim 9, wherein the first spacer is an L-shaped structure different from an L-shaped structure.

17. The method as claimed in claim 9, wherein the dielectric layer is a contact etch stop layer, an inter-layer dielectric layer, or a contact etch stop layer and an inter-layer dielectric layer.

18. The method according to claim 9, wherein the step of forming the second spacer comprises:

forming a substrate layer covering the substrate;

forming an outer dielectric layer covering the substrate layer; and

etching back to remove the outer dielectric layer and the substrate layer, wherein the second spacer is formed by the residual parts of the outer dielectric layer and the substrate layer,

wherein the residual substrate layer is the liner spacer and is an L-shaped structure, and the residual outer dielectric layer is the outer spacer and is located in the horizontal area of the L-shaped structure.

Technical Field

The present invention relates to semiconductor manufacturing technology, and more particularly, to a structure of a semiconductor device and a method for manufacturing the same.

Background

As the size of semiconductor devices is greatly reduced, the density of transistors is also increased. Thus, the spacing between the gates of the transistors is also reduced. The gate may also be a dummy gate during the fabrication process based on the development of gate structure technology. For example, the dummy gate is subsequently removed to form a metal gate structure. In addition, based on the development of transistor structures, a plurality of spacers are formed on the sidewalls of the gate in response to different stages. This in turn further reduces the spacing between the gates.

Further, after the gate structure of the transistor is completed, a Contact Etch Stop Layer (CESL) conformal to the gate structure is formed and an Inter-Layer Dielectric (ILD) Layer is deposited to cover the gate. Wherein the contact etch stop layer further reduces the spacing between the gates. Thus, the space between the gates is small before the deposition of the inter-layer dielectric, which tends to cause voids (seam) between the gates, and thus affects the performance of the semiconductor device.

If the occurrence of voids is reduced by reducing the thickness of the contact etch stop layer, the required tension provided by the contact etch stop layer may be insufficient. Simply reducing the thickness of the contact etch stop layer may cause other problems.

How to reduce the generation probability of voids between gates is one of the factors to be considered in the manufacturing technology.

Disclosure of Invention

The present invention is directed to a structure of a semiconductor device and a method for fabricating the same, which can at least reduce the generation probability of voids between gates.

The invention provides a structure of a semiconductor element, which comprises a grid structure arranged on a substrate. Spacers are disposed on sidewalls of the gate structure, wherein the spacers are l-shaped structures. The first doped regions are located in the substrate on both sides of the gate structure. The second doped region is located in the substrate, and is overlapped with the first doped region at two sides of the gate structure. The silicide layer is disposed on the substrate and separated from the spacer by a distance in the second doped region. A dielectric layer covers the second doped region and the gate structure with the spacer.

In one embodiment, for the structure of the semiconductor device, the spacer on the gate structure is silicon nitride or silicon carbonitride.

In one embodiment, for the structure of the semiconductor device, a plurality of the gate structures are disposed on the substrate.

In one embodiment, for the structure of the semiconductor device, the gate structure includes a gate insulating layer on the substrate and a gate layer on the gate insulating layer, the gate layer being stacked by a plurality of layers.

In one embodiment, for the structure of the semiconductor device, the first doped region in the substrate is used as a lightly doped drain region, and the second doped region in the substrate is used as a source/drain region.

In one embodiment, for the structure of the semiconductor device, the silicide layer is nickel silicide, cobalt silicide or titanium silicide, wherein the silicon material of the silicide layer is provided by the substrate separated from the spacer by the distance.

In one embodiment, for the semiconductor device structure, the distance is determined based on a width of a transient spacer that is transiently disposed on the spacer of the gate structure when the transient spacer is removed.

In one embodiment, for the structure of the semiconductor device, the dielectric layer is a contact etch stop layer, or an inter-layer dielectric layer, or a contact etch stop layer and an inter-layer dielectric layer.

The invention provides a method for manufacturing a semiconductor element, which comprises the step of forming a grid structure on a substrate. And forming a first gap wall on the side wall of the gate structure. First doped regions are formed in the substrate on both sides of the gate structure. Forming a second spacer on the first spacer and the substrate, wherein the second spacer comprises a liner spacer on the first spacer and an outer spacer on the liner spacer, wherein the liner spacer and the outer spacer are different dielectric materials. And forming second doped regions in the substrate at two sides of the gate structure. And forming a silicide layer on the substrate and in the second doping region and adjacent to the second gap wall. Removing the outer spacer and the liner spacer of the second spacer. Forming a dielectric layer to cover the second doped region and the gate structure with the first spacer.

In one embodiment, in the method for manufacturing a semiconductor device, the first spacer is nitride, the liner spacer is silicon oxide, and the outer spacer is silicon nitride.

In one embodiment, for the method of fabricating a semiconductor device, a plurality of gate structures are formed on the substrate.

In one embodiment, for the method of fabricating a semiconductor device, forming the gate structure includes forming a gate insulating layer on the substrate and forming a gate layer on the gate insulating layer, the gate layer being stacked by a plurality of layers.

In one embodiment, for the method of fabricating a semiconductor device, the first doped region in the substrate is used as a lightly doped drain region, and the second doped region in the substrate is used as a source/drain region.

In one embodiment, in the method of fabricating a semiconductor device, the silicide layer is nickel silicide, cobalt silicide or titanium silicide, wherein a silicon material of the silicide layer is provided by the substrate adjacent to the outer spacer of the second spacer.

In one embodiment, for the method of fabricating a semiconductor device, the outer spacer and the liner spacer are sequentially removed according to etch selectivity of material, wherein the first spacer remains.

In one embodiment, for the method of fabricating a semiconductor device, the first spacer is an L-shaped structure, different from an L-shaped structure.

In one embodiment, for the method of fabricating a semiconductor device, the dielectric layer is a contact etch stop layer, or an inter-layer dielectric layer, or a contact etch stop layer and an inter-layer dielectric layer.

In one embodiment, for the method of fabricating a semiconductor device, the step of forming the second spacer includes forming a substrate layer overlying the substrate; forming an outer dielectric layer covering the substrate layer; and etching back to remove the outer dielectric layer and the substrate layer, wherein the residual parts of the outer dielectric layer and the substrate layer form the second gap wall. The residual substrate layer is the liner gap wall and is an L-shaped structure, and the residual outer dielectric layer is the outer gap wall and is positioned in the horizontal area of the L-shaped structure.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor device in accordance with one embodiment of the present invention;

FIGS. 2A-2H are schematic cross-sectional views illustrating a process for fabricating a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view of a semiconductor device including a plurality of gate structures according to an embodiment of the present invention; and

FIG. 4 is a flow chart illustrating a method of fabricating a semiconductor device according to one embodiment of the present invention.

Description of the reference numerals

40: substrate

50: gate structure

Spacer 52

54 inner spacer

56 outer spacer

58 dielectric layer

60 doped region

62 pore space

80 base plate

82 isolation structure

100 gate insulating layer

102 gate layer

104 capping layer

105 nitride layer

106 spacer

108 gate structure

112 lightly doped region

114 lining spacer

116 outer spacer

118 spacer

122 doped region

124 silicide layer

S100, S102, S104, S106, S108, S110, S112, S114

Detailed Description

The present invention relates to a manufacturing technique of a semiconductor device. In response to the requirement of increasing the integration level of the integrated circuit, the size of the semiconductor device can be greatly reduced after the technology development. Transistors are the main components of integrated circuits, and their size is greatly reduced, and the spacing between adjacent transistors is reduced.

In the fabrication of semiconductor devices, as device dimensions shrink significantly, the space that is expected to be filled with dielectric material also shrinks. This makes it easier to create voids (seam) during the deposition of the dielectric material to form the desired dielectric layer.

The invention is illustrated below by means of some examples, but is not limited to the examples.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Referring to fig. 1, in one embodiment, the present invention explores the mechanism by which voids may occur in the semiconductor device as it is scaled down for increased integration. Taking the gate structure of the transistor as an example, a plurality of transistors, such as two adjacent transistors, are formed on the substrate 40. The transistor structure includes a gate structure 50 on a substrate 40. The sidewalls of the gate structure 50 are provided with spacers 56. The spacers 56 include, for example, the inner spacer 52 and the outer spacer 54. Doped regions 60 are formed in the substrate 40 on opposite sides of the gate structure 50 and serve as source and drain regions.

The spacing between two adjacent gate structures 50 is reduced as the overall device size is reduced. A dielectric layer 58 is subsequently deposited overlying the gate structure 50. As such, during subsequent formation of the desired dielectric layer 58 by a deposition process, the spacing between gate structures 50 may be reduced, which may tend to create voids 62 in dielectric layer 58. The dielectric layer 58 is, for example, a contact etch stop layer, or an interlevel dielectric layer, or both.

The occurrence of voids 62 may affect the performance of the device and may even damage the entire transistor device. The present invention observes the occurrence mechanism of voids 62, and explores the void phenomenon to propose an improvement in the art that can at least reduce the occurrence probability of voids 62.

Alternatively, if the dielectric layer 58 is a stack structure including a Contact Etch Stop Layer (CESL) and an inter-layer dielectric (ILD) layer in one embodiment, the contact etch stop layer is formed first on the lower portion to also maintain the tension balance effect, and the ILD layer is subsequently deposited on top of the contact etch stop layer. Thus, the contact etch stop layer further reduces the spacing between the gate structures 50, which makes it easier to form voids 62 during the deposition of the ild layer. If a reduction in the thickness of the contact etch stop layer is used, it may not provide sufficient tension or effectiveness of the etch stop layer, and therefore the contact etch stop layer needs to maintain its predetermined thickness. Also, if the thickness of the contact etch stop layer is too great, voids 62 may form directly within the contact etch stop layer.

That is, after studying the structure of fig. 1, it is observed that the occurrence probability of voids 62 in the subsequently formed dielectric layer 58, whether of a single layer or a multi-layer structure, is increased due to the trend of the reduction of the spacing between the gate structures 50.

The present invention also provides a structure of a semiconductor device and a method for fabricating the same, which at least effectively reduces the probability of voids 62 in the dielectric layer 58.

Fig. 2A to 2H are schematic cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 2A, a single transistor fabrication process is illustrated as an example. In practice, a plurality of transistors are formed on the substrate 80 in a compact manner according to the design requirements. In this embodiment, the substrate 80 may be a silicon substrate, and the substrate 80 may have a corresponding doped well region according to the conductive type of the transistor. The doped well region may be defined by, for example, isolation structure 82. The substrate 80 described below refers to a region for forming a transistor, and is not limited to a specific doping pattern.

A gate structure 108 is formed on the substrate 80. The gate structure 108 is a stack of multiple material layers, including the gate insulating layer 100, the gate layer 102 and the cap layer 104, and a nitride layer 105 may be added between the gate layer 102 and the cap layer 104 according to actual requirements. The gate layer 102 may be a single layer or a stacked layer structure depending on the actual design. The gate structure 108 of the present invention, as in the embodiment of fig. 2A, is a multi-layer stacked structure. The gate structure 108 of the present invention is not limited to a particular internal structure.

A spacer 106 is formed on the sidewalls of the gate structure 108. The structure of the spacer 106 is a vertical l-shaped structure with no lateral extension at its bottom. The spacer 106 may be made of silicon nitride (SiN) or silicon carbonitride (SiCN), for example. The spacer 106 is actually retained at the end while maintaining a relatively thin thickness.

Referring to fig. 2B, lightly doped regions 112 are formed in the substrate 80 at both sides of the gate structure 108, for example, using an implantation process. The lightly doped region 112 functions as a Lightly Doped Drain (LDD) region, for example.

Referring to fig. 2C, a thicker spacer 118 may be formed on the sidewalls of the gate structure 108 during fabrication based on the design of the transistor structure. Spacers 118 are formed on spacers 106. The spacers 118 are formed in response to the subsequent formation of desired structures on the substrate 80 and are not used as actual spacers for the gate structure 108. That is, the spacers 118 need to be removed in a subsequent manufacturing process. In order to remove the spacer 118 and leave the spacer 106, the spacer 118 includes, for example, the liner spacer 114 and the outer spacer 116. Liner spacer 114 is a different dielectric material than spacer 106. In general, for example, the spacers 106 are silicon nitride or silicon carbonitride, the liner spacers 114 are silicon oxide, and the outer spacers 116 are silicon nitride.

In one embodiment, spacers 118 are formed by first forming a liner layer overlying substrate 80 and then forming an outer dielectric layer overlying the liner layer in a generally known manner. And then, etching back to remove the outer dielectric layer and the substrate layer. The remaining portions of the outer dielectric layer and the substrate layer constitute the spacers 118. The remaining substrate layer is liner spacer 114, which is an L-shaped structure. The remaining outer dielectric layer forms outer spacers 116 in the horizontal regions of the L-shaped structure.

Referring to fig. 2D, a doped region 122 is formed in the substrate 80 on both sides of the gate structure 108 as a source region and a drain region by using the shielding of the spacers 106 and 118. As is generally known, the doped region 122 overlaps and covers the lightly doped region 112.

Referring to fig. 2E, a Silicide (Silicide) layer 124 is formed on the exposed surface of the substrate 80 in the doped region 122 by using the spacers 106 and 118. The material of the silicide layer 124 is, for example, but not limited to, nickel silicide, cobalt silicide, or titanium silicide. The silicon material of the silicide layer 124 is provided by the substrate 80. Due to the shielding of the spacers 118, the silicide layer 124 may be separated from the spacers 106 by a predetermined distance, which depends on the width of the spacers 118.

Referring to fig. 2F, the spacers 118 are removed as described above, and thus the outer spacers 116 are removed first by an etching process. Referring to fig. 2G, the liner spacers 114 may then be removed with the spacers 106 remaining by the etch selectivity of the etchant to the material. In one embodiment, the spacers 106 are nitride and the liner spacers 114 are oxide. Thus, the spacers 106 may be substantially completely retained, and the spacers 118, including the outer spacers 116 and the liner spacers 114, are sequentially removed.

In accordance with an embodiment of the present invention, the liner spacers 114 and the outer spacers 116 in the spacers 118 are removed, leaving only the spacers 106. The material of the spacers 106 is nitride, so that a thinner thickness can be maintained to sufficiently achieve the isolation of the spacers from the gate structure 108. The spacers 106 are vertical L-shaped structures, as opposed to L-shaped structures. And liner spacer 114 is an L-shaped structure with a lateral region, for example, on substrate 80. The outer spacer 116 is located in the lateral region of the liner spacer 114. The thickness of the spacers 118 determines the distance between the silicide layer 124 and the spacers 106.

Referring to fig. 2H, the formation of other structures may then continue, such as by depositing a dielectric layer 126. In one embodiment, the dielectric layer 126 is a Contact Etch Stop Layer (CESL) or an inter-layer dielectric (ILD)

As described in fig. 2G, since the spacers 118 including the liner spacers 114 are removed, the distance between two adjacent gate structures is widened, and the dielectric layer 126 is easier to cover the space between two adjacent gate structures, thereby reducing the occurrence of voids.

Fig. 3 is a schematic cross-sectional view illustrating a semiconductor device including a plurality of gate structures according to an embodiment of the invention. Referring to fig. 3, there are typically a plurality of transistors on the substrate 80. As transistor dimensions shrink, the spacing between gate structures 108 also shrinks. But since the spacers of the gate structures 108 are thin structures, the space between the gate structures 108 may be increased. When the subsequent dielectric layer 126 is deposited on the gate structures 108, it is easier to fill the space between the gate structures 108, thereby reducing the occurrence of voids 62 as shown in fig. 1. The dielectric layer 126 may be a single layer or a multi-layer structure as described above, and will not be described herein.

The invention can also be described in terms of a method of manufacturing a semiconductor component. FIG. 4 is a flow chart illustrating a method of fabricating a semiconductor device according to one embodiment of the present invention.

Referring to fig. 4 in conjunction with fig. 2A-2H, a method of fabricating a semiconductor device, for example, includes a plurality of steps. In step S100, a gate structure 108 is formed on a substrate. In step S102, a first spacer 106 is formed on the sidewall of the gate structure. In step S104, first doped regions 112 are formed in the substrate 80 on both sides of the gate structure 108. In step S106, a second spacer 118 is formed on the first spacer 106 and the substrate 80, wherein the second spacer 118 includes a liner spacer 114 on the first spacer 106 and an outer spacer 116 on the liner spacer 114, wherein the liner spacer 114 and the outer spacer 116 are different dielectric materials. In step S108, second doped regions 122 are formed in the substrate 80 on both sides of the gate structure 108. In step S110, a silicide layer 124 is formed on the substrate 80 within the second doped region 122 adjacent to the second spacer 118. In step S112, the outer spacer 116 and the liner spacer 114 of the second spacer 118 are removed. In step S114, a dielectric layer 126 is formed covering the second doped region 122 and the gate structure 108 having the spacers 106.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.