阅读说明：本技术 沟槽mosfet及其制造方法 (Trench MOSFET and method of manufacturing the same ) 是由 张新 李巍 叶俊 于 2018-07-03 设计创作，主要内容包括：本申请提供了一种沟槽MOSFET及其制造方法。所述沟槽MOSFET包括：具有第一导电类型的衬底；形成于所述衬底之上的具有第一导电类型的外延层,所述外延层的掺杂浓度低于所述衬底的掺杂浓度；形成于所述外延层中的沟槽；形成于所述沟槽下方的具有第二导电类型的埋层；填充在所述沟槽内的栅结构,所述栅结构包括屏蔽栅电极、位于所述屏蔽栅电极上方的控制栅电极及包覆所述屏蔽栅电极及填充在所述控制栅电极侧部的介质层；形成于所述外延层中的具有第二导电类型的体区；形成于所述外延层中且位于所述体区上方的具有第一导电类型的源区,所述源区的掺杂浓度大于所述体区的掺杂浓度。(The application provides a trench MOSFET and a method of manufacturing the same. The trench MOSFET includes: a substrate having a first conductivity type; an epitaxial layer having a first conductivity type formed over the substrate, the epitaxial layer having a doping concentration lower than a doping concentration of the substrate; a trench formed in the epitaxial layer; a buried layer of a second conductivity type formed below the trench; the gate structure is filled in the groove and comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode and a dielectric layer which coats the shielding gate electrode and is filled at the side part of the control gate electrode; a body region of a second conductivity type formed in the epitaxial layer; and the source region is formed in the epitaxial layer and positioned above the body region and has the first conductivity type, and the doping concentration of the source region is greater than that of the body region.)

1. A trench MOSFET, comprising:

a substrate (1) having a first conductivity type;

an epitaxial layer (2) of a first conductivity type formed over the substrate (1), the doping concentration of the epitaxial layer (2) being lower than the doping concentration of the substrate (1);

a trench (3) formed in the epitaxial layer (2);

a buried layer (4) of a second conductivity type formed below the trench (3);

the gate structure (5) is filled in the trench (3), and the gate structure (5) comprises a shielding gate electrode (501), a control gate electrode (502) positioned above the shielding gate electrode (501), a dielectric layer (503) covering the shielding gate electrode (501) and filled at the side part of the control gate electrode (502);

a body region (6) of a second conductivity type formed in the epitaxial layer (2);

a source region (7) of the first conductivity type formed in the epitaxial layer (2) and located above the body region (6), the source region (7) having a doping concentration greater than a doping concentration of the body region (6).

2. The trench MOSFET of claim 1, wherein the buried layer (4) has a depth in the range of 1 μm to 3 μm, and the buried layer (4) has an impurity implanted dose in the range of 4e12 ions/cm²6e12 ions/cm²。

3. The trench MOSFET of claim 1 wherein the epitaxial layer (2) comprises a first epitaxial layer (201) and a second epitaxial layer (202) formed over the first epitaxial layer (201), the first epitaxial layer (201) having a doping concentration less than the second epitaxial layer (202).

4. The trench MOSFET of claim 3, wherein a distance between a bottom of the buried layer (4) and an upper surface of the substrate (1) is smaller than a distance between a bottom of the second epitaxial layer (202) and the upper surface of the substrate (1).

5. The trench MOSFET of claim 1 further comprising a plurality of implanted regions (10) of the first conductivity type in the epitaxial layer (2) and below the body region (6), the plurality of implanted regions (10) being arranged from top to bottom and being located at the side of the shield gate electrode (501), the implanted regions (10) having a doping concentration greater than the doping concentration of the epitaxial layer (2).

6. The trench MOSFET of claim 5 wherein the difference between the distance between the bottom of the lowermost implant region (10) and the upper surface of the substrate (1) and the distance between the bottom of the shield gate electrode (501) and the upper surface of the substrate (1) is in the range-0.2 μm to 0.2 μm, and the difference between the distance between the top of the uppermost implant region (10) and the upper surface of the substrate (1) and the distance between the top of the shield gate electrode (501) and the upper surface of the substrate (1) is in the range-0.2 μm to 0.2 μm.

7. The trench MOSFET of claim 5 wherein the plurality of implanted regions (10) are uniformly spaced.

8. A trench MOSFET according to claim 5, characterized in that the doping concentration of a plurality of the implanted regions (10) is the same.

9. The trench MOSFET of claim 5 wherein the plurality of implanted regions (10) have doping concentrations that increase or decrease sequentially from top to bottom.

10. A method of fabricating a trench MOSFET, the method comprising:

preparing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is less than that of the substrate;

preparing a groove in the epitaxial layer;

preparing a buried layer having a second conductivity type under the trench;

preparing a gate structure in the trench, wherein the gate structure comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and a dielectric layer filled at the side part of the control gate electrode;

preparing a body region having a second conductivity type in the epitaxial layer;

preparing a source region with the first conductivity type above the body region in the epitaxial layer, wherein the doping concentration of the source region is greater than that of the body region.

11. The method of claim 10, wherein the buried layer has a depth in the range of 1 μm to 3 μm, and the impurity is implanted into the buried layer at a dose of 4e12 ions/cm²6e12 ions/cm²。

12. The method of manufacturing a trench MOSFET of claim 10, further comprising, prior to preparing a trench in the epitaxial layer:

preparing a plurality of injection regions with a first conductivity type in the epitaxial layer, wherein the injection regions are arranged from top to bottom and are positioned on the side part of the shielding gate electrode, the doping concentration of the injection regions is greater than that of the epitaxial layer, and the injection regions are positioned below the body region.

13. The method of claim 12, wherein a difference between a distance between a bottom of the lowermost implant region and an upper surface of the substrate and a distance between a bottom of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm, and a difference between a top of the uppermost implant region and the upper surface of the substrate and a distance between a top of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm.

Technical Field

The application relates to the technical field of semiconductors, in particular to a trench MOSFET and a manufacturing method thereof.

Background

In the development of the semiconductor field, for a medium-high voltage MOSFET (Metal-Oxide-semiconductor field-Effect Transistor), it is important to improve the breakdown voltage and reduce the specific on-resistance of the MOSFET.

SGTMOS (shielded gate trench MOS) includes a substrate, an epitaxial layer located over the substrate, and a device structure located within the epitaxial layer. In the prior art, the doping concentration of an epitaxial layer of the SGTMOS is constant, the withstand voltage of the SGTMOS can be improved by reducing the doping concentration of the epitaxial layer, but the specific on-resistance (on-resistance in unit area) of the SGTMOS is increased at the same time. Therefore, the conventional SGTMOS cannot further increase the withstand voltage of the SGTMOS without increasing the specific on-resistance, and cannot decrease the specific on-resistance of the SGTMOS without decreasing the withstand voltage.

Disclosure of Invention

According to a first aspect of embodiments of the present application, there is provided a trench MOSFET, comprising:

a substrate having a first conductivity type;

an epitaxial layer having a first conductivity type formed over the substrate, the epitaxial layer having a doping concentration lower than a doping concentration of the substrate;

a trench formed in the epitaxial layer;

a buried layer of a second conductivity type formed below the trench;

the gate structure is filled in the groove and comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and a dielectric layer filled at the side part of the control gate electrode;

a body region of a second conductivity type formed in the epitaxial layer;

and the source region is formed in the epitaxial layer and positioned above the body region and has the first conductivity type, and the doping concentration of the source region is greater than that of the body region.

In one embodiment of the present application, the buried layer has a depth ranging from 1 μm to 3 μm, and the impurity is implanted into the buried layer at a dose ranging from 4e12 ions/cm²6e12 ions/cm²。

In one embodiment of the present application, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer formed over the first epitaxial layer, the first epitaxial layer having a doping concentration less than the second epitaxial layer.

In one embodiment of the present application, a distance between a bottom of the buried layer and an upper surface of the substrate is smaller than a distance between a bottom of the second epitaxial layer and the upper surface of the substrate.

In an embodiment of the present application, the trench MOSFET further includes a plurality of injection regions having the first conductivity type, which are located in the epitaxial layer and below the body region, the injection regions are arranged from top to bottom and located at the side of the shield gate electrode, and a doping concentration of the injection regions is greater than a doping concentration of the epitaxial layer.

In one embodiment of the present application, a difference between a distance between a bottom of the lowermost implant region and an upper surface of the substrate and a distance between a bottom of the shield gate electrode and the upper surface of the substrate ranges from-0.2 μm to 0.2 μm, and a difference between a distance between a top of the uppermost implant region and the upper surface of the substrate and a distance between the top of the shield gate electrode and the upper surface of the substrate ranges from-0.2 μm to 0.2 μm.

In one embodiment of the present application, the plurality of implant regions are uniformly spaced.

In one embodiment of the present application, the doping concentration of a plurality of the implanted regions is the same.

In an embodiment of the present application, the doping concentrations of the plurality of implantation regions sequentially increase or sequentially decrease from top to bottom.

According to a second aspect of embodiments of the present application, there is provided a method of manufacturing a trench MOSFET, the method including:

preparing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is less than that of the substrate;

preparing a groove in the epitaxial layer;

preparing a buried layer having a second conductivity type under the trench;

preparing a gate structure in the trench, wherein the gate structure comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and a dielectric layer filled at the side part of the control gate electrode;

preparing a body region having a second conductivity type in the epitaxial layer;

preparing a source region with the first conductivity type above the body region in the epitaxial layer, wherein the doping concentration of the source region is greater than that of the body region.

In one embodiment of the present application, the buried layer has a depth ranging from 1 μm to 3 μm, and the impurity is implanted into the buried layer at a dose of 4e12 ions/cm²6e12 ions/cm²。

In one embodiment of the present application, before preparing the trench in the epitaxial layer, the manufacturing method further includes:

preparing a plurality of injection regions with a first conductivity type in the epitaxial layer, wherein the injection regions are arranged from top to bottom and are positioned on the side part of the shielding gate electrode, the doping concentration of the injection regions is greater than that of the epitaxial layer, and the injection regions are positioned below the body region.

In one embodiment of the present application, a difference between a distance between a bottom of the lowermost implant region and an upper surface of the substrate and a distance between a bottom of the shield gate electrode and the upper surface of the substrate ranges from-0.2 μm to 0.2 μm, and a difference between a distance between a top of the uppermost implant region and the upper surface of the substrate and a distance between the top of the shield gate electrode and the upper surface of the substrate ranges from-0.2 μm to 0.2 μm.

According to the trench MOSFET and the manufacturing method thereof provided by the embodiment of the application, the buried layer is formed below the trench, so that the electric field in the height range of the buried layer can be increased, and the withstand voltage of the trench MOSFET is improved. Meanwhile, when the voltage resistance of the MOSFET is fixed, the doping concentration of the epitaxial layer can be increased by forming the buried layer below the trench, so that the specific on-resistance of the trench MOSFET is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another trench MOSFET according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a trench MOSFET structure without a buried layer and the electric field distribution;

fig. 6 is a schematic diagram of a structure and an electric field distribution of a trench MOSFET according to an embodiment of the present application;

fig. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application.

The reference numerals in the figures are respectively:

1. a substrate;

2. an epitaxial layer;

201. a first epitaxial layer;

202. a second epitaxial layer;

3. a trench;

4. a buried layer;

5. a gate structure;

501. a shield gate electrode;

502. a control gate electrode;

503. a dielectric layer;

6. a body region;

7. a source region;

8. a source electrode;

9. a drain electrode;

10. an implantation region;

11. an insulating layer;

12. and (6) contacting the holes.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "plurality" includes two, and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The shielded gate trench MOSFET and the manufacturing method thereof in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following examples and embodiments can be supplemented or combined with each other without conflict.

Fig. 1 to 4 are schematic structural diagrams of a trench MOSFET according to an embodiment of the present disclosure, fig. 5 is a schematic structural diagram and an electric field distribution diagram of a trench MOSFET according to an embodiment of the present disclosure without a buried layer and an implant region, and fig. 6 is a schematic structural diagram and an electric field distribution diagram of a trench MOSFET according to an embodiment of the present disclosure. The trench MOSFET provided by the embodiment of the application is a medium-voltage (100V-200V) MOSFET.

In the embodiment of the present application, the direction pointing from the substrate to the epitaxial layer is upward.

Referring to fig. 1 to 4, a trench MOSFET provided in an embodiment of the present application includes:

a substrate 1 having a first conductivity type;

an epitaxial layer 2 having a first conductivity type formed over a substrate 1, the doping concentration of the epitaxial layer 2 being lower than the doping concentration of the substrate 1;

a trench 3 formed in the epitaxial layer 2;

a buried layer 4 having a second conductivity type formed under the trench 3;

the gate structure 5 is filled in the trench 3, and the gate structure 5 comprises a shielded gate electrode 501, a control gate electrode 502 positioned above the shielded gate electrode 501, a dielectric layer 503 covering the shielded gate electrode 501 and filled at the side part of the control gate electrode 502;

a body region 6 having the second conductivity type formed in the epitaxial layer 2;

a source region 7 of the first conductivity type formed in the epitaxial layer 2 and located above the body region 6, the doping concentration of the source region 7 being greater than the doping concentration of the body region 6;

a source electrode 8; and

and a drain electrode 9.

The trench MOSFET provided in the embodiment of the present application can increase the electric field within the height range of the buried layer 4 by forming the buried layer 4 below the trench 3. As can be seen from a comparison of fig. 5 and 6, by filling the buried layer 4 in the bottom of the trench 3, when the trench MOSFET is subjected to a reverse voltage, the electric field in the range of the height of the buried layer 4 is significantly increased, and therefore, the withstand voltage of the trench MOSFET can be improved. Meanwhile, by forming the buried layer 4, the doping concentration of the epitaxial layer 2 can be increased while the withstand voltage of the MOSFET is kept constant, so as to reduce the specific on-resistance of the trench MOSFET. And for a trench MOSFET with certain withstand voltage, the depth of the trench 3 can be reduced by forming the buried layer 4 below the trench 3, and the process difficulty of forming the trench 3 in the epitaxial layer 2 is reduced.

In one embodiment of the present application, the buried layer 4 has a thickness in a range of 1 μm to 3 μm, and may be, for example, 2 μm, and the implantation dose of the impurity when forming the buried layer 4 is in a range of 4e12 ions/cm²6e12 ions/cm²For example, it may be 5e12 ions/cm². The specific concentration and thickness of the buried layer 4 are determined according to the magnitude of the breakdown voltage of the trench MOSFET and the doping concentration of the epitaxial layer 2.

In one embodiment of the present application, the dielectric layer 503 of the gate structure 5 includes a field oxide layer covering the shield gate electrode 501 and a gate oxide layer filled on the side of the control gate electrode 502. The field oxide layer on the bottom and side of the shield gate electrode 501 may be formed by an oxidation deposition process or a thermal oxidation deposition process, and the field oxide layer between the shield gate electrode 501 and the control gate electrode 502 may be formed by a high density plasma chemical vapor deposition (HDP) process.

In an embodiment of the present application, the trench MOSFET further includes a plurality of implanted regions 10 of the first conductivity type formed in the epitaxial layer 2 and located below the body region 6, the plurality of implanted regions 10 are arranged from top to bottom and located at the side of the shield gate electrode 501, and a doping concentration of the implanted regions 10 is greater than a doping concentration of the epitaxial layer 2. By forming a plurality of implanted regions 10 in the epitaxial layer 2 at the side portions of the shield gate electrode 501, the doping concentration of the epitaxial layer 2 at different positions of the portion within the height range of the shield gate electrode 501 can be adjusted. When the trench MOSFET is subjected to a reverse voltage, the charge balance is more ideal, so that the actual electric field distribution is closer to a perfect rectangular distribution. And the doping concentration of the implantation region 10 is greater than that of the epitaxial layer 2, the specific on-resistance of the trench MOSFET can be reduced.

Further, the difference between the distance between the bottom of the lowermost implanted region 10 and the upper surface of the substrate 1 and the distance between the bottom of the shield gate electrode 501 and the upper surface of the substrate 1 is in the range of-0.2 μm to 0.2 μm, and the difference between the distance between the top of the uppermost implanted region 10 and the upper surface of the substrate 1 and the distance between the top of the shield gate electrode 501 and the upper surface of the substrate 1 is in the range of-0.2 μm to 0.2 μm. This arrangement allows the plurality of implant regions 10 to more effectively adjust the magnitude of the electric field within the height range of the shield gate electrode 501.

In one embodiment of the present application, the number of implant regions 10 is two to five, preferably three.

In one embodiment of the present application, the plurality of implant regions 10 are uniformly spaced. The plurality of injection regions 10 are arranged at intervals, and compared with continuous distribution, the manufacturing process is simple and the manufacturing cost is lower. In other embodiments, the plurality of implant regions 10 may be distributed continuously.

In one embodiment of the present application, the doping concentration of the plurality of implant regions 10 is the same.

In another embodiment of the present application, the doping concentrations of the plurality of implantation regions 10 are sequentially increased or sequentially decreased from top to bottom. In other embodiments, the doping concentration of the plurality of implantation regions 10 may also be irregularly distributed.

In one embodiment of the present application, the epitaxial layer 2 includes a first epitaxial layer 201 and a second epitaxial layer 202 located on the first epitaxial layer 201, and the first epitaxial layer 201 has a doping concentration less than that of the second epitaxial layer 202. A plurality of implant regions 10 are formed in the second epitaxial layer 202, the implant regions 10 having a doping concentration greater than the doping concentration of the second epitaxial layer 202.

In one embodiment of the present application, the distance between the bottom of the buried layer 4 and the upper surface of the substrate 1 is smaller than the distance between the bottom of the second epitaxial layer 202 and the upper surface of the substrate 1. When the trench MOSFET bears reverse voltage resistance, the buried layer 4 can simultaneously adjust the electric fields within the height ranges of the first epitaxial layer 201 and the second epitaxial layer 202, so that the electric fields within the height ranges of the first epitaxial layer 201 and the second epitaxial layer 202 can be respectively increased, and the electric field distribution within the height ranges of the first epitaxial layer 201 and the second epitaxial layer 202 is closer to a rectangle, thereby improving the voltage resistance of the trench MOSFET. Since the shield gate electrode 501 can also adjust the electric field distribution within the height range of the second epitaxial layer 202, the doping concentration of the second epitaxial layer 202 can be greater than the doping concentration of the first epitaxial layer 201, thereby reducing the specific on-resistance of the trench MOSFET. And the doping concentration of the first epitaxial layer 201 is low, so that the electric field can not drop too fast in the first epitaxial layer 201, and the high voltage resistance of the trench MOSFET is ensured.

In one embodiment of the present application, the trench MOSFET further includes an insulating layer 11 over the control gate electrode 502 and the source region. Contact holes 12 are formed in the insulating layer 11, the body region 6, and the source region 7. The source electrode 8 includes a metal layer over the insulating layer 11 and a metal filled in the contact hole 12.

In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. That is, the substrate 1 is an N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, the buried layer 4 is a P-type buried layer, the body region 6 is formed by P-type doping, the source region 7 is formed by N-type doping, and the implantation region 10 is formed by N-type doping.

In the trench MOSFET provided in the embodiment of the present application, the doping concentrations and thicknesses of the buried layer 4, the first epitaxial layer 201, the second epitaxial layer 202, and the implanted region 10 may be determined according to the requirement of the trench MOSFET for withstanding voltage.

According to the trench MOSFET provided by the embodiment of the application, the buried layer 4 is formed below the trench 3, and the plurality of injection regions 10 which are vertically arranged are formed on the side of the shield gate electrode 501, so that the electric field in the height range of the buried layer 4 and the electric field in the height range of the shield gate electrode 501 are increased, the electric field distribution in the height range of the epitaxial layer 2 is closer to a rectangle, and the withstand voltage of the trench MOSFET can be improved; through setting up epitaxial layer 2 and including first epitaxial layer 201 and second epitaxial layer 202, the doping concentration of second epitaxial layer 202 is greater than the doping concentration of first epitaxial layer 201, and the concentration of pouring into area 10 is greater than the doping concentration of second epitaxial layer 202, then can reduce trench MOSFET's specific on resistance, and the withstand voltage of first epitaxial layer can not descend too fast simultaneously, has further guaranteed trench MOSFET is withstand voltage. As can be seen from comparing fig. 5 and fig. 6 again, after the buried layer 4 and the plurality of implantation regions 10 are added on the basis of the first epitaxial layer 201 and the second epitaxial layer 202, when the trench MOSFET is subjected to a reverse voltage, the charge balance is more desirable, and the electric field in the height range of the shield gate electrode 501 is significantly increased, so that the withstand voltage of the trench MOSFET can be improved, and the electric field distribution in the height range of the epitaxial layer 2 is closer to the ideal rectangular distribution. In addition, the doping concentration of the implantation region 10 is greater than that of the epitaxial layer 2, so that the specific on-resistance of the trench MOSFET can be reduced, and finally, the trench MOSFET has low specific on-resistance while having a sufficiently high withstand voltage capability.

Fig. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application. Referring to fig. 7, the preparation method includes the following steps 201 to 211.

In step 201, an epitaxial layer having a first conductivity type is prepared on a substrate having the first conductivity type, and the doping concentration of the epitaxial layer is less than that of the substrate.

In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.

In one embodiment of the present application, an N-type doped semiconductor may be used as a substrate, and an N-type semiconductor may be deposited on the substrate by an epitaxial growth method to form an epitaxial layer.

In one embodiment of the present application, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer located above the first epitaxial layer, the first epitaxial layer having a doping concentration less than the second epitaxial layer. The first epitaxial layer may be formed on the substrate by epitaxial growth, and then the second epitaxial layer may be formed on the first epitaxial layer by epitaxial growth.

In step 202, a plurality of implantation regions of the first conductivity type are formed in the epitaxial layer from top to bottom, and the doping concentration of the implantation regions is greater than that of the epitaxial layer.

Wherein a plurality of implant regions are formed in the second epitaxial layer.

In one embodiment of the present application, a difference between a distance between a bottom of a lowermost implanted region and an upper surface of the substrate and a distance between a bottom of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm, and a difference between a distance between a top of an uppermost implanted region and the upper surface of the substrate and a distance between the top of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm.

In one embodiment of the present application, a plurality of N-type implant regions are formed in the second epitaxial layer by implanting impurities through an annealing process.

In one embodiment of the present application, the number of implanted regions is two to five, and may be three, for example.

In one embodiment of the present application, the plurality of implant regions are uniformly spaced. Compared with continuous distribution, the multiple injection regions are arranged at intervals, the manufacturing process is simple, and the manufacturing cost is lower. In other embodiments, the plurality of implant regions may be distributed continuously.

In one embodiment of the present application, the doping concentrations of the plurality of implanted regions are the same.

In another embodiment of the present application, the doping concentrations of the plurality of implanted regions sequentially increase or sequentially decrease from top to bottom. In other embodiments, the doping concentrations of the plurality of implanted regions may be irregularly distributed.

In step 203, trenches are prepared in the epitaxial layer.

In one embodiment of the present application, trenches are formed in the epitaxial layer by photolithography and etching techniques.

In step 204, a buried layer having a second conductivity type is prepared under the trench.

In one embodiment of the present application, a P-type buried layer of a certain distribution region is formed at the bottom of a trench by implanting impurities and performing an annealing process. Under the action of the P-type buried layer, the charge balance of the corresponding epitaxial layer part is more ideal, the electric field distribution is close to rectangular distribution, and therefore the withstand voltage of the trench MOSFET is increased.

In one embodiment of the present application, the implantation dose of the impurity when forming the P-type buried layer is in the range of 4e12 ions/cm²6e12 ions/cm²The thickness of the P-type buried layer ranges from 1 mu m to 3 mu m.

In step 205, a gate structure is formed in the trench, where the gate structure includes a shield gate electrode, a control gate electrode located above the shield gate electrode, a dielectric layer covering the shield gate electrode and filling the dielectric layer on the side of the control gate electrode, and the shield gate electrode is located on the side of the plurality of injection regions.

In one embodiment of the present application, a difference between a distance between a bottom of a lowermost implanted region and an upper surface of the substrate and a distance between a bottom of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm, and a difference between a distance between a top of an uppermost implanted region and the upper surface of the substrate and a distance between the top of the shield gate electrode and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm.

In one embodiment of the present application, the dielectric layer covering the shield gate electrode is a field oxide layer, and the dielectric layer filled at the side portion of the control gate electrode is a gate oxide layer.

In one embodiment of the present application, field oxide layers are formed on sidewalls of a bottom and a lower side of a trench through an oxidation deposition process or a thermal oxidation deposition process, a shield gate electrode is formed through a deposition of polysilicon and an etching technique, a field oxide layer is formed over the shield gate electrode through a high density plasma chemical vapor deposition (HDP) and an etching technique, a gate oxide layer is formed on sidewalls of an upper side of the trench through the thermal oxidation deposition process, and a control gate electrode is formed over the field oxide layer through the deposition of polysilicon and the etching technique.

In step 206, body regions of the second conductivity type are prepared in the epitaxial layer over the plurality of implanted regions.

In one embodiment of the present application, a P-type body region is formed in the second epitaxial layer by implanting impurities through an annealing process. The P-type body region is arranged at intervals with the uppermost injection region.

In step 207, a source region of the first conductivity type is formed in the epitaxial layer over the body region, the source region having a doping concentration greater than a doping concentration of the body region.

In one embodiment of the present application, an N-type source region is formed on an upper portion of a body region by implanting impurities through an annealing process.

In step 208, an insulating layer is prepared over the control gate electrode and the source region.

In one embodiment of the present application, an insulating layer is formed over the trench and the source region by chemical vapor deposition.

In step 209, contact holes are made in the insulating layer, body regions, and source regions.

In one embodiment of the present application, contact holes are formed in the insulating layer, the body region, and the source region by photolithography and etching techniques.

In step 210, a source is prepared in the contact hole and over the insulating layer.

In one embodiment of the present application, the contact hole is filled with a metal and a metal layer is formed over the insulating layer by metal sputtering, the metal in the contact hole and the metal layer over the insulating layer constituting the source.

In step 211, a drain is fabricated below the substrate.

In one embodiment of the present application, the drain electrode is formed by a metal evaporation process.

According to the preparation method of the trench MOSFET, the buried layer is formed below the trench, the plurality of injection regions which are vertically distributed are formed on the side portion of the shielding gate electrode, the epitaxial layer is arranged to comprise the first epitaxial layer and the second epitaxial layer, the electric field in the trench height range and the electric field in the shielding gate electrode height range are increased, the electric field distribution in the epitaxial layer height range is closer to a rectangle, the voltage resistance of the trench MOSFET is effectively improved, and meanwhile the reduction of the specific on resistance is not limited. In addition, the doping concentration of the second epitaxial layer is larger than that of the first epitaxial layer, and the concentration of the injection region is larger than that of the second epitaxial layer, so that the specific on-resistance of the trench MOSFET can be reduced, meanwhile, the withstand voltage of the first epitaxial layer cannot be reduced too fast, the withstand voltage of the trench MOSFET is further ensured, and finally, the trench MOSFET is ensured to have high enough withstand voltage capability and lower specific on-resistance.

Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.