阅读说明：本技术 一种晶振校准方法和系统 (Crystal oscillator calibration method and system ) 是由 胡阳 张鹏 张艳 周戌初 王英微 于 2019-10-14 设计创作，主要内容包括：本发明提供一种晶振校准方法,包含步骤：S1、转换接收串行参考脉冲信号为并行参考脉冲信号；S2、根据并行参考脉冲信号,对晶振输出时钟信号的频差进行监测,得到N个频差值；S3、筛选N个频差值,根据筛选后的频差值计算得到频差调整值,当频差调整值大于第一频差阈值进入S4,当频差调整值大于第二频差阈值且小于第一频差阈值进入S5,当频差调整值小于第二频差阈值结束晶振校准；S4、根据频差调整值,通过开环调整DA模块的输入值,进入S6；S5、根据频差调整值,通过闭环调整DA模块的输入值,进入S6；S6、根据M路并行参考脉冲信号对晶振输出时钟信号的频差进行一次监测,得到一个频差值,用该频差值更新N个频差值,进入S3。(The invention provides a crystal oscillator calibration method, which comprises the following steps: s1, converting the received serial reference pulse signal into a parallel reference pulse signal; s2, monitoring the frequency difference of the clock signal output by the crystal oscillator according to the parallel reference pulse signal to obtain N frequency difference values; s3, screening N frequency difference values, calculating to obtain a frequency difference adjustment value according to the screened frequency difference values, entering S4 when the frequency difference adjustment value is larger than a first frequency difference threshold value, entering S5 when the frequency difference adjustment value is larger than a second frequency difference threshold value and smaller than the first frequency difference threshold value, and finishing crystal oscillator calibration when the frequency difference adjustment value is smaller than the second frequency difference threshold value; s4, adjusting the input value of the DA module through open loop according to the frequency difference adjustment value, and entering S6; s5, adjusting the input value of the DA module through a closed loop according to the frequency difference adjustment value, and entering S6; s6, monitoring the frequency difference of the clock signal output by the crystal oscillator once according to the M paths of parallel reference pulse signals to obtain a frequency difference value, updating the N frequency difference values by using the frequency difference value, and entering S3.)

1. A crystal oscillator calibration method, comprising the steps of:

s1, receiving a path of serial reference pulse signal, sampling the serial reference pulse signal according to a clock signal output by a crystal oscillator, converting the serial reference pulse signal into M paths of parallel reference pulse signals which are respectively a first path of parallel reference pulse signal to an Mth path of parallel reference pulse signal;

s2, monitoring the frequency difference of the clock signal output by the crystal oscillator for N times according to the M paths of parallel reference pulse signals to obtain N frequency difference values delta F_i，i∈[1,N](ii) a Wherein N is the set total number of monitoring times;

s3, screening the N frequency difference values, and calculating according to the screened frequency difference values to obtain a frequency difference adjustment value; when the frequency difference adjustment value is larger than a preset first frequency difference threshold value, entering S4; when the frequency difference adjustment value is greater than a preset second frequency difference threshold and less than the first frequency difference threshold, entering S5; when the frequency difference adjusting value is smaller than the second frequency difference threshold value, the clock signal output by the crystal oscillator reaches the required precision, and the crystal oscillator calibration is finished; wherein the second frequency offset threshold is less than the first frequency offset threshold;

s4, adjusting the input value of the DA module through open loop according to the frequency difference adjustment value, and outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceeding to S6;

s5, adjusting the input value of the DA module through a phase-locked loop filter in a closed loop mode according to the frequency difference adjusting value, and outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceeding to S6;

s6, monitoring the frequency difference of the clock signal output by the crystal oscillator once according to the M paths of parallel reference pulse signals to obtain a frequency difference value, and updating the N frequency difference values by using the frequency difference value; proceed to S3.

2. The crystal oscillator calibration method according to claim 1, wherein the step S2 specifically includes:

s21, monitoring the M paths of parallel reference pulse signals, and recording a numerical value M when the M paths of parallel reference pulse signals are monitored to have a first pulse from the current time_0,iResetting the counter; wherein m is_0,i∈[1,M]，m_0,iIndicating that the first pulse monitored in the ith monitoring belongs to the m-th pulse₀A channel parallel reference pulse signal; i is the number of monitoring times, i belongs to [1, N ∈]N is setTotal number of monitoring of (1);

s22, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s23, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M_1,i(ii) a Wherein m is_1,i∈[1,M]，m_1,iIndicating that the second pulse monitored in the ith monitoring belongs to the m-th pulse₁A channel parallel reference pulse signal;

s24, calculating to obtain delta F_i＝cnt+(m_1,i-m_0,i) (ii) a Wherein cnt is the count value of the counter at the occurrence of said second pulse, Δ F_iThe frequency difference value obtained by the ith monitoring is obtained.

3. The crystal oscillator calibration method according to claim 2, wherein the step S3 specifically includes:

s31, calculating the average frequency difference value delta F at the moment k_mean(k) Frequency deviation root mean square delta F_std(k) Wherein

S32, setting a frequency difference screening threshold value delta F_thWhen frequency difference value Δ F_iSatisfies Δ F_i-ΔF_mean(k)-ΔF_std(k)>ΔF_thDeleting the frequency difference value delta F_i，i∈[1,N]；

S33, calculating the frequency difference adjustment value at the k momentIs Δ F₁～ΔF_NAverage value of all the frequency difference values which are not deleted;

s34, when

4. The crystal oscillator calibration method according to claim 3, wherein the step S4 specifically comprises:

s41, calculating

s42, calculating

s43, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is the input value of the DA module at time k, V_DA(k-1) is an input value of the DA module at the k-1 moment;

s44, outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceed to S6.

5. The crystal oscillator calibration method according to claim 3, wherein the step S5 specifically comprises:

s51, adjusting the frequency difference at the time k

Wherein c is₁,c₂,c₃Pll _ x (k), pll _ y (k), pll _ z (k) are loop parameters that are intermediate to the computation of the PLL filter at time k,

pll_z(k)＝pll_z(k-1)+pll_y(k)；

s52, calculating

s53, calculating delta V_DA(k)＝K_kX pll _ out (k), whereinΔV_DA(k) Adjusting the input value of the DA module at the time k; k_kThe ratio of the voltage-controlled terminal voltage value of the crystal oscillator at the moment k to the frequency of a clock signal output by the crystal oscillator;

s54, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is the input value of the DA module at time k, V_DA(k-1) is an input value of the DA module at the k-1 moment;

s55, outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceed to S6.

6. The crystal oscillator calibration method according to claim 1, wherein the step S6 specifically includes:

s61, monitoring the M paths of parallel reference pulse signals, and recording a numerical value M when the M paths of parallel reference pulse signals are monitored to have a first pulse from the current time₀Resetting the counter; wherein m is₀∈[1,M]，m₀Indicating that said first pulse belongs to the m-th pulse₀A channel parallel reference pulse signal;

s62, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s63, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M₁(ii) a Wherein m is₁∈[1,M]，m₁Indicates that the second pulse belongs to the m-th pulse₁A channel parallel reference pulse signal;

s64, calculating the frequency difference Δ F ═ cnt + (m) of the monitoring₁-m₀) (ii) a Wherein cnt is a count value of the counter at the time of the second pulse;

s65 using DeltaF_i+1Updating Δ F_i，i∈[1,N-1](ii) a Updating Δ F with Δ F_N(ii) a Obtaining N updated frequency difference values delta F₁～ΔF_N(ii) a Proceed to S3.

7. A crystal oscillator calibration system for implementing the crystal oscillator calibration method according to any one of claims 1 to 6, comprising: the device comprises a reference pulse generation module, a high-precision pulse measurement unit, a frequency difference monitoring unit, a frequency difference screening unit, a DA module and a crystal oscillator;

the reference pulse generating module is used for generating a path of serial reference pulse signals;

the high-precision pulse measuring unit is connected with the reference pulse generating module and the crystal oscillator output end and is used for sampling the reference pulse signal according to a clock signal output by the crystal oscillator and converting the one path of serial reference pulse signal into M paths of parallel reference pulse signals;

the frequency difference monitoring unit is connected with the high-precision pulse measuring unit and the crystal oscillator output end and is used for measuring the frequency difference value of the output clock signal of the crystal oscillator according to the M paths of parallel reference pulse signals;

the frequency difference screening unit is connected with the frequency difference monitoring unit and used for screening the frequency difference value and calculating to generate a frequency difference adjusting value according to the screened frequency difference value;

the adjusting module is connected between the input end of the DA module and the frequency difference screening unit and used for correcting the input value of the DA module according to the frequency difference adjusting value;

the DA module generates a corresponding analog quantity voltage signal according to the input value of the DA module;

and the crystal oscillator voltage control end is connected with the output end of the DA module, and the crystal oscillator generates a corresponding clock signal according to the analog quantity voltage signal output by the DA module.

8. The crystal oscillator calibration system of claim 7, wherein the adjustment module comprises:

the open-loop adjusting unit is connected between the frequency difference screening module and the DA module, and corrects an input value of the DA module according to the frequency difference value adjusting value by adopting an open-loop adjusting method;

and the closed-loop adjusting unit is connected between the frequency difference screening module and the DA module, and corrects the input value of the DA module according to the frequency difference adjusting value by adopting a closed-loop adjusting method.

Technical Field

The invention relates to the field of digital communication, in particular to a crystal oscillator calibration method and a crystal oscillator calibration system.

Background

The frequency standard is the heart of the time-domain equipment, and as the requirements on inter-station synchronization and time keeping of the time-domain equipment are increased, the requirements on the frequency standard for the time-domain equipment are also higher and higher. In the past, most of time-series equipment is configured with a high-stability quartz crystal frequency standard, and the single quartz crystal frequency standard cannot meet the requirement on occasions with high-precision requirements due to the problems of limitation of accuracy, requirement of a long starting preheating process and the like. Therefore, the combo frequency standard should be generated. The combined frequency standard is a frequency standard with different performance advantages, and an electronic circuit is adopted to combine the frequency standard with better performance indexes than a single frequency standard, namely a clock training technology. For example, time-domain equipment has used a standard frequency signal output by a rubidium atomic frequency standard to lock a high-short-stability quartz crystal frequency standard, so that the output signal has both high-frequency accuracy and good short-term frequency stability. The combined frequency standard is adopted under the condition that the existing frequency standard can not meet the comprehensive requirement of time system equipment on standard frequency signal indexes. The method can exert the advantages of different frequency standards in combination in one or some indexes, such as good frequency stability of quartz crystal frequency standard below second, high accuracy of cesium atom frequency standard, good frequency stability of hydrogen atom frequency standard above 10s, and the like. In recent years, another combination has been developed, that is, a frequency standard is combined with a precision frequency calibration receiver, and the frequency of a local frequency standard is calibrated by using a received standard time frequency signal, so that the accuracy of the local frequency standard is kept high. Such as a GPS disciplined quartz crystal oscillator, a GPS disciplined rubidium clock, etc. It is known that the output frequency of the quartz crystal frequency standard has a large aging rate due to the influence of crystal aging and the like, and the reproducibility is poor. The reproducibility of the rubidium atom frequency standard is the worst of the atom frequency standards, and the drift rate is also the largest. The combined frequency standard is used for receiving standard time frequency signals of GPS, GLONASS (Global NAVIGATION System SATELLITE SYSTEM), Beidou of China, long waves and the like, and the frequency of the local frequency standard tracks the signals so as to reduce the influence of reproducibility, aging or drift on the frequency standard. Currently, along with the development and application of GPS technology, a disciplined clock technology for controlling a local oscillator by using the excellent characteristics of GPS is also intensively studied and widely used. Other systems capable of providing high-precision time and frequency sources, such as GLONASS in Russia, Beidou in China, long wave and the like, cannot be widely applied due to respective reasons.

The existing literature researches a high-precision crystal oscillator calibration method. Document 1 (Xue Yicleng, Gong Rong, Liu Zeng Jun, Zhen Xiang Wei, GNSS-based crystal oscillation discipline method analysis [ J ]. Global positioning System, 2017,4(42):38-42.) provides a plurality of crystal oscillation discipline filtering methods, and compares the short stability and long stability precision which can be achieved by various methods. However, the simulation test results are only given by a plurality of methods, and the long taming time reaches the hour level. The long-term stability of the adaptive control model and the augmented least square algorithm of the OCXO discipline system proposed in the document 2 (Wang hong Jiang, Wang Ling, Huang Wen De, Liu Shi, OCXO high-precision time maintenance adaptive correction algorithm [ J ]. sensor and micro system, 2018,4(37): 132) can reach 3 x 10-11 orders, but the problem of too long convergence time exists. Patent 1 (design of crystal oscillator fast discipline and maintenance algorithm, CN201710399454, 2017) provides a crystal oscillator fitting, tracking and maintenance algorithm, which can make the frequency accuracy of the crystal oscillator reach the magnitude of 1.71e-11, and has the lock losing maintenance function, but has the problem of long discipline time, and cannot meet the requirement of fast calibration. Patent 2 (a crystal oscillator taming method and system based on SOPC technology, CN 201609614, 2016) proposes a crystal oscillator taming system based on SOPC technology, which has the functions of phase compensation, aging temperature compensation, etc., but does not mention the calibration time required for the calibration accuracy achieved by the method.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a quick calibration method for a voltage-controlled crystal oscillator.

In order to achieve the above object, the present invention provides a crystal oscillator calibration method, comprising:

s1, receiving a path of serial reference pulse signal, sampling the serial reference pulse signal according to a clock signal output by a crystal oscillator, converting the serial reference pulse signal into M paths of parallel reference pulse signals which are respectively a first path of parallel reference pulse signal to an Mth path of parallel reference pulse signal;

s2, monitoring the frequency difference of the clock signal output by the crystal oscillator for N times according to the M paths of parallel reference pulse signals to obtain N frequency difference values delta F_i，i∈[1,N](ii) a Wherein N is the set total number of monitoring times;

s3, screening the N frequency difference values, and calculating according to the screened frequency difference values to obtain a frequency difference adjustment value; when the frequency difference adjustment value is larger than a preset first frequency difference threshold value, entering S4; when the frequency difference adjustment value is greater than a preset second frequency difference threshold and less than the first frequency difference threshold, entering S5; when the frequency difference adjusting value is smaller than the second frequency difference threshold value, the clock signal output by the crystal oscillator reaches the required precision, and the crystal oscillator calibration is finished; wherein the second frequency offset threshold is less than the first frequency offset threshold;

s4, adjusting the input value of the DA module through open loop according to the frequency difference adjustment value, and outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceeding to S6;

s5, adjusting the input value of the DA module through a phase-locked loop filter in a closed loop mode according to the frequency difference adjusting value, and outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceeding to S6;

s6, monitoring the frequency difference of the clock signal output by the crystal oscillator once according to the M paths of parallel reference pulse signals to obtain a frequency difference value, and updating the N frequency difference values by using the frequency difference value; proceed to S3.

The step S2 specifically includes:

s21, monitoring the M paths of parallel reference pulse signals and starting from the current timeWhen the first pulse of the M paths of parallel reference pulse signals is monitored, the numerical value M is recorded_0,iResetting the counter; wherein m is_0,i∈[1,M]，m_0,iIndicating that the first pulse monitored in the ith monitoring belongs to the m-th pulse₀A channel parallel reference pulse signal; i is the number of monitoring times, i belongs to [1, N ∈]N is the set total monitoring times;

s22, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s23, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M_1,i(ii) a Wherein m is_1,i∈[1,M]，m_1,iIndicating that the second pulse monitored in the ith monitoring belongs to the m-th pulse₁A channel parallel reference pulse signal;

s24, calculating to obtain delta F_i＝cnt+(m_1,i-m_0,i) (ii) a Wherein cnt is the count value of the counter at the occurrence of said second pulse, Δ F_iThe frequency difference value obtained by the ith monitoring is obtained.

Step S3 specifically includes:

s31, calculating the average frequency difference value delta F at the moment k_mean(k) Frequency deviation root mean square delta F_std(k) Wherein

S32, setting a frequency difference screening threshold value delta F_thWhen frequency difference value Δ F_iSatisfies Δ F_i-ΔF_mean(k)-ΔF_std(k)>ΔF_thDeleting the frequency difference value delta F_i，i∈[1,N]；

S33, calculating the frequency difference adjustment value at the k moment

Is Δ F₁～ΔF_NAverage value of all the frequency difference values which are not deleted;

s34, when

If the frequency difference is larger than the preset first frequency difference threshold, the step S4 is entered; when in use

If the frequency difference is larger than a preset second frequency difference threshold and smaller than the first frequency difference threshold, entering S5; when in use

When the frequency difference is smaller than the second frequency difference threshold value, the clock signal output by the crystal oscillator reaches the required precision, and the crystal oscillator calibration is finished; wherein the second frequency offset threshold is less than the first frequency offset threshold.

The step S4 specifically includes:

s41, calculating

Represents the conversion ratio at time k;

s42, calculating

Wherein

ΔV_DA(k) Adjusting the input value of the DA module at the time k; k_kThe ratio of the voltage-controlled terminal voltage value of the crystal oscillator at the moment k to the frequency of a clock signal output by the crystal oscillator;

s43, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is the input value of the DA module at time k, V_DA(k-1) is an input value of the DA module at the k-1 moment;

s44, outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceed to S6.

The step S5 specifically includes:

s51, adjusting the frequency difference at the time k

Obtaining an output of the PLL filter at time k as an input of the PLL filter

Wherein c is₁,c₂,c₃Pll _ x (k), pll _ y (k), pll _ z (k) are loop parameters that are intermediate to the computation of the PLL filter at time k,

pll_z(k)＝pll_z(k-1)+pll_y(k)；

s52, calculating

Represents the conversion ratio at time k;

s53, calculating delta V_DA(k)＝K_kX pll _ out (k), wherein

ΔV_DA(k) Adjusting the input value of the DA module at the time k; k_kThe ratio of the voltage-controlled terminal voltage value of the crystal oscillator at the moment k to the frequency of a clock signal output by the crystal oscillator;

s54, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is the input value of the DA module at time k, V_DA(k-1) is an input value of the DA module at the k-1 moment;

s55, outputting a corresponding clock signal by the crystal oscillator according to the analog voltage signal output by the DA module; proceed to S6.

The step S6 specifically includes:

s61, monitoring the M paths of parallel reference pulse signals, and recording a numerical value M when the M paths of parallel reference pulse signals are monitored to have a first pulse from the current time₀Resetting the counter; wherein m is₀∈[1,M]，m₀Indicating that said first pulse belongs to the m-th pulse₀A channel parallel reference pulse signal;

s62, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s63, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M₁(ii) a Wherein m is₁∈[1,M]，m₁Indicates that the second pulse belongs to the m-th pulse₁A channel parallel reference pulse signal;

s64, calculating the frequency difference Δ F ═ cnt + (m) of the monitoring₁-m₀) (ii) a Wherein cnt is a count value of the counter at the time of the second pulse;

s65 using DeltaF_i+1Updating Δ F_i，i∈[1,N-1](ii) a Updating Δ F with Δ F_N(ii) a Obtaining N updated frequency difference values delta F₁～ΔF_N(ii) a Proceed to S3.

A crystal oscillator calibration system is used for realizing the crystal oscillator calibration method of the invention, and comprises the following steps: the device comprises a reference pulse generation module, a high-precision pulse measurement unit, a frequency difference monitoring unit, a frequency difference screening unit, a DA module and a crystal oscillator;

the reference pulse generating module is used for generating a path of serial reference pulse signals;

the high-precision pulse measuring unit is connected with the reference pulse generating module and the crystal oscillator output end and is used for sampling the reference pulse signal according to a clock signal output by the crystal oscillator and converting the one path of serial reference pulse signal into M paths of parallel reference pulse signals;

the frequency difference monitoring unit is connected with the high-precision pulse measuring unit and the crystal oscillator output end and is used for measuring the frequency difference value of the output clock signal of the crystal oscillator according to the M paths of parallel reference pulse signals;

the frequency difference screening unit is connected with the frequency difference monitoring unit and used for screening the frequency difference value and calculating to generate a frequency difference adjusting value according to the screened frequency difference value;

the adjusting module is connected between the input end of the DA module and the frequency difference screening unit and used for correcting the input value of the DA module according to the frequency difference adjusting value;

the DA module generates a corresponding analog quantity voltage signal according to the input value of the DA module;

and the crystal oscillator voltage control end is connected with the output end of the DA module, and the crystal oscillator generates a corresponding clock signal according to the analog quantity voltage signal output by the DA module.

The adjusting module comprises:

the open-loop adjusting unit is connected between the frequency difference screening module and the DA module, and corrects an input value of the DA module according to the frequency difference value adjusting value by adopting an open-loop adjusting method;

and the closed-loop adjusting unit is connected between the frequency difference screening module and the DA module, and corrects the input value of the DA module according to the frequency difference adjusting value by adopting a closed-loop adjusting method.

Compared with the prior art, the method and the device have the advantages that the reference pulse signal generated by the reference pulse generation module is used as a reference, the frequency of the crystal oscillator is quickly calibrated in a mode of combining open-loop adjustment and closed-loop adjustment, the accuracy and the stability of the clock signal output by the crystal oscillator are improved, and the influence of aging and temperature change of the crystal oscillator on the accuracy of the clock signal output by the crystal oscillator is reduced.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:

FIG. 1 is a flow chart of a crystal oscillator calibration method according to the present invention;

FIG. 2 is a block diagram of a crystal alignment system according to an embodiment of the present invention;

FIG. 3 is a block diagram of a PLL filter circuit according to an embodiment of the present invention;

in the figure:

1. a reference pulse generation module; 2. a high-precision pulse measurement unit; 3. a frequency difference monitoring unit; 4. a frequency difference screening unit; 51. an open loop adjustment unit; 52. a closed loop adjustment unit; 6. a DA module; 7. crystal oscillation;

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to achieve the above object, the present invention provides a crystal oscillator calibration method, as shown in fig. 1, including steps S1-S6:

and S1, receiving one path of serial reference pulse signal, sampling the serial reference pulse signal according to a clock signal output by a crystal oscillator, and converting the serial reference pulse signal into M paths of parallel reference pulse signals. The first path of parallel reference pulse signal to the Mth path of parallel reference pulse signal are respectively.

In the application embodiment of the invention, a navigation receiver is adopted to generate a serial reference pulse signal, and the crystal oscillator 7 is a voltage-controlled crystal oscillator with the frequency of 100 MHz.

In an embodiment of the present invention, M is 8, a sampling frequency of the serial reference pulse is 800MHz, and a sampling precision can reach 1.25 ns.

S2, monitoring the frequency difference of the clock signal output by the crystal oscillator for N times according to the M paths of parallel reference pulse signals to obtain N frequency difference values delta F_i，i∈[1,N](ii) a Wherein N is the set total number of monitoring times;

the step S2 specifically includes:

s21, monitoring the M paths of parallel reference pulse signals from the current time when monitoringWhen the first pulse of the M paths of parallel reference pulse signals is detected, the value M is recorded_0,iResetting the counter; wherein m is_0,i∈[1,M]，m_0,iIndicating that the first pulse monitored in the ith monitoring belongs to the m-th pulse₀A channel parallel reference pulse signal; i is the number of monitoring times, i belongs to [1, N ∈]N is the set total monitoring times;

s22, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s23, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M_1,i(ii) a Wherein m is_1,i∈[1,M]，m_1,iIndicating that the second pulse monitored in the ith monitoring belongs to the m-th pulse₁A channel parallel reference pulse signal;

s24, calculating to obtain delta F_i＝cnt+(m_1,i-m_0,i) (ii) a Wherein cnt is the count value of the counter at the occurrence of said second pulse, Δ F_iThe frequency difference value obtained by the ith monitoring is obtained.

S3, screening the N frequency difference values, and calculating according to the screened frequency difference values to obtain a frequency difference adjustment value; when the frequency difference adjustment value is larger than a preset first frequency difference threshold value, entering S4; when the frequency difference adjustment value is greater than a preset second frequency difference threshold and less than the first frequency difference threshold, entering S5; when the frequency difference adjustment value is smaller than the second frequency difference threshold value, the clock signal output by the crystal oscillator reaches the required precision, and the calibration of the crystal oscillator 7 is finished; wherein the second frequency offset threshold is less than the first frequency offset threshold;

step S3 specifically includes:

s31, calculating the average frequency difference value delta F at the moment k_mean(k) Frequency deviation root mean square delta F_std(k) Wherein

S32, setting a frequency difference screening threshold value delta F_thWhen frequency difference value Δ F_iSatisfies Δ F_i-ΔF_mean(k)-ΔF_std(k)>ΔF_thDelete the sameFrequency difference value delta F_i，i∈[1,N]；

S33, calculating the frequency difference adjustment value at the k momentIs Δ F₁～ΔF_NAverage value of all the frequency difference values which are not deleted;

s34, when

If the frequency difference is larger than the preset first frequency difference threshold, the step S4 is entered; when in use

If the frequency difference is larger than a preset second frequency difference threshold and smaller than the first frequency difference threshold, entering S5; when in use

When the frequency difference is smaller than the second frequency difference threshold value, the clock signal output by the crystal oscillator reaches the required precision, and the crystal oscillator calibration is finished; wherein the second frequency offset threshold is less than the first frequency offset threshold.

S4, adjusting the input value of the DA module 6 through open loop according to the frequency difference adjustment value, and outputting a corresponding clock signal by the crystal oscillator 7 according to the analog voltage signal output by the DA module 6; proceeding to S6;

the step S4 specifically includes:

s41, calculating

Represents the conversion ratio at time k;

s42, calculating

Wherein

ΔV_DA(k) Adjusting the input value of the DA module at the time k; k_kThe ratio of the voltage-controlled terminal voltage value of the crystal oscillator at the moment k to the frequency of a clock signal output by the crystal oscillator;

s43, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is an input value, V, of the DA module 6 at time k_DA(k-1) is an input value of the DA module 6 at the k-1 moment;

s44, the crystal oscillator 7 outputs a corresponding clock signal according to the analog voltage signal output by the DA module 6; proceed to S6.

S5, adjusting the input value of the DA module 6 through a phase-locked loop filter in a closed loop mode according to the frequency difference adjustment value (a circuit diagram of the phase-locked loop filter is shown in figure 3), and outputting a corresponding clock signal by the crystal oscillator 7 according to the analog voltage signal output by the DA module 6; proceeding to S6;

the step S5 specifically includes:

s51, adjusting the frequency difference at the time kObtaining an output of the PLL filter at time k as an input of the PLL filter

Wherein c is₁,c₂,c₃Pll _ x (k), pll _ y (k), pll _ z (k) are loop parameters that are intermediate to the computation of the PLL filter at time k,

pll_z(k)＝pll_z(k-1)+pll_y(k)；

s52, calculating

Represents the conversion ratio at time k;

s53, calculating delta V_DA(k)＝K_kX pll _ out (k), wherein

ΔV_DA(k) Adjusting the input value of the DA module at the time k; k_kThe ratio of the voltage-controlled terminal voltage value of the crystal oscillator at the moment k to the frequency of a clock signal output by the crystal oscillator;

s54, calculating to obtain V_DA(k)＝V_DA(k-1)+ΔV_DA(k)；V_DA(k) Is an input value, V, of the DA module 6 at time k_DA(k-1) is an input value of the DA module 6 at the k-1 moment;

s55, the crystal oscillator 7 outputs a corresponding clock signal according to the analog voltage signal output by the DA module; proceed to S6.

S6, monitoring the frequency difference of the clock signal output by the crystal oscillator once according to the M paths of parallel reference pulse signals to obtain a frequency difference value, and updating the N frequency difference values by using the frequency difference value; proceed to S3.

The step S6 specifically includes:

s61, monitoring the M paths of parallel reference pulse signals, and recording a numerical value M when the M paths of parallel reference pulse signals are monitored to have a first pulse from the current time₀Resetting the counter; wherein m is₀∈[1,M]，m₀Indicating that said first pulse belongs to the m-th pulse₀A channel parallel reference pulse signal;

s62, counting by the counter according to the frequency f of the clock signal output by the crystal oscillator, and adding 1 to the count value of the counter every time when 1/f of duration passes;

s63, when the second pulse of the M paths of parallel reference pulse signals is detected, recording the value M₁(ii) a Wherein m is₁∈[1,M]，m₁Indicates that the second pulse belongs to the m-th pulse₁A channel parallel reference pulse signal;

s64, calculating the frequency difference Δ F ═ cnt + (m) of the monitoring₁-m₀) (ii) a Wherein cnt is the counter occurring at said second pulseA count value of time;

s65 using DeltaF_i+1Updating Δ F_i，i∈[1,N-1](ii) a Updating Δ F with Δ F_N(ii) a Obtaining N updated frequency difference values delta F₁～ΔF_N(ii) a Proceed to S3.

The invention also provides a crystal oscillator calibration system, which is used for realizing the crystal oscillator calibration method. As shown in fig. 2, the crystal oscillator calibration system includes: the device comprises a reference pulse generation module 1, a high-precision pulse measurement unit 2, a frequency difference monitoring unit 3, a frequency difference screening unit 4, a DA module 6 and a crystal oscillator 7.

The reference pulse generating module 1 is configured to generate a path of serial reference pulse signals.

The high-precision pulse measuring unit 2 is connected with the reference pulse generating module 1 and the crystal oscillator output end, and is used for sampling the reference pulse signal according to a clock signal output by the crystal oscillator and converting the one-path serial reference pulse signal into an M-path parallel reference pulse signal. Preferably, the high-precision pulse measurement unit 2 is implemented by a serdes module of an FPGA.

And the frequency difference monitoring unit 3 is connected with the high-precision pulse measuring unit 2 and the crystal oscillator output end and is used for measuring the frequency difference value of the clock signal output by the crystal oscillator according to the M paths of parallel reference pulse signals.

The frequency difference screening unit 4 is connected to the frequency difference monitoring unit 3, and is configured to screen the frequency difference value, and calculate and generate a frequency difference adjustment value according to the screened frequency difference value.

The adjusting module is connected between the input end of the DA module 6 and the frequency difference screening unit 4, and is used for correcting the input value of the DA module 6 according to the frequency difference adjusting value.

The adjusting module comprises:

and the open-loop adjusting unit 51 is connected between the frequency difference screening module and the DA module 6, and corrects the input value of the DA module 6 according to the frequency difference value adjusting value by adopting an open-loop adjusting method.

And the closed-loop adjusting unit 52 is connected between the frequency difference screening module and the DA module 6, and corrects the input value of the DA module 6 according to the frequency difference adjusting value by adopting a closed-loop adjusting method. Preferably, the closed-loop adjusting unit 52 is a phase-locked loop filter.

The DA module 6 generates a corresponding analog quantity voltage signal according to the input value of the DA module 6.

The crystal oscillator voltage control end is connected with the output end of the DA module 6, and the crystal oscillator generates a corresponding clock signal according to the analog quantity voltage signal output by the DA module 6.

In the embodiment of the invention, the input precision of the reference pulse signal is plus or minus 50ns, the initial frequency difference of the crystal oscillator is 15Hz, and the stability of the crystal oscillator is 5 multiplied by 10^-8. The crystal oscillator calibration method can adjust the accuracy and stability of the crystal oscillator to 2 multiplied by 10 within 60s^-9Adjusting the accuracy and stability of the crystal oscillator to 5 × 10 within 120s^-10And (4) horizontal. It can be seen that, compared with the similar system, the invention greatly shortens the adjustment time of the crystal oscillator 7 while obtaining the high-precision crystal oscillator output.

Compared with the prior art, the reference pulse signal generated by the reference pulse generation module 1 is used as a reference, the frequency of the crystal oscillator is quickly calibrated in a mode of combining open-loop adjustment and closed-loop adjustment, the accuracy and the stability of the clock signal output by the crystal oscillator are improved, and the influence of aging and temperature change of the crystal oscillator 7 on the accuracy of the clock signal output by the crystal oscillator is reduced.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.