阅读说明：本技术 开关泄漏补偿电路 (Switch leakage compensation circuit ) 是由 R·弗朗西斯 C·埃德曼 于 2020-03-26 设计创作，主要内容包括：与开关泄漏补偿延迟电路(405a)相关的装置和相关方法包括补偿晶体管(T-(0)),该补偿晶体管(T-(0))被配置为被动地绕过与控制晶体管(M-(0))串联连接的电容器(C-(0))周围的泄漏电流。在说明性示例中,电容器(C-(0))和补偿晶体管(T-(0))可以并联连接在第一节点(a-(0))和第二节点(b-(0))之间。补偿晶体管(T-(0))的栅极可以例如直接连接到其源极和第二节点(b-(0))。控制晶体管(M-(0))可以将其漏极连接到第二节点(b-(0))。当控制信号关断控制晶体管(M-(0))时,控制晶体管(M-(0))的漏电流可以由补偿晶体管(T-(0))的漏电流提供,使得跨过电容器(C-(0))两端的电压可以保持不变基本恒定。延迟电路(405a)可以有利地减轻电容器(C-(0))的电压下降以减小时钟时间偏差,例如,在低速交错ADC操作中的时钟时间偏差。(Apparatus and associated methods associated with a switching leakage compensated delay circuit (405a) include a compensation transistor (T) 0 ) The compensation transistor (T) 0 ) Configured to passively bypass and control the transistor (M) 0 ) Capacitors (C) connected in series 0 ) Ambient leakage current. In the illustrative example, a capacitor (C) 0 ) And a compensation transistor (T) 0 ) May be connected in parallel at the first node (a) 0 ) And a second node (b) 0 ) In the meantime. Compensation transistor (T) 0 ) May for example be directly connected to its source and second node (b) 0 ). Control transistor(M 0 ) May have its drain connected to the second node (b) 0 ). When the control signal turns off the control transistor (M) 0 ) While controlling the transistor (M) 0 ) Can be compensated by a compensation transistor (T) 0 ) So as to cross the capacitor (C) 0 ) The voltage across the terminals may remain constant and substantially constant. The delay circuit (405a) may advantageously mitigate the capacitor (C) 0 ) To reduce clock skew, e.g., in low speed interleaved ADC operation.)