阅读说明：本技术 成像器件和电子装置 (Imaging device and electronic apparatus ) 是由 山岸肇 日田圣大 小林悠作 于 2018-05-02 设计创作，主要内容包括：成像器件包括：第一芯片(26),其包括含有光电转换区域(34)的第一半导体基板(33)。第一芯片(26)包括：第一绝缘层(53),其包括电连接至光电转换区域(34)的第一多层配线(37)。第一多层配线(37)包括：输出第一像素信号的第一垂直信号线(VSL1)；和第一配线(71)。成像器件包括：第二芯片(28),其包括具有逻辑电路(55)的第二半导体基板(54)。第二芯片(28)包括：第二绝缘层(56),其包括电连接至逻辑电路(55)的第二多层配线(59)。第二多层配线(59)包括第二配线(72)。第一芯片(26)和第二芯片(28)彼此接合,且在平面图中,第一配线(71)和第二配线(72)与第一垂直信号线(VSL1)的至少一部分重叠。(The imaging device includes: a first chip (26) includes a first semiconductor substrate (33) including a photoelectric conversion region (34). The first chip (26) comprises: a first insulating layer (53) including a first multilayer wiring (37) electrically connected to the photoelectric conversion region (34). The first multilayer wiring (37) includes: a first vertical signal line (VSL1) outputting a first pixel signal; and a first wiring (71). The imaging device includes: a second chip (28) comprising a second semiconductor substrate (54) with logic circuitry (55). The second chip (28) comprises: a second insulating layer (56) including a second multilayer wiring (59) electrically connected to the logic circuit (55). The second multilayer wiring (59) includes a second wiring (72). The first chip (26) and the second chip (28) are bonded to each other, and the first wiring (71) and the second wiring (72) overlap at least a part of the first vertical signal line (VSL1) in a plan view.)

1. An imaging device, comprising:

a first chip (26), the first chip (26) comprising:

a first semiconductor substrate (33), the first semiconductor substrate (33) including a photoelectric conversion region (34) that converts incident light into electric charges; and

a first insulating layer (53), the first insulating layer (53) including a first multi-layer wiring (37) electrically connected to the photoelectric conversion region, wherein the first multi-layer wiring includes a first vertical signal line (VSL1) and a first connection region (M4), the first vertical signal line (VSL1) outputs a first pixel signal based on the electric charges, the first connection region (M4) includes a first wiring (71); and

a second chip (28), the second chip (28) comprising:

a second semiconductor substrate (54), the second semiconductor substrate (54) including a logic circuit (55) for processing the first pixel signal; and

a second insulating layer (56), the second insulating layer (56) including a second multi-layer wiring (59) electrically connected to the logic circuit, wherein the second multi-layer wiring includes a second connection region (M14), the second connection region (M14) includes a second wiring (72),

wherein the first chip (26) and the second chip (28) are bonded to each other at least via the first wiring (71) and the second wiring (72), and

wherein the first wiring (71) and the second wiring (72) overlap with at least a part of the first vertical signal line (VSL1) in a plan view.

2. The imaging device according to claim 1, wherein a portion (66) of the first insulating layer (53) and a portion (66) of the second insulating layer (56) are bonded to each other.

3. The imaging device according to claim 1 or 2, wherein the first vertical signal line (VSL1) extends in a first direction, and wherein the first wiring (71) includes a first portion that extends in the first direction and overlaps with the first vertical signal line (VSL1) in the plan view.

4. The imaging device of claim 3, wherein a width of the first portion measured in a second direction is greater than a width of the first vertical signal line (VSL1) measured in the second direction, and wherein the second direction is perpendicular to the first direction.

5. The imaging device according to claim 3 or 4, wherein the first portion overlaps with an entire width of the first vertical signal line (VSL1) over an entire length of the first portion in the first direction in the plan view.

6. The imaging device according to any one of claims 3 to 5, wherein the first wiring (71) includes a second portion extending in a second direction perpendicular to the first direction.

7. The imaging device according to any one of claims 1 to 6, wherein the second wiring (72) extends in the second direction.

8. The imaging device according to claim 7, wherein a width of the second wiring (72) in the first direction is larger than a width of the second portion of the first wiring (71) in the first direction in the plan view.

9. The imaging device according to claim 8, wherein the second wiring (72) overlaps the second portion of the first wiring (71) in the plan view.

10. The imaging device according to claim 8 or 9, wherein the second wiring (72) overlaps with an entirety of the second portion of the first wiring (71) in the plan view.

11. The imaging device according to claim 1 or 2, wherein the first vertical signal line (VSL1) extends in a first direction, and wherein the first wiring (71) extends in a second direction perpendicular to the first direction, and wherein the second wiring (72) extends in the first direction and overlaps with the first vertical signal (VSL1) in the plan view.

12. The imaging device according to claim 11, wherein the second wiring (72) overlaps with all of the first vertical signal line (VSL1) over an entire length of the first portion in the plan view.

13. An imaging device, comprising:

a first chip (26), the first chip (26) comprising:

a first semiconductor substrate (33), the first semiconductor substrate (33) including a plurality of pixel regions (34) arranged in a matrix form and converting incident light into electric charges; and

a first insulating layer (53), the first insulating layer (53) including a first multi-layer wiring (37) electrically connected to the plurality of pixel regions (34), wherein the first multi-layer wiring includes a plurality of vertical signal lines (VSL1) and at least one first wiring (71), the plurality of vertical signal lines (VSL1) outputting respective pixel signals based on the electric charges; and

a second chip (28), the second chip (28) comprising:

a second semiconductor substrate (54), the second semiconductor substrate (54) including a logic circuit (55) for processing the pixel signal; and

a second insulating layer (56), the second insulating layer (56) including a second multi-layered wiring (59) electrically connected to the logic circuit (55), wherein the second multi-layered wiring (59) includes at least one second wiring (72),

wherein the first chip (26) and the second chip (28) are bonded to each other at least via the at least one first wiring (71) and the at least one second wiring (72), and

wherein the at least one first wiring (71) and the at least one second wiring (72) overlap the plurality of vertical signal lines (VSL1) in a plan view.

14. The imaging device according to claim 13, wherein the plurality of vertical signal lines (VSL1) extend in a first direction and are arranged at regular first intervals in the first multilayer wiring (53) in a second direction perpendicular to the first direction, and wherein the at least one first wiring (71) is a plurality of first wirings including first portions that extend in the first direction and are arranged at regular second intervals in the second direction in the first multilayer wiring (53).

15. The imaging device of claim 14, wherein the regular first spacing and the regular second spacing correspond to a pitch between two of the plurality of pixel regions (34).

16. The imaging device of claim 14, wherein the regular first spacing corresponds to a pitch between two of the plurality of pixel regions (34) and the regular second spacing corresponds to half the pitch.

17. The imaging device according to any one of claims 14 to 16, wherein the plurality of first wirings (71) include second portions extending in the second direction.

18. The imaging device according to any one of claims 13 to 17, wherein the at least one second wiring (72) is a plurality of second wirings including a first portion extending in a first direction, and wherein the at least one first wiring (71) extends in a second direction perpendicular to the first direction.

19. The imaging device according to any one of claims 13 to 18, wherein the at least one second wiring (72) includes second wiring portions for respective ones of the plurality of pixel regions (34).

20. An electronic device, comprising:

an imaging device, the imaging device comprising:

first chip (26) the first chip (26) comprises:

a first semiconductor substrate (33), the first semiconductor substrate (33) including a photoelectric conversion region (34) that converts incident light into electric charges; and

a first insulating layer (53), the first insulating layer (53) including a first multi-layer wiring (37) electrically connected to the photoelectric conversion region (34), wherein the first multi-layer wiring (53) includes a first vertical signal line (VSL1) and a first wiring (71), the first vertical signal line (VSL1) outputting a first pixel signal based on the electric charge; and

a second chip (28), the second chip (28) comprising:

a second semiconductor substrate (54), the second semiconductor substrate (54) including a logic circuit (55) for processing the first pixel signal; and

a second insulating layer (56), the second insulating layer (56) including a second multilayer wiring (59) electrically connected to the logic circuit (55), wherein the second multilayer wiring (59) includes a second wiring (72),

wherein the first chip (26) and the second chip (28) are bonded to each other at least via the first wiring (71) and the second wiring (72), and

wherein the first wiring (71) and the second wiring (72) overlap with at least a part of the first vertical signal line (VSL1) in a plan view.

Technical Field

The present invention relates to an imaging device and an electronic apparatus, and particularly to a technique of an imaging device configured by bonding a plurality of semiconductor substrates.

Background

In recent years, digital cameras have become increasingly popular. With the popularization of digital cameras, the demand for solid-state image sensors (image sensors) as main components of digital cameras has been increasing. In terms of performance of the solid-state image sensor, techniques for realizing high image quality and high functions are being developed.

Meanwhile, mobile terminals (mobile phones, Personal Digital Assistants (PDAs), notebook Personal Computers (PCs), tablet computers, and the like) having an imaging function have become popular. With the popularization of mobile terminals, miniaturization, weight reduction, and thinning of solid-state image sensors and components constituting the same have been progressing for the purpose of enhancing the portability of mobile terminals. In addition, in order to continue to expand the spread of mobile terminals, the cost reduction of the solid-state image sensor and the components constituting the same is progressing.

In general, a solid-state image sensor such as a Complementary Metal Oxide Semiconductor (CMOS) image sensor is configured by forming a photoelectric conversion unit, an amplifier circuit, and a multilayer wiring layer on a light receiving surface side of a silicon substrate, and further forming a color filter and a microlens on the semiconductor substrate on the silicon substrate. Further, the cover glass is bonded on the light receiving surface side using a spacer (spacer) such as an adhesive. Further, a terminal is formed on the opposite side of the light receiving surface side.

A signal processing circuit that performs predetermined processing on the output signal is connected to the solid-state image sensor. With the multifunctionalization of the solid-state image sensor, the processing performed in the signal processing circuit tends to increase.

In order to miniaturize a configuration in which a plurality of semiconductor substrates are connected, various steps have been taken. For example, a plurality of semiconductor substrates are sealed in one package by a System In Package (SiP) technology. By sealing, the mounting area can be reduced, and the entire structure can be miniaturized. However, due to the wiring connecting the semiconductor substrate in the SiP technology, the transmission distance becomes long, and high-speed operation may be hindered.

Incidentally, for example, patent document 1 describes a solid-state image sensor configured by bonding together a first semiconductor substrate including a pixel region (pixel array) and a second semiconductor substrate including a logic circuit. According to this configuration, signals can be transmitted at high speed. In the solid-state image sensor, a first semiconductor substrate including a semi-finished pixel array and a second semiconductor substrate including a semi-finished logic circuit are bonded together, and the first semiconductor substrate is thinned, and then the pixel array and the logic circuit are connected. The connection is performed by forming a connection wiring including: the semiconductor device includes a connection conductor connected to a necessary wiring of a first semiconductor substrate, a through connection conductor penetrating the first semiconductor substrate and connected to a necessary wiring of a second semiconductor substrate, and a connection conductor connecting the two connection conductors. Thereafter, the solid-state image sensor is manufactured as a final product and a semiconductor substrate, and the solid-state image sensor is configured as a back-illuminated solid-state image sensor.

Meanwhile, in the solid-state image sensor of patent document 2, which is a relatively new technique in the solid-state image sensor configured by bonding the first semiconductor substrate and the second semiconductor substrate, a method of taking out and connecting copper (Cu) electrodes on both semiconductor substrate surfaces is considered instead of an electrical connection method using through connection conductors.

Further, in the solid-state image sensor of patent document 3, the above-described copper (Cu) electrode is used as a shielding layer. With this configuration, light emission due to hot carriers from the transistors of the logic circuit is shielded, and incidence of light to the pixel array is suppressed. Further, when the first semiconductor substrate and the second semiconductor substrate are bonded, capacitive coupling occurs in a portion where the insulating film is connected, and an image quality problem may occur. In contrast, according to the solid-state image sensor of patent document 3, the formation of the shielding layer can suppress the generation of the capacitive coupling. Further, patent document 3 describes that the entire thickness of the semiconductor substrate after bonding is also suppressed. Note that in order to use a copper electrode as a shielding layer as in patent document 3, the surface occupation ratio (coverage) of the copper electrode needs to be set at a fixed high ratio. Here, the "surface occupancy ratio" refers to a ratio of a surface area of the shielding portion to a surface area of one pixel unit.

Reference list

Patent document

Patent document 1: JP 2012 64709A

Patent document 2: JP 2013-73988A

Patent document 3: JP 2012 164870A

Disclosure of Invention

Technical problem to be solved by the invention

However, the solid-state image sensor in patent document 3 does not have a region where the insulating film of the upper substrate and the insulating film of the lower substrate are directly bonded on the bonding surface of the semiconductor substrate, and therefore the bonding strength becomes low and voids (bubbles) are easily formed when bonding the semiconductor substrate. If the voids are formed, the semiconductor substrate may be separated in the process of thinning the Si substrate of the first semiconductor wafer performed after bonding the wafers because the bonding strength of the void portion is low.

The reason why the separation is caused is that the bonding strength of copper and the region where copper and the insulating film are directly bonded is lower than the bonding strength of the region where the insulating film and the insulating film are directly bonded. Therefore, in order to reduce the separation at the time of bonding the semiconductor substrates, it is necessary to ensure that the ratio of the region where the insulating film and the insulating film are directly bonded is a fixed ratio or higher.

The present invention has been made in view of the above circumstances, and it is desirable to provide an imaging device capable of improving the bonding strength of a semiconductor substrate while suppressing occurrence of voids in a bonding portion of the semiconductor substrate.

Solution to the technical problem

According to an embodiment of the present invention, an imaging device includes a first chip including: a first semiconductor substrate including a photoelectric conversion region that converts incident light into electric charges; and a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multi-layer wiring includes a first vertical signal line that outputs a first pixel signal based on electric charges and a first wiring. The imaging device includes a second chip including: a second semiconductor substrate including a logic circuit for processing the first pixel signal; and a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to each other via at least a first wiring and a second wiring, and the first wiring and the second wiring overlap at least a part of the first vertical signal line in a plan view.

In some embodiments, a portion of the first insulating layer and a portion of the second insulating layer are bonded to each other.

In some embodiments, the first vertical signal line may extend in the first direction, and the first wiring may include a first portion extending in the first direction and overlapping the first vertical signal line in a plan view.

In some embodiments, a width of the first portion measured in the second direction may be greater than a width of the first vertical signal line measured in the second direction, and the second direction may be perpendicular to the first direction.

In some embodiments, the first portion may overlap with an entire width of the first vertical signal line over an entire length of the first portion in the first direction in a plan view.

In some embodiments, the first wiring may include a second portion extending in a second direction perpendicular to the first direction.

In some embodiments, the second wire may extend in the second direction.

In some embodiments, a width of the second wiring in the first direction may be larger than a width of the second portion of the first wiring in the first direction in a plan view.

In some embodiments, the second wire may overlap with a second portion of the first wire in a plan view.

In some embodiments, the second wire may overlap with an entirety of the second portion of the first wire in a plan view.

In some embodiments, the first vertical signal line may extend in a first direction, and the first wiring may extend in a second direction perpendicular to the first direction, the second wiring extending in the first direction and overlapping the first vertical signal in a plan view, the second portion extending in the second direction.

In some embodiments, the second wiring may overlap with all of the first vertical signal lines over an entire length of the first portion in a plan view.

According to another embodiment of the present invention, an imaging device includes a first chip including: a first semiconductor substrate including a plurality of pixel regions arranged in a matrix form and converting incident light into charges; and a first insulating layer including a first multi-layered wiring electrically connected to the plurality of pixel regions. The first multi-layer wiring includes a plurality of vertical signal lines that output respective pixel signals based on electric charges and at least one first wiring. The imaging device includes a second chip including: a second semiconductor substrate including a logic circuit for processing a pixel signal; and a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit. The second multilayer wiring includes at least one second wiring. The first chip and the second chip are bonded to each other via at least one first wiring and at least one second wiring, and the at least one first wiring and the at least one second wiring overlap with the plurality of vertical signal lines in a plan view.

In some embodiments, the plurality of vertical signal lines may extend in a first direction, and may be arranged in the first multi-layered wiring at regular first intervals in a second direction perpendicular to the first direction, and the at least one first wiring may be a plurality of first wirings including: first portions extending in the first direction and arranged at regular second intervals in the second direction in the first multilayer wiring.

In some embodiments, the regular first interval and the regular second interval may correspond to a pitch between two of the plurality of pixel regions.

In some embodiments, the regular first interval may correspond to a pitch between two of the plurality of pixel regions, and the regular second interval may correspond to half the pitch.

In some embodiments, the plurality of first wires may include a second portion extending in the second direction.

In some embodiments, the at least one second wire may be a plurality of second wires including a first portion extending in a first direction, and the at least one first wire may extend in a second direction perpendicular to the first direction.

In some embodiments, the at least one second wiring may include a second wiring portion for a corresponding pixel region of the plurality of pixel regions.

According to another embodiment of the present invention, an electronic apparatus includes an imaging device including a first chip. The first chip includes: a first semiconductor substrate including a photoelectric conversion region that converts incident light into electric charges; and a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multi-layer wiring includes a first vertical signal line that outputs a first pixel signal based on electric charges and a first wiring. The imaging device includes a second chip including: a second semiconductor substrate including a logic circuit for processing the first pixel signal; and a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to each other via at least the first wiring and the second wiring. The first wiring and the second wiring overlap with at least a part of the first vertical signal line in a plan view.

The invention has the advantages of

According to the present invention, it is possible to provide a solid-state image sensor capable of improving the bonding strength of a semiconductor substrate while suppressing the occurrence of voids in the bonding portion of the semiconductor substrate. Note that the effect of the present invention is not limited to the above-described effect, and may be expressed as any effect described in the present invention.

Embodiments of the present invention will now be described with reference to the drawings, wherein like reference numerals represent like parts throughout.

Drawings

Fig. 1 is a block diagram illustrating a configuration example of a solid-state image sensor according to an embodiment of the present invention.

Fig. 2A to 2C are schematic diagrams illustrating a stacked structure of a solid-state image sensor according to an embodiment of the present invention.

Fig. 3 is a schematic configuration diagram illustrating a main part of a first embodiment of a solid-state image sensor according to the present invention.

Fig. 4 is an enlarged configuration diagram illustrating a main portion of the first semiconductor substrate of the first embodiment.

Fig. 5 is an enlarged configuration diagram illustrating a main portion of the second semiconductor substrate of the first embodiment.

Fig. 6A and 6B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the first embodiment.

Fig. 7 is an enlarged schematic view illustrating a pixel unit signal line layout of the first embodiment.

Fig. 8 is a manufacturing process diagram (part 1) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 9 is a manufacturing process diagram (part 2) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 10 is a manufacturing process diagram (part 3) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 11 is a manufacturing process diagram (part 4) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 12 is a manufacturing process diagram (part 5) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 13 is a manufacturing process diagram (part 6) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 14 is a manufacturing process diagram (part 7) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 15 is a manufacturing process diagram (part 8) illustrating an example of a manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 16 is a manufacturing process diagram (part 9) illustrating an example of the manufacturing method of the solid-state image sensor of the first embodiment.

Fig. 17A and 17B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the second embodiment.

Fig. 18A and 18B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the third embodiment.

Fig. 19A and 19B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the fourth embodiment.

Fig. 20A and 20B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the fifth embodiment.

Fig. 21A and 21B are enlarged configuration diagrams illustrating a shielding portion of a solid-state image sensor of a sixth embodiment.

Fig. 22A and 22B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the seventh embodiment.

Fig. 23A and 23B are enlarged configuration diagrams illustrating a shielding portion of a solid-state image sensor of an eighth embodiment.

Fig. 24A and 24B are enlarged configuration diagrams illustrating a shielding portion of the solid-state image sensor of the ninth embodiment.

Fig. 25 is a schematic configuration diagram illustrating a main part of a tenth embodiment of a solid-state image sensor according to the present invention.

Fig. 26 is a schematic configuration diagram of an electronic device according to an eleventh embodiment of the invention.

Detailed Description

Hereinafter, preferred embodiments for implementing the present invention will be described with reference to the accompanying drawings. Note that the embodiments described below illustrate examples of representative embodiments of the present invention, and the scope of the present invention is not construed in a narrow manner by these embodiments. Furthermore, any one or more of the embodiments described below can be combined. Note that, with respect to the drawings, the same or equivalent elements or members are denoted by the same reference numerals, and overlapping description is omitted.

The description will be given in the following order.

1. Example of construction of solid-state image sensor

2. Stacked structure example of solid-state image sensor

3. Solid-state image sensor of first embodiment

4. Solid-state image sensor of the second embodiment

5. Solid-state image sensor of third embodiment

6. Solid-state image sensor of fourth embodiment

7. Solid-state image sensor of fifth embodiment

8. Solid-state image sensor of sixth embodiment

9. Solid-state image sensor of seventh embodiment

10. Solid-state image sensor of eighth embodiment

11. Solid-state image sensor of ninth embodiment

12. Solid-state image sensor of tenth embodiment

13. Electronic device of eleventh embodiment

<1. configuration example of solid-state image sensor >

Fig. 1 is a block diagram illustrating a configuration example of a solid-state image sensor according to an embodiment of the present invention.

As shown in fig. 1, the solid-state image sensor 1 is configured as, for example, a Complementary Metal Oxide Semiconductor (CMOS) image sensor. The solid-state image sensor 1 includes a pixel region (pixel array) 3, in which pixel region 3a plurality of pixels (or pixel regions) 2 are arranged in a two-dimensional array on a semiconductor substrate (e.g., Si substrate) (not shown).

The pixel (or pixel region) 2 includes one (or more) photoelectric conversion unit(s) (e.g., photodiode (s)) and a plurality of pixel transistors (MOS transistors). The plurality of pixel transistors can be constituted by, for example, three transistors including a transfer transistor, a reset transistor, and an amplification transistor. Further, the plurality of pixel transistors can also be constituted by four transistors obtained by adding a selection transistor. Note that the equivalent circuit of the unit pixel is similar to a known technique, and thus detailed description is omitted.

Further, the pixel 2 can be constituted by one unit pixel, or can have a pixel sharing structure. The pixel sharing structure is a structure in which a plurality of photodiodes share transistors other than a floating diffusion and a plurality of transfer transistors. That is, in pixel sharing, the photodiode and the transfer transistor constituting a plurality of unit pixels share one other pixel transistor.

The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

The vertical drive circuit 4 is constituted by, for example, a shift register. The vertical drive circuit 4 selects a pixel drive wiring, supplies a pulse for driving a pixel to the selected pixel drive wiring, and drives the pixel in units of rows. That is, the vertical drive circuit 4 sequentially selects and scans the pixels 2 in the pixel array 3 in a row unit in the vertical direction. Then, the vertical drive circuit 4 supplies a pixel signal based on the signal charge generated according to the received-light amount in the photoelectric conversion unit of each pixel 2 to the column signal processing circuit 5 through a Vertical Signal Line (VSL) 9.

The column signal processing circuit 5 is arranged in each column of the pixels 2, for example. The column signal processing circuit 5 performs signal processing such as noise removal on signals output from the pixels 2 of one row in each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as Correlated Double Sampling (CDS) (for removing fixed pattern noise unique to the pixel 2), signal amplification, analog/digital (a/D) conversion, and the like. A horizontal selection switch (not shown) is connected and provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

The horizontal drive circuit 6 is constituted by a shift register, for example. The horizontal drive circuit 6 sequentially outputs horizontal scan pulses to sequentially select the column signal processing circuits 5, and outputs pixel signals from the respective column signal processing circuits 5 to the horizontal signal line 10.

The output circuit 7 performs signal processing on signals sequentially supplied from the column signal processing circuit 5 through the horizontal signal line 10, and outputs the signals. The output circuit 7 may perform only buffering, or may perform various types of digital signal processing such as black level adjustment and column variation correction.

The control circuit 8 receives an input clock and data indicating an operation mode and the like, and outputs data of internal information and the like of the solid-state image sensor 1. Further, the control circuit 8 generates a clock signal and a control signal serving as references for the operations of the vertical drive circuit 4, the column signal processing circuits 5, the horizontal drive circuit 6, and the like, based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. Then, the control circuit 8 inputs signals to the vertical drive circuit 4, the column signal processing circuits 5, the horizontal drive circuit 6, and the like.

The input/output terminal 12 exchanges signals with the outside.

<2 > stacked structure example of solid-state image sensor >

Fig. 2A to 2C are schematic diagrams illustrating a stacked structure example of a solid-state image sensor according to an embodiment of the present invention. A stacked structure example of a solid-state image sensor to which the present invention is applied will be described using fig. 2A to 2C.

As a first example, the solid-state image sensor 1a shown in fig. 2A is constituted by a first semiconductor substrate 21 and a second semiconductor substrate 22. The pixel array 23 and the control circuit 24 are mounted on the first semiconductor substrate 21. A logic circuit 25 including a signal processing circuit is mounted on the second semiconductor substrate 22. Then, the first semiconductor substrate 21 and the second semiconductor substrate 22 are electrically connected to each other to configure the solid-state image sensor 1a as one semiconductor substrate.

As a second example, the solid-state image sensor 1B shown in fig. 2B is constituted by a first semiconductor substrate 21 and a second semiconductor substrate 22. The pixel array 23 is mounted on the first semiconductor substrate 21. A control circuit 24 and a logic circuit 25 including a signal processing circuit are mounted on the second semiconductor substrate 22. Then, the first semiconductor substrate 21 and the second semiconductor substrate 22 are electrically connected to each other to configure the solid-state image sensor 1b as one semiconductor substrate.

As a third example, the solid-state image sensor 1C shown in fig. 2C is constituted by a first semiconductor substrate 21 and a second semiconductor substrate 22. A pixel array 23 and a control circuit 24-1 that controls the pixel array 23 are mounted on the first semiconductor substrate 21. A logic circuit 25 and a control circuit 24-2 that controls the logic circuit 25 including a signal processing circuit are mounted on the second semiconductor substrate 22. Then, the first semiconductor substrate 21 and the second semiconductor substrate 22 are electrically connected to each other to configure the solid-state image sensor 1c as one semiconductor substrate.

Although not shown, the CMOS solid-state image sensor may be constituted by two or more bonded semiconductor substrates depending on the configuration. For example, a semiconductor substrate including a memory element array or a semiconductor substrate including other circuit elements can be added to the first semiconductor substrate and the second semiconductor substrate to join these three or more semiconductor substrates, thereby configuring the CMOS solid-state image sensor as one substrate.

[ configuration example of solid-state image sensor ]

<3 > solid-state image sensor of the first embodiment

Fig. 3 illustrates a first embodiment of a solid-state image sensor (i.e., a back-illuminated CMOS solid-state image sensor) according to the present invention. The back-illuminated CMOS solid-state image sensor is a CMOS solid-state image sensor: has a light receiving section arranged above a circuit section and has higher sensitivity and lower noise than a front-illuminated CMOS solid-state image sensor. The solid-state image sensor 31 according to the first embodiment is constituted by a laminated semiconductor substrate 32 in which a first semiconductor substrate (or first chip) 26 on which a pixel array (or pixel region) 34 and a control circuit (not shown) are formed and a second semiconductor substrate (or second chip) 28 on which a logic circuit 55 is formed are bonded to each other, similarly to the solid-state image sensor 1a shown in fig. 2A. The first semiconductor substrate 26 and the second semiconductor substrate 28 are bonded to each other in such a manner that mutual multilayer wiring layers as described below face each other and connection wirings are directly bonded.

In the first semiconductor substrate 26, a pixel array 34 is formed on a first semiconductor substrate 33 made of silicon formed as a thin film, the pixel array 34 having a plurality of pixels arranged in a two-dimensional column manner, each pixel including a photodiode PD serving as a photoelectric conversion unit and a plurality of pixel transistors Tr1 and Tr 2. Although not shown, a plurality of MOS transistors constituting a control circuit are formed on the semiconductor substrate 33. On the surface 33a side of the semiconductor substrate 33, a multilayer wiring layer 37 is formed through an interlayer insulating film 53 as a first insulating film, in which multilayer wiring layer 37 are arranged wiring 36 and wiring 35(35a to 35d) made of multilayer metals (in this example, four layers of metals M1 to M4). As the wiring 35 and the wiring 36, copper (Cu) wirings formed by a dual damascene method are used. On the back surface side of the semiconductor substrate 33, a light shielding film 39 is formed via an insulating film 38, the light shielding film 39 includes an optical black region 41, and a color filter 44 and an on-semiconductor-substrate lens 45 are formed on an effective pixel array 42 via a planarization film 43. The on-semiconductor-substrate lens 45 can also be formed on the optical black region 41.

In fig. 3, the pixel transistors Tr1 and Tr2 are illustrated as representatives of a plurality of pixel transistors. FIG. 3 schematically illustrates a pixel of the pixel array 34, and FIG. 4 illustrates oneDetails of the individual pixels. In the first semiconductor substrate 26, the photodiode PD is formed on a semiconductor substrate 33 formed as a thin film. The photodiode PD includes, for example, an n-type semiconductor region 46 and a P-type semiconductor region 47 on the substrate surface side. A P-type semiconductor region 48 is formed on a substrate surface constituting a pixel through a gate insulating film, and the gate electrode 48 and the source/drain region 49 paired with the gate electrode 48 form pixel transistors Tr1 and Tr 2. The pixel transistor Tr1 adjacent to the photodiode PD corresponds to the floating diffusion region FD. The unit pixel is isolated in the element isolation region 51. For example, the element isolation region 51 is formed to have a Shallow Trench Isolation (STI) structure having, for example, SiO embedded in a groove formed in the substrate₂An insulating film such as a film.

In the multilayer wiring layer 37 of the first semiconductor substrate 26, the adjacent upper and lower layers of the corresponding pixel transistor and wiring 35 are connected by a conductive via 52. Further, the connection wiring 36 made of the fourth layer metal M4 is formed so as to face the junction surface 40 between the first semiconductor substrate 26 and the second semiconductor substrate 28. The connection wiring 36 is connected to the necessary wiring 35d made of the third-layer metal M3 through the conductive via 52. In addition, a vertical signal line VSL1 is formed in the third layer. The joining surface 40 may include a first connection region for the multilayer wiring layer 37 including the first wiring 71 and a second connection region for the multilayer wiring layer 59 including the second wiring 72. The first chip 26 and the second chip 28 are bonded to each other at least by the first wiring 71 and the second wiring 72.

In the second semiconductor substrate 28, a logic circuit 55 constituting a peripheral circuit is formed in a region serving as a semiconductor substrate of the second semiconductor substrate 54 made of silicon. The logic circuit 55 is formed of a plurality of MOS transistors Tr11 to Tr14 including CMOS transistors. On the surface side of the second semiconductor substrate 54 shown in fig. 5, a multilayer wiring layer 59 is formed by an interlayer insulating film 56 as a second insulating film, and a wiring 58 and wirings 57(57a to 57c) made of multilayer metals (in this example, four layers of metals M11 to M14) are arranged in this multilayer wiring layer 59. As the wiring 57 and the wiring 58, copper (Cu) wirings formed by a dual damascene method are used.

Fig. 3 illustrates MOS transistors Tr11 to Tr14 as representatives of the plurality of MOS transistors of the logic circuit 55. For example, fig. 3 schematically illustrates MOS transistors Tr11 to Tr14, and fig. 5 illustrates details of the MOS transistors Tr11 and Tr 12. In the second semiconductor substrate 28, MOS transistors Tr11 and Tr12 including a pair of source/drain regions 61 and a gate electrode 62 are formed via a gate insulating film in a semiconductor well region on the surface side of the second semiconductor substrate 54. The MOS transistors Tr11 and Tr12 are isolated in the element isolation region 63 having an STI structure, for example.

In the multilayer wiring layer 59 of the second semiconductor substrate 28, the MOS transistors Tr11 to Tr14 and the wiring 57 and the adjacent upper and lower layers of the wiring 57 are connected by the conductive via 64. Further, the connection wiring 58 made of the fourth-layer metal M14 is formed so as to face the bonding surface 40 between the first semiconductor substrate 26 and the second semiconductor substrate 28. The connection wiring 58 is connected to a necessary wiring 57c made of the third-layer metal M13 through a conductive via 64.

The first semiconductor substrate 26 and the second semiconductor substrate 28 are electrically connected to each other by directly bonding the connection wiring 36 and the connection wiring 58 facing the bonding surface 40 in such a manner that the mutual multilayer wiring layers 37 and 59 face each other. As described in the following manufacturing method, the interlayer insulating film 66 located in the vicinity of the junction is formed by combining a Cu diffusion barrier insulating film for preventing (or, for reducing) Cu diffusion of the Cu wiring and an insulating film having no Cu diffusion property. The direct bonding of the connection wiring 36 and the connection wiring 58 to the Cu wiring is performed by thermal diffusion bonding. The interlayer insulating film 66 other than the connection wiring 36 and the connection wiring 58 is bonded by plasma bonding or using an adhesive.

As described above, in addition to the method of directly bonding the connection wiring 36 and the connection wiring 58 facing the bonding surface 40, a method of forming an extremely thin uniform insulating film 900 on the multilayer wiring layers 37 and 59 and bonding the layers by plasma bonding or the like may also be used. Note that the insulating film 900 is not illustrated in fig. 3.

In the present embodiment, as shown in fig. 3, a shielding layer 68 having a potential clamped by a conductive film on the same layer as the connection wiring is formed particularly in the vicinity of the junction between the first semiconductor substrate 26 and the second semiconductor substrate 28. The shielding layer 68 of the present embodiment is formed as follows: a shielding portion (first conductor or first wiring) 71 made of metal M4 located at the same layer as the connection wiring 36 on the first semiconductor substrate 26 side and a shielding portion (second conductor or second wiring) 72 made of metal M14 located at the same layer as the connection wiring 58 on the second semiconductor substrate 28 side overlap each other.

Fig. 6A is an enlarged configuration diagram illustrating the shielding portion 71 of the first semiconductor substrate 26 of the present embodiment. Fig. 6B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the present embodiment. The layout of the shielding portions 71 and 72 of the present invention will be described using fig. 6A and 6B.

As shown in fig. 6A, the shielding portion 71 of the present embodiment is formed in the following layout: wherein a plurality of vertical stripe shapes are arranged according to an arrangement interval of the beams of the vertical signal line M3 or an FD pitch (FD pitch) of the pixel unit, and the horizontal stripe shapes are arranged in a direction perpendicular to the plurality of vertical stripe shapes. As an example, the bundle of the vertical signal lines M3 is formed of four vertical signal lines. The shielding portion 71 of the present embodiment is arranged above the bundle of vertical signal lines M3 of the analog circuit in the direction of the bonding surface 40 to cover a part or all of the vertical signal lines M3. Note that the vertical stripe shape and the horizontal stripe shape of the shielding portion 71 of the present embodiment are perpendicular to each other. However, the directions are not limited to the vertical directions as long as the directions intersect with each other. Further, as shown in fig. 6B, the shielding portion 72 of the present embodiment is formed in the following layout: the interlayer insulating film 66 is included at a position overlapping the shielding portion 71 in a plan view, and the horizontal stripe shape is arranged at a position overlapping the horizontal stripe shape of the shielding portion 71. According to at least one embodiment, the FD pitch is the pitch between the floating diffusions of the photoelectric conversion regions in the pixel cell (e.g., from the center of one floating diffusion region to the center of an adjacent floating diffusion region). According to at least one embodiment, the FD pitch is the pitch between pixel cells (e.g., between the boundaries of pixel cells), where each pixel cell includes a plurality of pixels (e.g., 2 x 2 pixels, 2 x 4 pixels, 4 x 2 pixels, etc.) that share a floating diffusion region. According to at least one exemplary embodiment, the FD pitch is a pitch between photodiodes of two pixels or pixel units.

As the shielding portions 71 and 72 of the present embodiment, copper (Cu) is used as the first conductor and the second conductor as an example. In the present embodiment, the surface occupation ratio (area ratio) of Cu of the first conductor is 40 to 70%, and the surface occupation ratio of Cu of the second conductor is 0 to 30%. Here, the "surface occupancy ratio" refers to a ratio of a surface area of the shielding portion to a surface area of one pixel unit.

Fig. 7 is an enlarged view illustrating a signal line layout of a pixel array of the solid-state image sensor of the present embodiment. In the pixel array 23 of the present embodiment, a plurality of photodiodes are arranged vertically and horizontally in parallel. A plurality of reset signal lines M21, transfer signal lines M22, and pixel selection signal lines M23 are arranged in parallel in the pixel array 23 at predetermined pitches in the horizontal direction. Further, a plurality of vertical signal lines M3 are arranged in the pixel array 23 at a predetermined pitch in the vertical direction.

The shielding layer 68 advantageously has a potential clamp. For example, a ground potential (ground potential) is applied and the potential of the shielding layer 68 is stabilized. The potential clamping can be performed on the first semiconductor substrate 33 side, the second semiconductor substrate 54 side, or both the first semiconductor substrate 33 and the second semiconductor substrate 54. As a method of potential clamping, for example, there is a method of connecting to a reference voltage VSS on the low voltage side. As an example, there is a method of connecting a horizontal signal line supplying a power supply voltage and a shielding layer using a multilayer wiring technique. The location of the connections is advantageous in the pixel array 34. However, the location of the connection may be external to the pixel array 34. Note that in the shielding portion 71 as the first conductor and the shielding portion 72 as the second conductor, the size covering the planar shape of the pixel array 34 is favorably the size of the planar shape of the pixel array 34 or more.

< example of method for manufacturing solid-state image sensor >

An example of a method of manufacturing the solid-state image sensor 31 according to the first embodiment will be explained in fig. 8 to 16. Fig. 8 to 10 illustrate the process on the first semiconductor substrate 26 side including the pixel array 34, fig. 11 to 13 illustrate the process on the second semiconductor substrate 28 side including the logic circuit 55, and fig. 14 to 16 illustrate the process at the time of bonding and after bonding.

First, as shown in fig. 8, a semiconductor well region 30 is formed in a region serving as a semiconductor substrate of a first semiconductor wafer (hereinafter, referred to as a semiconductor substrate) 33 made of silicon, and a photodiode PD serving as a photoelectric conversion unit of a pixel is formed in the semiconductor well region 30. Although not illustrated, the element isolation region 51 can be formed first (see fig. 4). The photodiode PD is formed to extend in the depth direction of the semiconductor well region 30. The photodiodes PD are formed in the effective pixel array 42 and the optical black region 41 constituting the pixel array 34.

Further, a plurality of pixel transistors constituting pixels are formed on the surface 33a side of the semiconductor well region 30. For example, the pixel transistor can be constituted by a transfer transistor, a reset transistor, and an amplification transistor. Here, as described above, the pixel transistors Tr1 and Tr2 are illustrated as being representative. Although not shown, the pixel transistors Tr1 and Tr2 are formed to include a pair of source/drain regions and a gate electrode formed via a gate insulating film.

In the present example, the wiring 35(35a, 35b, 35c, and 35d) made of the three-layered metals M1 to M3 is formed via the interlayer insulating film 53 to include the conductive via 52 in the upper portion on the surface 33a side of the semiconductor substrate 33. The wiring 35 can be formed by a dual damascene method. That is, a wiring groove and a via first connection hole are simultaneously formed in the interlayer insulating film 53, then a Cu diffusion barrier metal film for preventing (or alternatively, reducing) Cu diffusion and a Cu seed film are formed, and then a Cu material layer is embedded by plating. Examples of the Cu diffusion barrier metal film include films made of Ta, TaN, Ti, TiN, W, WN, Ru, and TiZrN, and alloy films containing the above metals. Next, the excess Cu material layer is removed by a Chemical Mechanical Planarization (CMP) method, and a Cu wiring integrated with the planarized conductive via is formed. Thereafter, although not shown, a Cu diffusion barrier insulating film is formed. As the Cu barrier insulating film, for example, an insulating film made of SiN, SiC, SiCN, or SiON can be used. By repeating the above process, the wirings 35a to 35d made of the three-layered metals M1 to M3 are formed.

Next, as shown in fig. 9, a first insulating film 76 having no Cu diffusion barrier property, a second insulating film 77 having no Cu diffusion barrier property, and a Cu diffusion barrier insulating film 75 are sequentially formed. The first insulating film 76 and the second insulating film 77 are made of SiO₂Film or SiCOH film formation. Further, as the Cu barrier insulating film 75, for example, an insulating film made of SiN, SiC, SiCN, or SiON can be used similarly to the above description. The Cu diffusion barrier insulating film 75, the first insulating film 76, and the second insulating film 77 correspond to the interlayer insulating film 53. Next, first, the uppermost Cu diffusion barrier insulating film 75, the first insulating film 76, and the second insulating film 77 are patterned using pre-punching by photolithography and etching techniques, and a via (via) 80 as an opening portion is selectively formed. Thereafter, the second insulating film 77 is partially patterned, and the opening portion 78 is selectively formed. That is, patterning is performed to include the opening 78 corresponding to the shielding portion 71 to be formed, and the opening 79 and the through hole 80 corresponding to the connection wiring 36 to be formed.

Next, as shown in fig. 10, similarly to the above description, the shielding portion 71 including the opening portions, and the conductive via 52 and the connection wiring 36 connected to the wiring 35d are formed in such a manner that the Cu material is fitted into the opening portions 78, 79 and the through hole 80 using the dual damascene method. The shielding portion 71 and the connection wiring 36 are formed of a fourth-layer metal M4. Through these processes, the multilayer wiring layer 37 is formed of the wirings 35a to 35d made of the metals M1 to M4, the connection wiring 36, the shielding section 71, the interlayer insulating film 53, and the insulating films 75 to 77. Here, the wiring 35d made of the fourth-layer metal M4 connected to the connection wiring 36 is advantageously formed to extend sufficiently to the shielding portion 71 side and to have an area overlapping with the shielding portion 71 so that light emitted from the logic circuit side does not leak to the photodiode PD side.

Further, an extremely thin uniform insulating film 900 is formed on the shielding portion 71 and the connection wiring 36.

Meanwhile, as shown in fig. 11, a semiconductor well region 50 is formed in a region serving as a semiconductor substrate of a second semiconductor wafer (hereinafter, referred to as a semiconductor substrate) 54 made of silicon. A plurality of MOS transistors Tr11 to Tr14 constituting the logic circuit 55 are formed in the semiconductor well region 50. Here, as described above, the MOS transistors Tr11 to Tr14 are illustrated as representatives. Although not shown, the element isolation region 63 can be formed first (see fig. 5).

In the present example, the wiring 57(57a, 57b, and 57c) made of the three-layer metals M11 to M13 is formed via the interlayer insulating film 56 to include the conductive via 64 in the upper portion on the surface side of the semiconductor substrate 54. The wiring 57 can be formed by a dual damascene method. That is, a via hole and a wiring groove are formed simultaneously first in an interlayer insulating film, then a Cu diffusion barrier metal film for preventing (or alternatively, reducing) Cu diffusion and a Cu seed film are formed, and then a Cu material layer is embedded by plating. Examples of the Cu diffusion barrier metal film include films made of Ta, TaN, Ti, TiN, W, WN, Ru, and TiZrN, and alloy films containing the above metals. Next, the excess Cu material layer is removed by a Chemical Mechanical Planarization (CMP) method, and a Cu wiring integrated with the flat conductive via is formed. Thereafter, although not shown, a Cu diffusion barrier insulating film is formed. As the Cu barrier insulating film, for example, an insulating film made of SiN, SiC, SiCN, or SiON can be used. By repeating these processes, the wirings 57a to 57c made of the three-layered metals M11 to M13 are formed.

Next, as shown in fig. 12, a first insulating film 82 having no Cu diffusion barrier property, a second insulating film 83 having no Cu diffusion barrier property, and a Cu diffusion barrier insulating film 81 are sequentially formed. The first insulating film 82 and the second insulating film 83 are made of SiO₂Film or SiCOH film formation. Further, as the Cu barrier insulating film 81, for example, an insulating film made of SiN, SiC, SiCN, or SiON can be used similarly to the above description. The Cu diffusion barrier insulating film 81, the first insulating film 82, and the second insulating film 83 correspond to an interlayer insulating film. Next, the Cu diffusion barrier insulating film 81, the first insulator, on the uppermost surface are subjected to pre-drilling using photolithography and etching techniquesThe insulating film 82 and the second insulating film 83 are patterned, and the through holes 86 are selectively formed as opening portions. Thereafter, a portion of the second insulating film 83 is patterned, and the opening portions 84 and 85 are selectively formed.

Next, as shown in fig. 13, similarly to the above description, the shielding portion 72, and the conductive via 64 and the connection wiring 58 connected to the wiring 57c are formed in such a manner that the Cu material is embedded in the opening portions 84, 85 and the through hole 86 using the dual damascene method. The shielding portion 72 and the connection wiring 58 are formed of a fourth-layer metal M14. Through these processes, the wirings 57a to 57c made of the metals M11 to M13, the connection wiring 58, the shielding section 72, the interlayer insulating film 56, and the insulating films 81 to 83 form the multilayer wiring layer 59.

Further, an extremely thin uniform insulating film 901 is formed on the shielding portion 72 and the connection wiring 58.

Next, as shown in fig. 14, the first semiconductor substrate 33 and the second semiconductor substrate 54 are bonded as follows: the mutual multilayer wiring layers face each other, and the connection wiring 36 and the connection wiring 58 are in direct contact with each other and electrically connected. That is, the first semiconductor substrate 33 and the second semiconductor substrate 54 are physically bonded and electrically connected. At this time, the shielding portion 71 and the shielding portion 72 are directly joined at the overlapping portion. That is, the connection wiring 36 and the connection wiring 58 are thermally diffusion bonded to the shielding portions 71 and 72 by heat treatment. The heat treatment temperature at this time can be about 100 to 500 ℃. Further, an insulating film as an interlayer insulating film is plasma-bonded by surface treatment. Note that an insulating film as an interlayer insulating film can be bonded using an adhesive.

As described above, the first conductor of the shielding portion 71 and the second conductor of the shielding portion 72 can first have the insulating film provided in the junction surface 40 and then heat is applied to subject copper as a conductor to crystal growth to connect the first and second conductors in the vicinity of the junction surface 40. Therefore, the first conductor and the second conductor are arranged on the bonding surface 40 side with respect to the first semiconductor substrate 26 and with respect to the logic circuit 55 and the wiring 35 formed in the second semiconductor substrate, respectively.

Next, as shown in fig. 15, the first semiconductor substrate 33 is ground and polished using a CMP method or the like, and the first semiconductor substrate 33 is formed into a thin film so as to leave the necessary film thickness of the photodiode PD from the back surface side.

Next, as shown in fig. 16, a light-shielding film 39 is formed on the film surface via an insulating film 38 so as to include the photodiode PD corresponding to the optical black region. Further, on the photodiodes PD corresponding to the effective pixel array, a color filter 44 and an on-semiconductor-substrate lens 45 are formed via a planarization film 43.

Next, semiconductor substrate fabrication is performed in which the bonded first semiconductor substrate 33 and second semiconductor substrate 54 are separated, thereby obtaining the target solid-state image sensor 31 shown in fig. 16.

As the shielding portions 71 and 72, the connection wirings 36 and 58, and the metals M4 and M14 located in the same layer as them, it is desirable to use a material having high conductivity, high shielding property, and easy bonding. As a material having such characteristics, a single material or an alloy of Al, W, Ti, Ta, Mo, or Ru can be used in addition to Cu.

It is desirable that the film thickness of the shielding layer 68 (in this example, the film thicknesses of the shielding portions 71 and 72) be determined in accordance with the wavelength of light emitted from the second semiconductor substrate 28 side. In the present embodiment, light emission due to hot carriers from the MOS transistors of the second semiconductor substrate 28 needs to be shielded. Therefore, the thickness of the shielding film needs to be designed for light having a wavelength of about 1 μm. For example, the film thickness of the shielding layer 68 (i.e., the film thickness of the shielding portions 71 and 72) can be about 50 to 800 nm.

According to the solid-state image sensor 31 and the manufacturing method thereof of the present embodiment, the light shielding layer and the shielding layer (shielding layer) 68 against electrical noise are formed using only the first conductor 71 and the second conductor near the joining surface 40 of the first semiconductor substrate 26 and the second semiconductor substrate 28. Further, in the vicinity of the joining surface 40, the area ratio of the region in contact with the joining surface 40 in the first conductor 71 is higher than the area ratio of the region in contact with the joining surface 40 in the second conductor 72, and the above area ratios are asymmetric. Therefore, according to the solid-state image sensor 31 and the manufacturing method thereof, wafer bonding of the conductive film having a high area ratio can be realized, and generation of voids in the bonding surface 40 can be suppressed. Further, suppressing the generation of voids in the bonding surface 40 can improve the image quality of the solid-state image sensor 31. Note that the area ratio of the region in contact with the joining surface 40 in the second conductor 72 may also be higher than the area ratio of the region in contact with the joining surface 40 in the first conductor 71 as long as the area ratios of the first conductor 71 and the second conductor 72 are different and asymmetric. The reason why the region not subjected to bonding is generated is: since the high area ratio of the copper electrode causes the velocity of the bonding wave at the time of bonding the wafer to become uneven, a relatively low bonding velocity occurs in a portion of the peripheral portion of the wafer and a region where bonding is not performed (i.e., a void) is formed. If the area ratio of the first conductor 71 and the second conductor 72 is symmetrical, the area ratio of the conductors becomes higher on both the upper substrate side and the lower substrate side. In this case, the velocity of the joining wave becomes uneven. Meanwhile, if the area ratio is made asymmetric to reduce the area ratio of one of the conductors, the unevenness in the velocity of the joining wave is solved and the generation of voids can be suppressed. When the generation of voids is suppressed and the shielding layer 68 is formed, noise can be eliminated, so that image quality can be improved.

Note that, near the joining surface 40, a dummy conductor may be arranged instead of the first conductor 71 or the second conductor 72. In the manufacturing process, when a surface including dummy devices (dummy) is planarized by a CMP apparatus, flatness can be ensured by disposing dummy conductors. Further, the plurality of first conductors 71 and second conductors 72 may be arranged to cover 30% or more of the vertical signal lines, or may be advantageously arranged to cover 50% or more of the vertical signal lines. By covering the vertical signal lines at the above ratio, the bonding strength of the semiconductor substrate can be improved, and generation of voids in the bonding portion of the semiconductor substrate can be suppressed. With this configuration, deterioration in image quality can be prevented (or alternatively reduced).

If the area ratio of both the first conductor 71 and the second conductor 72 is made high, the velocity of the bonding wave at the time of wafer-to-wafer bonding becomes uneven, and therefore, a relatively low bonding velocity occurs in a part of the peripheral portion of the wafer, and a region where bonding is not performed (i.e., a void) is formed. Therefore, in order to make the ratio of the conductors of the joining surfaces high, it is necessary to reduce the ratio of the other conductor. Here, "changing the occupation ratio of the upper and lower conductors" is expressed as "causing asymmetry". In addition, in order to enhance the bonding strength, it is necessary to secure a region where the insulating film and the insulating film are bonded to some extent.

The surface occupation ratio (area ratio) of the conductor having a large area in contact with the joining surface needs to be set to 30% to 90%. Further, it is effective to set the surface occupancy ratio of the conductor having a smaller area in contact with the joining surface to 0 to 50%. Desirably, if the surface occupation ratio of the conductor having a large area is set to 40 to 70%, and the surface occupation ratio of the conductor having a small area is set to 0 to 30%, the generation of voids at the time of bonding can be more effectively suppressed. Further, it is optimal (or desirable) to set the surface occupancy ratio of the conductor having a larger proportion to 55%.

Further, the width of the conductor at this time is desirably set to 10 μm or less. Desirably, if the width of the conductor is set to 1 μm or less, generation of voids at the time of bonding can be more effectively suppressed.

Further, according to the solid-state image sensor 31 and the manufacturing method thereof of the present embodiment, the shielding layer 68 made of the metals M4 and M14, which is located in the same layer as the connection wirings 36 and 58, is formed in the vicinity of the junction of the first semiconductor substrate 26 and the second semiconductor substrate 28. By virtue of the shielding layer 68, entry of light emission toward the first semiconductor substrate 26 side due to hot carriers from the MOS transistors of the logic circuit 55 of the second semiconductor substrate 28 can be suppressed. Therefore, an adverse effect of light emission due to hot carriers is suppressed. Therefore, dark current and random noise can be suppressed.

Further, according to the solid-state image sensor 31 and the manufacturing method thereof of the present embodiment, the shielding layer 68 is formed of the metals M4 and M14 located in the same layer as the connection wirings 36 and 58. Therefore, the thickness of the entire semiconductor substrate to be bonded can be made smaller than that of the conventional technique, and the solid-state image sensor 31 can be formed as a thinner film. With this configuration, the solid-state image sensor 31 having a small dark current and random noise can be provided without increasing the thickness of the entire semiconductor substrate.

Further, according to the solid-state image sensor 31 and the manufacturing method thereof of the present embodiment, the wiring, the connection wiring, and the shielding layer can be formed simultaneously. Therefore, the manufacturing steps can be reduced, the mask process can be reduced, and the material cost can be reduced, and a solid-state image sensor having small dark current and random noise can be manufactured at low cost.

<4 > solid-state image sensor of second embodiment

Fig. 17A is an enlarged configuration diagram illustrating a shielding portion 71 of the first semiconductor substrate 26 of the second embodiment. Fig. 17B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the second embodiment. A second embodiment of a solid-state image sensor according to an embodiment of the present invention will be described using fig. 17A and 17B.

The present embodiment is different from the first embodiment in fig. 6A and 6B in that: a plurality of vertical stripe shapes of the shielding portions 71 in the first semiconductor substrate 26 are arranged between bundles of adjacent vertical signal lines M3 or between FDs of pixel units. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment. Further, in the solid-state image sensor 31 of the present embodiment, the shielding portion 71 is formed in a plurality of stripe shapes, so that the width of one stripe can be narrowed. Therefore, the generation of the joint gap can be further suppressed.

<5 > solid-state image sensor of third embodiment

Fig. 18A is an enlarged configuration diagram illustrating a shielding portion 71 of the first semiconductor substrate 26 of the third embodiment. Fig. 18B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the third embodiment. A third embodiment of the solid-state image sensor according to the present invention will be described using fig. 18A and 18B.

Similar to the second embodiment, the present embodiment is different from the first embodiment in fig. 6A and 6B in that: a plurality of vertical stripe shapes of the shielding portions 71 in the first semiconductor substrate 26 are arranged between bundles of adjacent vertical signal lines M3 or between FDs of pixel units. Another difference between the present embodiment and the first embodiment in fig. 6A and 6B is that: the horizontal stripe shape is not formed in the shielding portion 71 in the first semiconductor substrate 26. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment. Further, the solid-state image sensor 31 of the present embodiment can reduce the surface occupation ratio of the shielding portion 71, as compared with the shielding portion 71 in the first semiconductor substrate 26 of the second embodiment. Therefore, the generation of the joint gap can be further suppressed.

<6 > solid-state image sensor of fourth embodiment

Fig. 19A is an enlarged configuration diagram illustrating a shielding portion 71 of the first semiconductor substrate 26 of the fourth embodiment. Fig. 19B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the fourth embodiment. A fourth embodiment of the solid-state image sensor according to the present invention will be described using fig. 19A and 19B.

The present embodiment is different from the first embodiment in fig. 6A and 6B in that: the plurality of vertical stripe shapes of the shielding portion 71 in the first semiconductor substrate 26 are not formed. Another difference between the present embodiment and the first embodiment in fig. 6A and 6B is that: the horizontal stripe shape is not formed in the shielding part 72 in the second semiconductor substrate 28, and the vertical stripe shape similar to the second embodiment in fig. 17A is formed in the shielding part 72. In the present embodiment, the upper surface of the first semiconductor substrate 26 in fig. 19A and the upper surface of the second semiconductor substrate 28 in fig. 19B are bonded in a face-to-face manner to manufacture the solid-state image sensor 31. At this time, the shielding portions 71 and 72 are joined to finally form the mesh-like shielding layer 68 conductor. Therefore, after the wafer bonding, the shielding portion 71 and the shielding portion 72 which are in contact with each other have the same potential. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment.

<7 > solid-state image sensor of fifth embodiment

Fig. 20A is an enlarged configuration diagram illustrating a shielding portion 71 of the first semiconductor substrate 26 of the fifth embodiment. Fig. 20B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the fifth embodiment. A fifth embodiment of the solid-state image sensor according to the present invention will be described using fig. 20A and 20B.

The shielding portion 71 in the first semiconductor substrate 26 of the present embodiment has a similar configuration to the shielding portion 71 of the second embodiment in fig. 17A. Meanwhile, the shielding portion 72 in the second semiconductor substrate 28 of the present embodiment is different from the shielding portion 72 of the second embodiment in fig. 17B in that: a rectangular (including square) shape is formed in a dot manner near the center of the pixel unit. The solid-state image sensor 31 of the present embodiment is formed with the shielding portion 72 of a low area ratio, and therefore, the bonding strength of the semiconductor substrate can be further improved as compared with the solid-state image sensors 31 of the first to fourth embodiments.

<8 > solid-state image sensor of sixth embodiment

Fig. 21A is an enlarged configuration diagram illustrating a shielding portion 71 of a first semiconductor substrate 26 of the sixth embodiment. Fig. 21B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the sixth embodiment. A sixth embodiment of the solid-state image sensor according to the present invention will be described using fig. 21A and 21B.

As shown in fig. 21A, the shielding portion 71 of the present embodiment is formed in a layout such that: the plurality of horizontal stripe shapes are arranged at a predetermined pitch in a direction perpendicular to the bundle of the vertical signal lines M3. Further, as shown in fig. 21B, the shielding portion 72 of the present embodiment is formed in a layout such that: the vertical stripe shape is arranged at a position covering the bundle of the vertical signal lines M3 when the first semiconductor substrate 26 and the second semiconductor substrate 28 are bonded. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment.

<9 > solid-state image sensor of seventh embodiment >

Fig. 22A is an enlarged configuration diagram illustrating a shielding portion 71 of the first semiconductor substrate 26 of the seventh embodiment. Fig. 22B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the seventh embodiment. A seventh embodiment of the solid-state image sensor according to the present invention will be described using fig. 22A and 22B.

As shown in fig. 22A, similarly to the sixth embodiment in fig. 21A, the shielding portion 71 of the present embodiment is formed in a layout such that: a plurality of horizontal stripe shapes are arranged at a predetermined pitch in a direction perpendicular to the bundle of the vertical signal lines M3. Further, as shown in fig. 21B, the shielding portion 72 of the present embodiment is formed in a layout such that: a plurality of rectangular (including square) shapes are randomly arranged on the surface of the second semiconductor substrate 28. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment.

<10 > solid-state image sensor of eighth embodiment

Fig. 23A is an enlarged configuration diagram illustrating a shielding portion 71 of a first semiconductor substrate 26 of the eighth embodiment. Fig. 23B is an enlarged configuration diagram illustrating the shielding portion 72 of the second semiconductor substrate 28 of the eighth embodiment. An eighth embodiment of the solid-state image sensor according to the present invention will be described using fig. 23A and 23B.

As shown in fig. 23A, the shielding portion 71 of the present embodiment is formed in a layout such that: the plurality of diagonal stripe shapes are arranged at a predetermined pitch in a direction intersecting the beam of the vertical signal line M3 in such a manner as to be inclined from the upper right to the lower left in fig. 23A. With this layout, the shielding portion 71 of the present embodiment partially covers the vertical signal line M3. Further, as shown in fig. 21B, the shielding portion 72 of the present embodiment is formed in a layout such that: arranged in a diagonal stripe shape inclined from upper left to lower right in fig. 23B. Note that the shielding portions 71 and 72 of the present embodiment may not be arranged according to the arrangement interval of the bundles of the vertical signal lines M3 or the FD pitch of the pixel unit. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment.

<11 > solid-state image sensor of ninth embodiment >

Fig. 24A is an enlarged configuration diagram illustrating a shielding portion 71 of a first semiconductor substrate 26 of the ninth embodiment. Fig. 24B is an enlarged configuration diagram illustrating a shielding portion 72 of the second semiconductor substrate 28 of the ninth embodiment. A ninth embodiment of the solid-state image sensor according to the present invention will be described using fig. 24A and 24B.

As shown in fig. 24A, the shielding portion 71 of the present embodiment is formed in a layout such that: a plurality of rectangular (including square) shapes are arranged in a lattice pattern on the surface of the first semiconductor substrate 26. Further, as shown in fig. 24B, the shielding portion 72 of the present embodiment is formed in a layout such that: similarly to the first embodiment, the interlayer insulating film 66 is included and the horizontal stripe shape is arranged at a position overlapping with the shielding portion 71 when viewed from above. The solid-state image sensor 31 of the present embodiment has effects similar to those of the solid-state image sensor 31 of the first embodiment. Note that not only the plurality of squares of the shielding portions 71 may be arranged in the direction parallel to and perpendicular to the vertical signal line M3, but also the plurality of squares of the shielding portions 71 may be arranged in a direction diagonally inclined with respect to the vertical signal line M3.

<12 > solid-state image sensor of tenth embodiment

A tenth embodiment of the solid-state image sensor according to the present invention will be described using fig. 25. The present embodiment is different from the first embodiment in fig. 16 in that: two layers of the second semiconductor substrate 54 are stacked in the second semiconductor substrate 28. The wiring 57c of the interlayer insulating film and the wiring 57c of the second semiconductor substrate 54 bonded to the interlayer insulating film are electrically connected to the wiring 904. In addition to having similar effects to the solid-state image sensor 31 of the first embodiment, the solid-state image sensor 31 of the present embodiment can further achieve high performance of the image sensor and miniaturization of the chip size by laminating substrates having various functions with three semiconductor substrates. Note that the number of stacked semiconductor substrates of the solid-state image sensor according to the embodiment of the present invention is not limited to three or less, but may be four or more.

<13 > electronic device of eleventh embodiment

An eleventh embodiment of the solid-state image sensor according to the present invention will be described using fig. 26. Fig. 26 illustrates an electronic device according to an embodiment of the invention. The above-described solid-state image sensor according to an embodiment of the present invention can be applied to electronic devices such as: camera systems such as digital cameras and video cameras, mobile phones having an imaging function, and other devices having an imaging function, and the like.

Fig. 26 illustrates an eleventh embodiment applied to a camera as an example of an electronic apparatus according to the present invention. The camera according to the present embodiment is a video camera capable of taking still images or moving images. The camera 201 according to the present embodiment includes: a solid-state image sensor 202; an optical system 203 that guides incident light into a light receiving section of the solid-state image sensor 202; and a shutter device 204. Further, the camera 201 includes: a driving circuit 205 that drives the solid-state image sensor 202; and a signal processing circuit 206 that processes an output signal of the solid-state image sensor 202.

Any of the solid-state image sensors of the above embodiments is applied to the solid-state image sensor 202. An optical system (optical lens) 203 images image light (incident light) from an object on an imaging surface of the solid-state image sensor 202. By the above-described imaging, the signal charges are accumulated in the solid-state image sensor 202 for a fixed time. The optical system 203 may be an optical lens system composed of a plurality of optical lenses. The shutter device 204 controls the light illumination period and the light shielding period of the solid-state image sensor 202. The drive circuit 205 supplies a drive signal that controls the transfer operation of the solid-state image sensor 202 and the shutter operation of the shutter device 204. The signal transmission of the solid-state image sensor 202 is performed by a driving signal (timing signal) supplied from the driving circuit 205. The signal processing circuit 206 performs various types of signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or is output to a monitor.

An electronic device according to the eleventh embodiment includes the back-illuminated solid-state image sensor 202 in the present invention described above. Therefore, light emission due to hot carriers from the MOS transistor of the logic circuit does not enter the pixel array side, and dark current and random noise can be suppressed. Therefore, an electronic device with high image quality can be provided. For example, a camera with improved image quality can be provided.

Note that the embodiment of the present invention is not limited to the above-described embodiment, but can be variously changed without departing from the spirit of the present invention. For example, an embodiment in which all or part of the above-described plurality of embodiments are combined can be employed. Further, for example, each layout of the shielding portions of the first chip presented in fig. 6A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, and 24A may be combined with any layout of the shielding portions of the second chip presented in fig. 6B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B.

Further, the present invention can adopt the following configuration.

(1) A solid-state image sensor, comprising:

a first semiconductor substrate in which a first insulating film and a pixel array are formed; and a second semiconductor substrate bonded to the first semiconductor substrate, in which a second insulating film and a logic circuit are formed, wherein

A conductor is formed in at least one of the first insulating film and the second insulating film

A region where the first insulating film and the second insulating film are connected is included in a bonding surface of the first semiconductor substrate and the second semiconductor substrate.

(2) The solid-state image sensor according to (1), wherein

A first conductor and a second conductor are formed in the first insulating film and the second insulating film, respectively, and the first conductor and the second conductor overlap each other on the junction surface.

(3) The solid-state image sensor according to (2), wherein

The surface occupancy ratio of a region of the first conductor in contact with the bonding surface is different from the surface occupancy ratio of a region of the second conductor in contact with the bonding surface.

(4) The solid-state image sensor according to (2), wherein

Among the first conductor and the second conductor overlapping each other, a surface occupancy ratio of the first conductor or the second conductor having a larger area in contact with the joining surface is 30 to 90%.

(5) The solid-state image sensor according to (2), wherein

Among the first conductor and the second conductor overlapping each other, a surface occupancy ratio of the first conductor or the second conductor having a larger area in contact with the joining surface is 40 to 70%.

(6) The solid-state image sensor according to (2), wherein

Among the first conductor and the second conductor overlapping each other, a surface occupancy ratio of the first conductor or the second conductor having a smaller area in contact with the joining surface is 0 to 50%.

(7) The solid-state image sensor according to (2), wherein

Among the first conductor and the second conductor overlapping each other, a surface occupancy ratio of the first conductor or the second conductor having a smaller area in contact with the joining surface is 0 to 30%.

(8) The solid-state image sensor according to (1), wherein a length of the conductor in contact with the bonding surface in a width direction is 10um or less.

(9) The solid-state image sensor according to (1), wherein a length of the conductor in contact with the bonding surface in a width direction is 1um or less.

(10) The solid-state image sensor according to (1), wherein

The first semiconductor substrate has a wiring and a connection hole for potential-clamping the conductor formed therein.

(11) The solid-state image sensor according to (1), wherein

The second semiconductor substrate has a wiring line and a connection hole for potential-clamping the conductor formed therein.

(12) The solid-state image sensor according to (1), wherein

Wiring lines and connection holes for potential-clamping the conductors are formed in both the first semiconductor substrate and the second semiconductor substrate.

(13) The solid-state image sensor according to (1), wherein

The size of the conductor covering the planar shape of the pixel array is the size of the planar shape of the pixel array or larger.

(14) The solid-state image sensor according to (1), wherein

The conductor is arranged to cover at least a part of a signal line of an analog circuit in a direction of the bonding surface with respect to the signal line.

(15) The solid-state image sensor according to (14), wherein

The conductor is arranged to cover 30% or more of the signal line.

(16) The solid-state image sensor according to (14), wherein

The conductor is arranged to cover 50% or more of the signal line.

(17) The solid-state image sensor according to (14), wherein

A plurality of conductors arranged according to the arrangement interval of the signal lines are formed.

(18) The solid-state image sensor according to (14), wherein

A plurality of conductors are formed, and the arrangement direction of the plurality of conductors is an oblique direction with respect to the direction of the signal line.

(19) A method of manufacturing a solid-state image sensor, the method comprising the steps of:

forming a first insulating film and a pixel array in a first semiconductor substrate;

forming a second insulating film and a logic circuit in a second semiconductor substrate;

forming a conductor in at least one of the first insulating film and the second insulating film; and

bonding the first semiconductor substrate and the second semiconductor substrate, wherein

A region where the first insulating film and the second insulating film are connected is included in a bonding surface of the first semiconductor substrate and the second semiconductor substrate.

(20) An electronic device, comprising:

a first semiconductor substrate in which a first insulating film and a pixel array are formed; and a second semiconductor substrate bonded to the first semiconductor substrate, the second semiconductor substrate having a second insulating film and a logic circuit formed therein, wherein

A conductor is formed in at least one of the first insulating film and the second insulating film

A region where the first insulating film and the second insulating film are connected is included in a bonding surface of the first semiconductor substrate and the second semiconductor substrate.

(21) An imaging device, comprising:

a first chip, the first chip comprising:

a first semiconductor substrate including a photoelectric conversion region that converts incident light into electric charges; and

a first insulating layer including a first multi-layer wiring electrically connected to the photoelectric conversion region, wherein the first multi-layer wiring includes a first vertical signal line that outputs a first pixel signal based on the electric charges and a first connection region including a first wiring; and

a second chip, the second chip comprising:

a second semiconductor substrate including a logic circuit for processing the first pixel signal; and

a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit, wherein the second multi-layered wiring includes a second connection region including a second wiring,

wherein the first chip and the second chip are bonded to each other via at least the first wiring and the second wiring, and

wherein the first wiring and the second wiring overlap with at least a part of the first vertical signal line in a plan view.

(22) The imaging device according to (21), wherein a part of the first insulating layer and a part of the second insulating layer are bonded to each other.

(23) The imaging device according to (21) or (22), wherein the first vertical signal line extends in a first direction, and wherein the first wiring includes a first portion that extends in the first direction and overlaps with the first vertical signal line in the plan view.

(24) The imaging device according to (23), wherein a width of the first portion measured in a second direction is larger than a width of the first vertical signal line measured in the second direction, and wherein the second direction is perpendicular to the first direction.

(25) The imaging device according to (23) or (24), wherein the first portion overlaps with an entire width of the first vertical signal line over an entire length of the first portion in the first direction in the plan view.

(26) The imaging device according to any one of (23) to (25), wherein the first wiring includes: a second portion extending in a second direction perpendicular to the first direction.

(27) The imaging device according to any one of (23) to (26), wherein the second wiring extends in the second direction.

(28) The imaging device according to (27), wherein a width of the second wiring in the first direction is larger than a width of a second portion of the first wiring in the first direction in the plan view.

(29) The imaging device according to (28), wherein the second wiring overlaps with a second portion of the first wiring in the plan view.

(30) The imaging device according to (28) or (29), wherein the second wiring overlaps with an entirety of the second portion of the first wiring in the plan view.

(31) The imaging device according to (21) or (22), wherein the first vertical signal line extends in a first direction, and wherein the first wiring extends in a second direction perpendicular to the first direction, and wherein the second wiring extends in the first direction and overlaps with the first vertical signal in the plan view.

(32) The imaging device according to (31), wherein the second wiring overlaps with all of the first vertical signal lines over an entire length of the first portion in the plan view.

(33) An imaging device, comprising:

a first chip, the first chip comprising:

a first semiconductor substrate including a plurality of pixel regions arranged in a matrix form and converting incident light into charges; and

a first insulating layer including a first multi-layered wiring electrically connected to the plurality of pixel regions, wherein the first multi-layered wiring includes: a plurality of vertical signal lines that output respective pixel signals based on the charges; and a first connection region including at least one first wire; and

a second chip, the second chip comprising:

a second semiconductor substrate including a logic circuit for processing the pixel signal; and

a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit, wherein the second multi-layered wiring includes a second connection region including at least one second wiring,

wherein the first chip and the second chip are bonded to each other via at least the at least one first wiring and the at least one second wiring, and

wherein the at least one first wiring and the at least one second wiring overlap with the plurality of vertical signal lines in a plan view.

(34) The imaging device according to (33), wherein the plurality of vertical signal lines extend in a first direction and are arranged at regular first intervals in a second direction perpendicular to the first direction in the first multilayer wiring, and wherein the at least one first wiring is a plurality of first wirings including first portions extending in the first direction and arranged at regular second intervals in the second direction in the first multilayer wiring.

(35) The imaging device of (34), wherein the first regular interval and the second regular interval correspond to a pitch between two of the plurality of pixel regions.

(36) The imaging device of (34), wherein the first regular interval corresponds to a pitch between two of the plurality of pixel regions, and the regular second interval corresponds to half the pitch.

(37) The imaging device according to any one of (34) to (36), wherein the plurality of first wirings include second portions extending in the second direction.

(38) The imaging device according to any one of (33) to (37), wherein the at least one wiring is a plurality of second wirings including a first portion extending in a first direction, and wherein the at least one first wiring extends in a second direction perpendicular to the first direction.

(39) The imaging device according to any one of (33) to (38), wherein the at least one second wiring includes second wiring portions for respective ones of the plurality of pixel regions.

(40) An electronic device, comprising:

an imaging device, the imaging device comprising:

a first chip, the first chip comprising:

a first semiconductor substrate including a photoelectric conversion region that converts incident light into electric charges; and

a first insulating layer including a first multi-layer wiring electrically connected to the photoelectric conversion region, wherein the first multi-layer wiring includes a first vertical signal line that outputs a first pixel signal based on the electric charges and a first connection region including a first wiring; and

a second chip, the second chip comprising:

a second semiconductor substrate including a logic circuit for processing the first pixel signal; and

a second insulating layer including a second multi-layered wiring electrically connected to the logic circuit, wherein the second multi-layered wiring includes a second connection region including a second wiring,

wherein the first chip and the second chip are bonded to each other via at least the first wiring and the second wiring, and

wherein the first wiring and the second wiring overlap with at least a part of the first vertical signal line in a plan view.

List of reference numerals

1, 1a to 1c, 31 solid-state image sensor

2 pixels

3, 23, 34 pixel array (pixel region)

4 vertical driving circuit

5-column signal processing circuit

6 horizontal driving circuit

7 output circuit

8, 24, 24-1, 24-2 control circuit

9, VSL1 vertical signal line

10 horizontal signal line

21, 33 first semiconductor substrate

22, 54 second semiconductor substrate

25, 55 logic circuit

26 first semiconductor substrate

28 second semiconductor substrate

30, 50 semiconductor well region

32 laminated semiconductor substrate

33a surface

35a to 35d, 36, 57a to 57c, 58, 904 wiring

37, 59 multilayer wiring layer

38 insulating layer

39 light shielding film

40 engaging surface

41 optical black area

42 effective pixel array

43 Flat film

44 color filter

45 lens on semiconductor substrate

47, 48P type semiconductor region

49, 61 source/drain regions

51, 63 element isolation region

52, 64 conductive vias

53, 56, 66 interlayer insulating film

62 grid electrode

68 masking layer

71 shielding part (first conductor)

72 shielding part (second conductor)

75, 81Cu diffusion barrier insulating film

76, 82 first insulating layer

77, 83 second insulating layer

78, 79, 84, 85 opening part

80, 86 through hole

900, 901 insulating film

PD photodiode

Tr1, Tr2 pixel transistor

M1 to M4, M11 to M14 metals

FD Floating diffusion region

Tr 11-Tr 14 MOS transistor