阅读说明：本技术 一种基于晶体管的电阻结构及其制作方法 (Transistor-based resistor structure and manufacturing method thereof ) 是由 陈智广 吴淑芳 林伟铭 于 2019-08-23 设计创作，主要内容包括：本发明公开一种基于晶体管的电阻结构及其制作方法,其中方法包括如下步骤：在具有栅极金属、源极金属、漏极金属、第一层氮化物以及第一层金属连线的器件上沉积第二层氮化物；对源极金属、漏极金属位置的第二层氮化物进行蚀刻开口；沉积平坦化层,对源极金属、漏极金属位置的平坦化层进行蚀刻开口；沉积第二层金属,使得第二层金属连接源极第一层金属和漏极第一层金属。本技术方案具有如下优点：优点1：省去了现有制备高值电阻的工艺步骤,可有效降低制造成本,同时因工艺步骤减少可在一定程度上提高制程稳定性。优点2：制备出高值的电阻占用外延面积较小。(The invention discloses a transistor-based resistor structure and a manufacturing method thereof, wherein the method comprises the following steps: depositing a second layer of nitride on the device having the gate metal, the source metal, the drain metal, the first layer of nitride, and the first layer of metal lines; etching openings of the second layer of nitride at the positions of the source metal and the drain metal; depositing a planarization layer, and etching openings of the planarization layer at the positions of the source metal and the drain metal; and depositing a second layer of metal, so that the second layer of metal is connected with the source electrode first layer of metal and the drain electrode first layer of metal. The technical scheme has the following advantages: the method has the advantages that: the existing process step for preparing the high-value resistor is omitted, the manufacturing cost can be effectively reduced, and the process stability can be improved to a certain extent due to the reduction of the process step. The method has the advantages that: the prepared high-value resistor occupies a small epitaxial area.)

1. A method for manufacturing a resistor structure based on a transistor is characterized by comprising the following steps:

depositing a second layer of nitride on the device having the gate metal, the source metal, the drain metal, the first layer of nitride, and the first layer of metal lines;

etching openings of the second layer of nitride at the positions of the source metal and the drain metal;

depositing a planarization layer, and etching openings of the planarization layer at the positions of the source metal and the drain metal;

and depositing a second layer of metal, so that the second layer of metal is connected with the source electrode first layer of metal and the drain electrode first layer of metal.

2. The method of claim 1, wherein fabricating the device comprises:

depositing a source metal and a drain metal on the wafer;

etching to remove the cap layer at the position of the grid electrode;

depositing a gate metal at the gate location;

depositing a first layer of nitride, and etching openings at the positions of the source metal and the drain metal;

a first layer of metal is deposited at the openings at the location of the source and drain metals.

3. The method of claim 1, further comprising the steps of:

a third layer of nitride is deposited.

4. A method of fabricating a transistor-based resistor structure according to any of claims 1 to 3, characterized by: the number of the devices is more than two, and the step of depositing the second layer of metal to enable the second layer of metal to be connected with the first layer of metal of the source electrode and the first layer of metal of the drain electrode comprises the following steps:

depositing a second layer of metal connected with the first layer of metal of the source and drain of one device;

and depositing a separate second layer of metal at the source and drain first layer of metal location of the other device.

5. A method of fabricating a transistor-based resistor structure according to any of claims 1 to 3, characterized by: the transistor is a pseudomorphic modulation doped heterojunction field effect transistor.

6. A transistor-based resistor structure, characterized in that it is produced by a method for manufacturing a transistor-based resistor structure according to any one of claims 1 to 5.

Technical Field

The invention relates to the field of wafer resistor manufacturing, in particular to a resistor structure based on a transistor and a manufacturing method thereof.

Background

The pHEMT (pseudomorphic modulation doped heterojunction field effect transistor) device has wide application in the radio frequency field, but in some cases, the pHEMT needs to be matched with a high-value resistor to match an application circuit. On the premise of the pHEMT epitaxial structure, the current methods for manufacturing high-value resistors generally include the following two methods: firstly, the method comprises the following steps: the number of carriers of the epitaxial structure in a specific region is reduced through ion implantation so as to achieve the effect of large resistance; second, the conductive path of the current in a certain region is changed by etching to increase the resistance, generally, a groove is etched on the cap layer with excellent conductivity, and the conductive path of the conductive carriers on the surface (cap layer) of the device is cut off, so that the conductive carriers are forced to conduct in the semiconductor region with higher resistance value under the cap layer.

The above solution has the following disadvantages: the method has the disadvantages that when the high-value resistor is prepared, the consumed epitaxial structure area is large, so that the device integration level of the wafer is reduced, and the cost is increased. The disadvantages 2 and the above methods all require additional process steps besides the fabrication of the pherm device to realize high-value resistance, which increases the process cost.

Disclosure of Invention

Therefore, it is necessary to provide a transistor-based resistor structure and a manufacturing method thereof, so as to solve the problems of complex process and large occupied epitaxial area in the existing high-value resistor manufacturing process.

To achieve the above object, the inventor provides a method for manufacturing a transistor-based resistor structure, comprising the following steps:

depositing a second layer of nitride on the device having the gate metal, the source metal, the drain metal, the first layer of nitride, and the first layer of metal lines;

etching openings of the second layer of nitride at the positions of the source metal and the drain metal;

depositing a planarization layer, and etching openings of the planarization layer at the positions of the source metal and the drain metal;

and depositing a second layer of metal, so that the second layer of metal is connected with the source electrode first layer of metal and the drain electrode first layer of metal.

Further, the manufacturing of the device comprises the following steps:

depositing a source metal and a drain metal on the wafer;

etching to remove the cap layer at the position of the grid electrode;

depositing a gate metal at the gate location;

depositing a first layer of nitride, and etching openings at the positions of the source metal and the drain metal;

a first layer of metal is deposited at the openings at the location of the source and drain metals.

Further, the method also comprises the following steps:

a third layer of nitride is deposited.

Further, the number of the devices is more than two, and the depositing the second layer of metal to enable the second layer of metal to be connected with the first source layer of metal and the first drain layer of metal comprises the following steps:

depositing a second layer of metal connected with the first layer of metal of the source and drain of one device;

and depositing a separate second layer of metal at the source and drain first layer of metal location of the other device.

Further, the transistor is a pseudomorphic modulation doped heterojunction field effect transistor.

The invention provides a resistor structure based on a transistor, which is manufactured by the manufacturing method of the resistor structure based on the transistor in any one embodiment.

Different from the prior art, the technical scheme has the following advantages: the method has the advantages that: the existing process step for preparing the high-value resistor is omitted, the manufacturing cost can be effectively reduced, and the process stability can be improved to a certain extent due to the reduction of the process step. The method has the advantages that: the prepared high-value resistor occupies a small epitaxial area.

Drawings

Fig. 1 is a schematic view of an epitaxial structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a source/drain metal deposition process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an etched cap layer at a gate location according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a gate metal deposited according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a structure of a first layer of nitride after deposition and etching in accordance with one embodiment of the present invention;

FIG. 6 is a schematic structural diagram illustrating a first metal interconnection after fabrication according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a second layer of nitride after deposition according to one embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a structure of a second nitride layer after etching according to an embodiment of the present invention;

FIG. 9 is a polymer-coated planarization layer structure in accordance with one embodiment of the present invention;

FIG. 10 is a schematic diagram of a polymer structure after etching according to one embodiment of the present invention;

FIG. 11 is a schematic structural diagram illustrating a second metal interconnection after fabrication according to an embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating a structure of a third layer of nitride after deposition according to one embodiment of the present invention;

fig. 13 is a graph of electrical characteristics of a fabricated device in accordance with an embodiment of the present invention.

Description of reference numerals:

1. a wafer;

20. a substrate, 21, a buffer layer, 22, a channel layer, 23, a barrier layer, 24 and a cap layer;

2. a source metal;

3. a drain metal;

4. a gate location;

5. a gate metal;

6. a first layer of nitride;

7. a first layer of a metal, a second layer of a metal,

8. a second layer of nitride;

9. a second layer of nitride openings;

10. a planarization layer;

11. a planarization layer opening;

12. a second layer of metal;

13. and a third layer of nitride.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 13, the present embodiment provides a method for manufacturing a transistor-based resistor structure, and the main improvement of the present invention is that a resistor can be simultaneously manufactured during the manufacturing process of the transistor, and the resistor is mainly manufactured by connecting a second metal layer to a first metal layer. The transistor may be a pHEMT (pseudomorphic doped heterojunction field effect transistor) as long as it has source, drain and gate metals.

The embodiment provides a complete process step, which specifically comprises the following steps: firstly, cleaning a wafer to remove foreign matters on the surface of the wafer, wherein the epitaxial structure of the wafer 1 comprises a substrate 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 from bottom to top in sequence as shown in fig. 1. Then, a source metal 2 and a drain metal 3 are deposited on the wafer, and the structure is shown in fig. 2. The method specifically comprises photoresist coating, source/drain pattern definition, photoresist development, metal deposition, photoresist removal, source/drain metal tempering and wafer cleaning. The cap layer at gate location 4 is then etched away and the structure is shown in figure 3. The specific process comprises photoresist coating, gate photoresist pattern definition, photoresist development and cap layer etching. The gate metal 5 continues to be deposited at the gate location and the structure is shown in figure 4. The method specifically comprises the steps of gate metal deposition, photoresist removal and wafer cleaning. A first layer of nitride 6, which may be silicon nitride, is deposited and openings are etched at the location of the source and drain metals, as shown in figure 5. A first layer of metal 7 is deposited at the openings at the location of the source and drain metals, the structure being shown in figure 6. The above process steps can produce a device having a gate metal, a source metal, a drain metal, a first layer of nitride, and a first layer of metal interconnects, i.e., a basic transistor device. Of course, the above embodiment is merely an example, and the device structure is not limited to be manufactured by the above steps.

A second layer of nitride 8 is deposited on top of the device described above and the structure is shown in figure 7. The second layer of nitride at the location of the source metal and the drain metal is etched to form an opening 9, as shown in fig. 8. A planarization layer 10 is deposited and the structure is shown in fig. 9, and the planarization layer at the location of the source metal and the drain metal is etched to form an opening 11, which is shown in fig. 10. A second metal layer 12 is deposited so that the second metal layer connects the source first metal layer and the drain first metal layer, and the structure is shown in fig. 11. The method specifically comprises the following steps: coating and developing the photoresist to remove the photoresist above the first layer of metal and between the first layers of metal, depositing the second layer of metal, removing the photoresist and cleaning. In the existing transistor manufacturing process, generally, only the photoresist above the first layer of metal of the source and drain is removed by development, and then only the second layer of metal is deposited above the first layer of metal of the source and drain, that is, the existing process deposits the second layer of metal separately, and the second layer of metal is not connected with each other. Further, the method for protecting the device further comprises the following steps: a third layer of nitride 13 is deposited and the structure is shown in figure 12.

The device manufactured by the embodiment electrically connects the source electrode and the drain electrode by the second layer of metal connecting wire, and if a reverse bias voltage is added on the grid electrode, the device presents high-value resistance with the size changing along with the change of the grid electrode voltage before breakdown. The transistor device is essentially converted into the effect similar to a diode by virtue of the Schottky contact formed by the grid electrode and the Schottky layer, so that the characteristic of high resistance of the diode in a reverse working region can be effectively utilized. To form a good schottky contact, the barrier layer is typically selected from a large energy gap material, typically AlGaAs, but not limited to AlGaAs.

In addition, the present embodiment focuses on the schottky diode manufactured by using the transistor structure to utilize the characteristic of large resistance, and therefore, the epitaxial structure is not described. The buffer layer typically comprises a superlattice buffer layer, the channel layer typically comprises upper and lower Spacer layers and upper and lower electron-providing layers, and the barrier layer material may be a combination of materials.

The electrical characteristics of the device prepared by the process are shown in fig. 13, and it can be seen that the resistance value can reach the maximum when the gate is connected with a reverse bias voltage of 2V, and meanwhile, the resistance value of the device can also be obtained from the figure, the resistance value of the device changes along with the change of the bias voltage of the gate, and the gate voltage can be flexibly set according to the requirements of users to obtain resistors with different values, but it needs to be provided that the device is prevented from being damaged due to the fact that the device works and breaks down in a breakdown region when the device is used.

The resistor structure provided by this embodiment may be fabricated separately or simultaneously with a transistor, so that a resistor is fabricated while the transistor structure is fabricated, the number of devices is two or more, and depositing the second layer of metal so that the second layer of metal connects the source first layer of metal and the drain first layer of metal includes: depositing a second layer of metal connected with the first layer of metal of the source and drain of one device to obtain the resistor structure; the method comprises the steps of depositing an independent second layer of metal on the first layer of metal position of the source and drain of another device to obtain a transistor structure, so that a transistor and a resistor structure can be obtained in one process, specifically, developing and removing the photoresist above the first layer of metal position of the source and drain of one device and the photoresist above the first layer of metal position of the source and drain and above the first layer of metal position of the source and drain of another device when the second layer of metal photoresist is developed, so that after one-time metal deposition, the independent second layer of metal and the connected second layer of metal can be deposited on one device without adding extra process steps.

The invention provides a resistor structure based on a transistor, which is manufactured by the manufacturing method of the resistor structure based on the transistor in any one embodiment. The resistor prepared by the invention occupies a smaller epitaxial area, and can be combined with the existing transistor process steps, so that the existing process step for preparing a high-value resistor is omitted, the manufacturing cost can be effectively reduced, and the process stability can be improved to a certain extent due to the reduction of the process steps.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.