阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 安国一 赵槿汇 河大元 河承锡 于 2019-07-05 设计创作，主要内容包括：一种半导体器件包括衬底、衬底上的栅极结构和栅极结构上的第一导电连接组。栅极结构包括栅极间隔件和栅电极。第一导电连接组包括铁电材料层。铁电材料层的至少一部分设置在栅极间隔件的上表面之上。(A semiconductor device includes a substrate, a gate structure on the substrate, and a first set of conductive connections on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first set of conductive connections includes a layer of ferroelectric material. At least a portion of the ferroelectric material layer is disposed over an upper surface of the gate spacer.)

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate, the gate structure comprising a gate spacer and a gate electrode; and

a first set of conductive connections on the gate structure, the first set of conductive connections comprising a layer of ferroelectric material,

wherein at least a portion of the ferroelectric material layer is disposed over an upper surface of the gate spacer.

2. The semiconductor device as set forth in claim 1,

wherein the first set of conductive connections is in contact with the gate electrode.

3. The semiconductor device of claim 2, further comprising:

a source/drain region disposed on a region adjacent to at least one side of the gate structure; and

source/drain contact plugs connected to the source/drain regions,

wherein the first conductive connection group includes a gate contact plug, and

an upper surface of the source/drain contact plug is located at substantially the same height as an upper surface of the gate contact plug is located from an upper surface of the substrate.

4. The semiconductor device as set forth in claim 1,

wherein the first conductive connection set includes a gate contact plug in contact with the gate electrode.

5. The semiconductor device as set forth in claim 4,

wherein the gate contact plug includes the ferroelectric material layer.

6. The semiconductor device as set forth in claim 5,

wherein the gate contact plug further comprises a blocking conductive layer and a filling conductive layer, and

the ferroelectric material layer is disposed between the barrier conductive layer and the fill conductive layer.

7. The semiconductor device as set forth in claim 4,

wherein the first conductive connection group further includes a first via plug and a first interlayer wiring, and

the first via plug is in contact with the gate contact plug.

8. The semiconductor device as set forth in claim 7,

wherein the first conductive connection group further includes a second via plug and a second interlayer wiring over the first interlayer wiring.

9. The semiconductor device as set forth in claim 4,

wherein the first conductive connection group further includes a via plug and an interlayer wiring on the gate contact plug, the via plug being in contact with the gate contact plug,

the via plug includes a first filled conductive layer, and

the interlayer wiring includes a second filled conductive layer connected to the first filled conductive layer.

10. The semiconductor device of claim 1, further comprising:

a source/drain region disposed in a region of the substrate adjacent to at least one side of the gate structure; and

a second set of conductive connections connected to the source/drain regions,

wherein the second set of conductive connections does not comprise a layer of ferroelectric material.

11. A semiconductor device, comprising:

a substrate;

a gate structure comprising a gate electrode on the substrate;

a source/drain region disposed in a region of the substrate adjacent to at least one side of the gate structure;

a first set of conductive connections on the gate electrode, the first set of conductive connections being connected to the gate electrode and comprising a layer of ferroelectric material; and

a second set of conductive connections connected to and disposed on the source/drain regions,

wherein the first conductive connection group includes a gate contact plug in contact with the gate electrode,

the second set of conductive connections includes source/drain contact plugs in contact with the source/drain regions,

an upper surface of the gate contact plug is located at substantially the same height as an upper surface of the source/drain contact plug from an upper surface of the substrate, and

a height from an upper surface of the gate structure to an uppermost surface of the ferroelectric material layer is equal to or greater than a height from an upper surface of the gate structure to an upper surface of the source/drain contact plug.

12. The semiconductor device as set forth in claim 11,

wherein the second set of conductive connections does not include a layer of ferroelectric material.

13. The semiconductor device as set forth in claim 11,

wherein the gate contact plug includes a ferroelectric material layer.

14. The semiconductor device as set forth in claim 11,

wherein the first conductive connection group includes via plugs and interlayer wirings connected with the gate contact plugs, and

the ferroelectric material layer is included in at least one of the via plug and the interlayer wiring.

15. A semiconductor device, comprising:

a substrate including an active region and a field region;

a first gate electrode on the substrate, the first gate electrode extending over the active region and the field region in a first direction; and

a first gate contact plug on the first gate electrode, the first gate contact plug being connected to the first gate electrode and including a ferroelectric material layer,

wherein a width of the first gate contact plug in the first direction is smaller than a width of the first gate electrode in the first direction.

16. The semiconductor device as set forth in claim 15,

wherein the first gate contact plug has a second width in a second direction crossing the first direction that is smaller than a first width in the first direction.

17. The semiconductor device as set forth in claim 15,

wherein the first gate contact plug has a second width in the second direction crossing the first direction greater than a first width in the first direction.

18. The semiconductor device as set forth in claim 15,

wherein the first gate contact plug is in contact with the first gate electrode.

19. The semiconductor device of claim 15, further comprising:

a via plug on the first gate contact plug; and

an insert wiring disposed between the first gate contact plug and the via plug.

20. The semiconductor device of claim 19, further comprising:

a second gate electrode extending over the active region and the field region in the first direction; and

a second gate contact plug on the second gate electrode,

wherein the insert wiring is further provided between the second gate contact plug and the via plug, and connects the second gate contact plug to the first gate contact plug.

Technical Field

The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a negative capacitor having a negative capacitance using a ferroelectric material.

Background

After the development of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), the integration of integrated circuits has been increasing. For example, the degree of integration of integrated circuits has indicated a trend of doubling the total number of transistors per unit chip area every two years. To increase the integration density of integrated circuits, the size of individual transistors is continually decreasing. In addition, semiconductor technologies for improving the performance of miniaturized transistors have emerged.

Among such semiconductor technologies, there may be a high-K metal gate (HKMG) technology that improves gate capacitance and reduces leakage current, and a FinFET technology that can improve SCE (short channel effect) in which the potential of a channel region is affected by a drain voltage.

However, the reduction in the drive voltage of the transistor is not significantly improved as compared with the miniaturization of the transistor size. As a result, the power density of Complementary Metal Oxide (CMOS) transistors increases exponentially. In order to reduce the power density, the power of the driving voltage must be reduced. However, it is difficult to achieve very low supply voltages because silicon-based MOSFETs have physical operating characteristics based on thermal emission.

For this reason, the necessity has arisen to develop transistors with sub-threshold swings below 60mV/decade (considered as the physical limit of sub-threshold swing (SS) at normal temperature) or lower.

Disclosure of Invention

According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate, a gate structure on the substrate, and a first set of conductive connections on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first set of conductive connections includes a layer of ferroelectric material. At least a portion of a layer of ferroelectric material is disposed over an upper surface of the gate spacer.

According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate; a gate structure comprising a gate electrode on the substrate; a source/drain region disposed in a region of the substrate adjacent to at least one side of the gate structure; a first conductive connection group disposed on and connected to the gate electrode; and a second set of conductive connections connected to and disposed on the source/drain regions. The first set of conductive connections includes a layer of ferroelectric material. The first conductive connection set includes a gate contact plug in contact with the gate electrode. A second set of conductive connections includes source/drain contact plugs in contact with the source/drain regions. An upper surface of the gate contact plug is located at substantially the same height as an upper surface of the source/drain contact plug is located from an upper surface of the substrate. The height from the upper surface of the gate structure to the uppermost surface of the ferroelectric material layer is equal to or greater than the height from the upper surface of the gate structure to the upper surface of the source/drain contact plug.

According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including an active region and a field region; a first gate electrode on the substrate, the first gate electrode extending over the active region and the field region in a first direction; and a first gate contact plug on the first gate electrode, the first gate contact plug being connected to the first gate electrode and including a ferroelectric material layer. The width of the first gate contact plug in the first direction is smaller than the width of the first gate electrode in the first direction.

Drawings

The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

fig. 1 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 2 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 3 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 4 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 5 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 6 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 7 is a cross-sectional view for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 8 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure;

fig. 9 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure;

FIGS. 10 to 12 are sectional views taken along line A-A, line B-B and line C-C in FIG. 9;

fig. 13a to 13e are diagrams for explaining example shapes that the upper surface of the second gate contact plug may have;

fig. 14 and 15 are diagrams for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 16 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 17 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 18 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 19 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 20 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 21 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure;

FIG. 22 is a cross-sectional view taken along line D-D of FIG. 21;

fig. 23 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure;

fig. 24 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure; and

fig. 25 is a sectional view taken along line D-D of fig. 24.

Detailed Description

In the drawings of a semiconductor device according to some embodiments of the present disclosure, a fin transistor (FinFET) including a fin-pattern-shaped channel region or a planar transistor is exemplarily shown, but the present disclosure is not limited thereto. Of course, semiconductor devices according to some embodiments of the present disclosure may include tunneling FETs, transistors including nanowires, transistors including nanoplates, or three-dimensional (3D) transistors. In addition, semiconductor devices according to some embodiments of the present disclosure may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), and the like.

Fig. 1 is a diagram for illustrating a semiconductor device according to some embodiments of the present disclosure.

Referring to fig. 1, a semiconductor device according to some embodiments of the present disclosure may include a first gate structure 115, a first source/drain region 150, a first set of conductive connections 155, and a second set of conductive connections 156.

The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate, or may include, but is not limited to, other materials such as silicon germanium, Silicon Germanium On Insulator (SGOI), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

An element isolation film 101 may be formed in the substrate 100. The element isolation film 101 may define an active region. The element isolation film 101 may include, for example, at least one of silicon oxide, silicon oxynitride, and silicon nitride.

The first gate structure 115 may be formed on the substrate 100. The first gate structure 115 may include a first gate spacer 140, a first gate electrode 120, a first interface layer 135, and a first gate insulating layer 130.

The first gate spacer 140 may be formed on the substrate 100. The first gate spacer 140 may define a space in which the first interface layer 135, the first gate insulating layer 130, and the first gate electrode 120 are formed.

The first gate spacer 140 may include, for exampleSuch as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO)₂) And silicon oxycarbonitride (SiOCN).

The first interface layer 135 may be formed on the substrate 100. The first interface layer 135 may be formed between two of the first gate spacers 140. Although the first interface layer 135 is illustrated as being formed only on the upper surface of the substrate 100, the present disclosure is not limited thereto. Depending on the manufacturing method, the first interface layer 135 may extend along the sidewalls of the first gate spacer 140.

When the substrate 100 includes silicon, the first interface layer 135 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

The first gate insulating layer 130 may be formed on the first interface layer 135. The first gate insulating layer 130 may extend along the upper surface of the substrate 100 and sidewalls of the first gate spacer 140.

The first gate insulating layer 130 may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

Unlike the illustrated case, the first gate insulating layer 130 may be formed only on the upper surface of the substrate 100 without extending along the sidewalls of the first gate spacers 140.

Further, unlike the illustrated case, the first gate insulating layer 130 may not be formed on the first interface layer 135. In addition, the first interface layer 135 may not be formed between the first gate insulating layer 130 and the substrate 100. For example, the first interface layer 135 may be omitted so that the first gate insulating layer 130 may be in contact with the upper surface of the substrate 100.

The first gate electrode 120 may be formed on the first gate insulating layer 130. The first gate electrode 120 may fill a space defined by the first gate spacer 140. For example, the upper surface of the first gate electrode 120 may be placed on the same plane as the upper surface of the first gate spacer 140.

The first gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaSiN), titanium aluminum nitride (tiain), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), and, At least one of zinc (Zn), vanadium (V), and combinations thereof.

A first source/drain region 150 may be formed on at least one side of the first gate structure 115. As an example, the first source/drain region 150 may be formed by implanting impurities into the substrate 100. As another example, the first source/drain region 150 may include an epitaxial pattern. The epitaxial pattern may fill a recess formed in the substrate 100.

Although not shown, the first source/drain region 150 may further include a metal silicide layer.

The first interlayer insulating layer 71 may be formed on the substrate 100. The first interlayer insulating layer 71 may cover the first source/drain region 150 and the first gate structure 115. Although the first interlayer insulating layer 71 is illustrated as a single layer, the present disclosure is not limited thereto. For example, the first interlayer insulating layer 71 may be a plurality of insulating layers formed in different processes with reference to the upper surface 140u of the first gate spacer 140.

The second interlayer insulating layer 72 and the third interlayer insulating layer 73 may be sequentially formed on the first interlayer insulating layer 71.

Each of the first interlayer insulating layer 71, the second interlayer insulating layer 72, and the third interlayer insulating layer 73 may include, but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (flowable oxide), TOSZ (eastern silazane), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma enhanced tetraethylorthosilicate), FSG (fluoride silicate glass), CDO (carbon-doped silicon oxide), xerogel, aerogel, amorphous carbon fluoride, OSG (organosilicate glass), parylene, BCB (bis-benzocyclobutene), SiLK, polyimide, porous polymer material, or a combination thereof.

The first set of conductive connections 155 may be formed on the substrate 100. The first conductive connection group 155 may be connected to the first gate electrode 120.

The first conductive connection group 155 may include a first gate contact plug 165, a first lower via plug 176, a first lower interlayer wiring 177, a first upper via plug 186, and a first upper interlayer wiring 187. The first lower interlayer wiring 177 is formed at a different metal level (metal level) from that of the first upper interlayer wiring 187. For example, the metal level of the first lower interlayer wiring 177 is lower than that of the first upper interlayer wiring 187.

The first gate contact plug 165 may be formed on the first gate structure 115. The first gate contact plug 165 may be connected to the first gate electrode 120. The first gate contact plug 165 may contact the first gate electrode 120.

The first gate contact plug 165 may be formed in the first gate contact hole 165t within the first interlayer insulating layer 71. The first gate contact hole 165t may expose the first gate electrode 120.

The first gate contact plug 165 may include a first gate contact blocking layer 165a, a first ferroelectric material layer 50, and a first gate contact filling layer 165b on the first gate electrode 120. The upper surface of the first gate contact plug 165 is higher than the upper surface of the first gate structure 115.

The first gate contact blocking layer 165a may extend along sidewalls and a bottom surface of the first gate contact hole 165 t.

The first ferroelectric material layer 50 may be formed on the first gate contact blocking layer 165 a. The first ferroelectric material layer 50 may extend along sidewalls and a bottom surface of the first gate contact hole 165 t. At least a portion of the first ferroelectric material layer 50 may be disposed over the upper surface 140u of the first gate spacer 140. In an example embodiment, the uppermost surface of the first ferroelectric material layer 50 is higher than the upper surface 140u of the first gate spacer 140.

A first gate contact fill layer 165b may be formed on first ferroelectric material layer 50. The first gate contact filling layer 165b may fill the first gate contact hole 165 t.

The first lower via plug 176 may be formed on the first gate contact plug 165. The first lower via plug 176 may be connected to the first gate contact plug 165. The first lower via plug 176 may contact the first gate contact plug 165.

The first lower via plug 176 may be formed in the first lower via 176t within the second interlayer insulating layer 72. The first lower via hole 176t may expose the first gate contact plug 165.

The first lower via plug 176 may include a first lower via blocking layer 176a and a first lower via filling layer 176b on the first gate contact plug 165.

The first lower via blocking layer 176a may be formed along sidewalls and a bottom surface of the first lower via 176 t. A first lower via-filling layer 176b may be formed on the first lower via-blocking layer 176 a. The first lower via filling layer 176b may fill the first lower via 176 t.

The first lower interlayer wiring 177 may be formed on the first lower via plug 176. The first lower interlayer wiring 177 may be connected to the first lower via plug 176. The first lower interlayer wiring 177 may be in contact with the first lower via plug 176.

The first lower interlayer wiring 177 may be formed in the first lower wiring trench 177t within the second interlayer insulating layer 72. The first lower via hole 176t may be formed on a bottom surface of the first lower routing trench 177 t. For example, the first lower via 176t may be connected to the bottom surface of the first lower routing trench 177 t.

The first lower interlayer wiring 177 may include a first lower wiring blocking layer 177a and a first lower wiring filling layer 177b on the first lower via plug 176.

The first lower wiring blocking layer 177a may be formed along sidewalls and a bottom surface of the first lower wiring trench 177 t. The first lower wiring filling layer 177b may be formed on the first lower wiring blocking layer 177 a. The first lower wiring filling layer 177b may fill the first lower wiring trench 177 t.

The first lower wiring blocking layer 177a and the first lower via blocking layer 176a may be formed through the same manufacturing process, and the first lower wiring filling layer 177b and the first lower via filling layer 176b may be formed through the same manufacturing process. For example, the first lower interlayer wiring 177 and the first lower via plug 176 may be integrally formed using a dual-damascene process (dual-damascene). As a result, the first lower via plugs 176 and the first lower interlayer wiring 177 may realize an integral structure.

The first upper via plug 186 may be formed on the first lower interlayer wiring 177. The first upper via plugs 186 may be connected to the first lower interlayer wiring 177.

The first upper via plug 186 may be formed in the first upper via 186t within the third interlayer insulating layer 73. The first upper via plug 186 may include a first upper via blocking layer 186a and a first upper via filling layer 186b on the first lower interlayer wiring 177.

First upper via blocking layer 186a may be formed along sidewalls and a bottom surface of first upper via 186 t. A first upper via filling layer 186b may be formed on the first upper via blocking layer 186 a. The first upper via filling layer 186b may fill the first upper via 186 t.

A first upper interlayer wiring 187 may be formed on the first upper via plug 186. The first upper interlayer wiring 187 may be connected to the first upper via plug 186. The first upper interlayer wiring 187 may be in contact with the first upper via plug 186.

The first upper interlayer wiring 187 may be formed in the first upper wiring groove 187t within the third interlayer insulating layer 73. The first upper via 186t may be formed on a bottom surface of the first upper routing groove 187 t. For example, the first upper via 186t may be connected to a bottom surface of the first upper routing groove 187 t.

The first upper interlayer wire 187 may include a first upper wire blocking layer 187a and a first upper wire filling layer 187b on the first upper via plug 186.

The first upper wiring blocking layer 187a may be formed along sidewalls and a bottom surface of the first upper wiring trench 187 t. A first upper wiring filling layer 187b may be formed on the first upper wiring blocking layer 187 a. The first upper wiring filling layer 187b may fill the first upper wiring trench 187 t.

The first upper-wiring-block layer 187a and the first upper-via-hole-block layer 186a may be formed by the same manufacturing process, and the first upper-wiring-filling layer 187b and the first upper-via-hole-filling layer 186b may be formed by the same manufacturing process. For example, the first upper interlayer wiring 187 and the first upper via plug 186 may be integrally formed using a dual damascene process. As a result, the first upper via plug 186 and the first upper interlayer wiring 187 may realize an integral structure.

Other via plugs and interlayer wirings may be further formed between the first upper via plug 186 and the first lower interlayer wiring 177, unlike the illustrated case.

The second set of conductive connections 156 may be formed on the substrate 100. The second set of conductive connections 156 may be connected to the first source/drain region 150.

The second conductive connection group 156 may include a first source/drain contact plug 160, a second lower via plug 171, a second lower interlayer wiring 172, a second upper via plug 181, and a second upper interlayer wiring 182. The second lower interlayer wiring 172 is formed at a different metal level from the second upper interlayer wiring 182. The first and second lower interlayer wirings 177 and 172 may be formed at the same metal level, and the first and second upper interlayer wirings 187 and 182 may be formed at the same metal level.

First source/drain contact plugs 160 may be formed on the first source/drain regions 150. The first source/drain contact plug 160 may be connected to the first source/drain region 150. The first source/drain contact plug 160 may contact the first source/drain region 150.

The first source/drain contact plugs 160 may be formed in the first source/drain contact holes 160t within the first interlayer insulating layer 71. The first source/drain contact hole 160t may expose the first source/drain region 150.

The first source/drain contact plug 160 may include a first source/drain contact blocking layer 160a and a first source/drain contact filling layer 160b on the first source/drain region 150.

The first source/drain contact blocking layer 160a may extend along sidewalls and a bottom surface of the first source/drain contact hole 160 t. A first source/drain contact fill layer 160b may be formed on the first source/drain contact blocking layer 160 a. The first source/drain contact filling layer 160b may fill the first source/drain contact hole 160 t.

The upper surface of the first source/drain contact plug 160 is higher than the upper surface of the first gate structure 115. The upper surface of the first source/drain contact plug 160 may be placed on the same plane as the upper surface of the first gate contact plug 165.

In the semiconductor device according to some embodiments of the present disclosure, a height h11 from the upper surface of the first gate structure 115 to the uppermost surface of the first ferroelectric material layer 50 may be equal to or greater than a height h12 from the upper surface of the first gate structure 115 to the upper surface of the first source/drain contact plug 160. For example, the uppermost surface of the first ferroelectric material layer 50 may be located at the same or higher position as the upper surface of the first source/drain contact plugs 160 in a vertical direction perpendicular to the upper surface of the substrate 100.

For example, a height h11 from the upper surface of the first gate structure 115 to the uppermost surface of the first ferroelectric material layer 50 may be substantially the same as a height h12 from the upper surface of the first gate structure 115 to the upper surface of the first source/drain contact plugs 160.

A second lower via plug 171 may be formed on the first source/drain contact plug 160. The second lower via plug 171 may be connected to the first source/drain contact plug 160. The second lower via plug 171 may contact the first source/drain contact plug 160.

The second lower via plug 171 may be formed in the second lower via 171t within the second interlayer insulating layer 72. The second lower via hole 171t may expose the first source/drain contact plug 160.

The second lower via plug 171 may include a second lower via blocking layer 171a and a second lower via filling layer 171b on the first source/drain contact plug 160.

A second lower via blocking layer 171a may be formed along sidewalls and a bottom surface of the second lower via 171 t. A second lower via filling layer 171b may be formed on the second lower via blocking layer 171 a. The second lower via filling layer 171b may fill the second lower via 171 t.

A second lower interlayer wiring 172 may be formed on the second lower via plug 171. The second lower interlayer wiring 172 may be connected to the second lower via plug 171. The second lower interlayer wiring 172 may be in contact with the second lower via plug 171.

The second lower interlayer wiring 172 may be formed in the second lower wiring trench 172t within the second interlayer insulating layer 72. The second lower via hole 171t may be formed on the bottom surface of the second lower wiring trench 172 t. For example, the second lower via hole 171t may be connected to the bottom surface of the second lower wiring trench 172 t.

The second lower interlayer wire 172 may include a second lower wire blocking layer 172a and a second lower wire filling layer 172b on the second lower via plug 171.

The second lower wiring blocking layer 172a may be formed along sidewalls and a bottom surface of the second lower wiring trench 172 t. The second lower wiring filling layer 172b may be formed on the second lower wiring blocking layer 172 a. The second lower wiring filling layer 172b may fill the second lower wiring trench 172 t.

The second lower wiring blocking layer 172a and the second lower via blocking layer 171a may be formed through the same manufacturing process, and the second lower wiring filling layer 172b and the second lower via filling layer 171b may be formed through the same manufacturing process. For example, the second lower via plug 171 and the second lower interlayer wiring 172 may be integrally formed using a dual damascene process. Accordingly, the second lower via plug 171 and the second lower interlayer wiring 172 may realize an integral structure.

A second upper via plug 181 may be formed on the second lower interlayer wiring 172. The second upper via plug 181 may be connected to the second lower interlayer wiring 172.

The second upper via plug 181 may be formed in the second upper via 181t within the third interlayer insulating layer 73. The second upper via plug 181 may include a second upper via blocking layer 181a and a second upper via filling layer 181b on the second lower interlayer wiring 172.

The second upper via blocking layer 181a may be formed along sidewalls and a bottom surface of the second upper via 181 t. A second upper via-filling layer 181b may be formed on the second upper via-blocking layer 181 a. The second upper via filling layer 181b may fill the second upper via 181 t.

A second upper interlayer wiring 182 may be formed on the second upper via plug 181. The second upper interlayer wiring 182 may be connected to the second upper via plug 181. The second upper interlayer wiring 182 may contact the second upper via plug 181.

The second upper interlayer wiring 182 may be formed in the second upper wiring trench 182t within the third interlayer insulating layer 73. The second upper via hole 181t may be formed on the bottom surface of the second upper wiring trench 182 t. For example, the second upper via 181t may be connected to the bottom surface of the second upper wiring trench 182 t.

The second upper interlayer wiring 182 may include a second upper wiring blocking layer 182a and a second upper wiring filling layer 182b on the second upper via plug 181.

The second upper wiring blocking layer 182a may be formed along sidewalls and a bottom surface of the second upper wiring trench 182 t. A second upper wiring filling layer 182b may be formed on the second upper wiring blocking layer 182 a. The second upper wiring filling layer 182b may fill the second upper wiring trench 182 t.

The second upper wiring blocking layer 182a and the second upper via blocking layer 181a may be formed through the same manufacturing process, and the second upper wiring filling layer 182b and the second upper via filling layer 181b may be formed through the same manufacturing process. For example, the second upper via plug 181 and the second upper interlayer wiring 182 may be integrally formed using a dual damascene process. Accordingly, the second upper via plug 181 and the second upper interlayer wiring 182 may realize an integral structure.

The first ferroelectric material layer 50 may have ferroelectric characteristics. The first ferroelectric material layer 50 may have a sufficient thickness to have ferroelectric characteristics. For example, the thickness of the first ferroelectric material layer 50 may be greater than the critical thickness of the ferroelectric material layer 50 having ferroelectric characteristics. Since the critical thickness exhibiting ferroelectric characteristics may vary depending on the kind of ferroelectric material of the first ferroelectric material layer 50, the thickness of the first ferroelectric material layer 50 may vary depending on the kind of ferroelectric material.

First ferroelectric material layer 50 may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Herein, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr), and may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The first ferroelectric material layer 50 may further include a doping element doped in the above-described material. The doping element may be an element selected from: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn).

Each of the barrier layers 160a, 165a, 171a, 172a, 176a, 177a, 181a, 182a, 186a, and 187a may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), Vanadium Nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh).

Each of the filling layers 160b, 165b, 171b, 172b, 176b, 177b, 181b, 182b, 186b, and 187b may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), and cobalt (Co).

The first set of conductive connections 155 connected to the first gate electrode 120 may include the first ferroelectric material layer 50. However, the second set of conductive connections 156 connected to the first source/drain region 150 does not include a layer of ferroelectric material.

Conductive layers are formed on upper and lower portions of the first ferroelectric material layer 50 included in the first conductive connection group 155. That is, first set of conductive connections 155 may include a ferroelectric capacitor having first ferroelectric material layer 50. In fig. 1, a ferroelectric capacitor may be defined by disposing a first ferroelectric material layer 50 between a first gate contact blocking layer 165a and a first gate contact filling layer 165 b. For example, the layered structure of the first gate contact blocking layer 165a, the first ferroelectric material layer 50, and the first gate contact filling layer 165b may be used as a ferroelectric capacitor.

The ferroelectric capacitor may have a negative capacitance. The fact that the ferroelectric capacitor has a negative capacitance means that the dipole moment of the molecules can change when the ferroelectric material receives more energy than a certain external energy. Unlike a general dielectric capacitor, in a ferroelectric capacitor, a portion having negative energy may be generated at a phase transition of a material.

Therefore, when the ferroelectric material layer having ferroelectric characteristics is used, a capacitor having a negative capacitance in a specific portion can be realized.

On the other hand, when the ferroelectric capacitor is connected in series with the gate electrode, the total capacitance can be increased. Accordingly, the voltage applied to the gate electrode can be amplified.

As a result, voltage amplification can be realized in the gate electrode of the transistor, and the switching speed of the transistor can be improved. That is, transistors having a sub-threshold swing (SS) of less than 60mV/decade at room temperature can be realized.

Fig. 2 is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 1 will be mainly described.

Referring to fig. 2, in the semiconductor device according to some embodiments of the present disclosure, the first gate contact plug 165 may include a first ferroelectric material layer 50, a first gate contact blocking layer 165a, and a first gate contact filling layer 165b sequentially stacked on the first gate electrode 120.

A first gate contact blocking layer 165a may be disposed between the first ferroelectric material layer 50 and the first gate contact filling layer 165 b. For example, the first ferroelectric material layer 50 may be in contact with the first gate electrode 120.

A ferroelectric capacitor may be defined by disposing first ferroelectric material layer 50 between first gate contact blocking layer 165a and first gate electrode 120.

Fig. 3 is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. Fig. 4 is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 1 will be mainly described.

Referring to fig. 3 and 4, in a semiconductor device according to some embodiments of the present disclosure, the first lower via plug 176 may include the first ferroelectric material layer 50.

The first lower via plug 176 may include a first lower via blocking layer 176a, a first ferroelectric material layer 50, and a first lower via filling layer 176b formed on the first gate contact plug 165.

The first ferroelectric material layer 50 may be disposed between the first lower via blocking layer 176a and the first lower via filling layer 176 b. A ferroelectric capacitor may be defined by disposing the first ferroelectric material layer 50 between the first lower via blocking layer 176a and the first lower via filling layer 176 b.

In example embodiments, a first lower via blocking layer 176a may be disposed between the first ferroelectric material layer 50 and the first lower via filling layer 176 b.

The first lower interlayer wiring 177 may not include the first ferroelectric material layer 50. The first ferroelectric material layer 50 may not extend along the lower surface of the first lower wiring filling layer 177 b. That is, the first ferroelectric material layer 50 may not extend along the bottom surface of the first lower wiring trench 177 t.

A height h11 from the upper surface of the first gate structure 115 to the uppermost surface of the first ferroelectric material layer 50 is greater than a height h12 from the upper surface of the first gate structure 115 to the upper surface of the first source/drain contact plugs 160.

In fig. 3, the first lower wiring fill layer 177b may be in contact with the first ferroelectric material layer 50. The first lower wiring filling layer 177b may be directly connected to the first lower via filling layer 176 b.

In fig. 4, the first lower wiring fill layer 177b may not be in contact with the first ferroelectric material layer 50. The first lower wiring blocking layer 177a may be disposed between the first lower wiring filling layer 177b and the first ferroelectric material layer 50. The lower wiring filling layer 177b and the first lower via filling layer 176b may be separated from each other by a first lower wiring blocking layer 177 a.

Fig. 5 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 1 will be mainly described.

Referring to fig. 5, in a semiconductor device according to some embodiments of the present disclosure, the first lower via plug 176 and the first lower interlayer wiring 177 may include the first ferroelectric material layer 50.

The first ferroelectric material layer 50 may include: a first portion 50a extending along the sidewall and bottom surface of the first lower via 176 t; and a second portion 50b extending along sidewalls and a bottom surface of the first lower wiring trench 177 t.

The first lower via plug 176 may include a first lower via blocking layer 176a formed on the first gate contact plug 165, a first portion 50a of the first ferroelectric material layer, and a first lower via filling layer 176 b.

The first lower interlayer wiring 177 may include a first lower wiring blocking layer 177a formed on the first lower via plug 176, a second portion 50b of the first ferroelectric material layer, and a first lower wiring filling layer 177 b.

The first ferroelectric material layer 50 may be disposed between the first lower via blocking layer 176a and the first lower wiring blocking layer 177a and the first lower via filling layer 176b and the first lower wiring filling layer 177 b. The ferroelectric capacitor may be defined by disposing the first ferroelectric material layer 50 between the first lower via-blocking layer 176a and the first lower wiring-blocking layer 177a and the first lower via-filling layer 176b and the first lower wiring-filling layer 177 b.

Fig. 6 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 7 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 1 will be mainly described.

Referring to fig. 6, in a semiconductor device according to some embodiments of the present disclosure, first upper via plug 186 may include first ferroelectric material layer 50.

The first upper via plug 186 may include a first upper via blocking layer 186a, a first ferroelectric material layer 50, and a first upper via filling layer 186b formed on the first lower interlayer wiring 177.

First ferroelectric material layer 50 may be disposed between first upper via blocking layer 186a and first upper via filling layer 186 b. A ferroelectric capacitor may be defined by disposing first ferroelectric material layer 50 between first upper via blocking layer 186a and first upper via fill layer 186 b.

Unlike the case shown, of course, first upper via blocking layer 186a may be disposed between first ferroelectric material layer 50 and first upper via filling layer 186 b. The first ferroelectric material layer 50 may be in contact with the first lower wiring filling layer 177 b.

Although it is illustrated that the first upper interlayer wiring 187 does not include the first ferroelectric material layer 50, the present disclosure is not limited thereto. For example, the first upper interlayer wiring 187 may include the first ferroelectric material layer 50.

Referring to fig. 7, the semiconductor device according to some embodiments of the present disclosure may further include a first insert wiring 195 and a second insert wiring 190. The first interposing wiring 195 may include the first ferroelectric material layer 50.

The first conductive connection group 155 may include a first insert wiring 195. The first insert wiring 195 may be disposed between the first gate contact plug 165 and the first lower via plug 176.

The first insert wiring 195 may be formed on the first gate contact plug 165. The first insert wiring 195 may be connected to the first gate contact plug 165. The first insert wiring 195 may contact the first gate contact plug 165.

The first insert wiring 195 may be formed in the first insert wiring groove 195t inserted in the interlayer insulating layer 74. The first insert wiring trench 195t may expose the first gate contact plug 165.

The first interwiring 195 may include a first interwiring blocking layer 195a, a first ferroelectric material layer 50, and a first interwiring filling layer 195b on the first gate contact plug 165. The first insert wiring blocking layer 195a and the first ferroelectric material layer 50 may extend along sidewalls and a bottom surface of the first insert wiring trench 195 t. A first intervening wiring fill layer 195b may be formed on the first ferroelectric material layer 50.

As shown, a ferroelectric capacitor may be defined by disposing a first ferroelectric material layer 50 between a first intervening wire barrier layer 195a and a first intervening wire fill layer 195 b.

On the other hand, in the case where the first intervening wiring blocking layer 195a is disposed between the first ferroelectric material layer 50 and the first intervening wiring filling layer 195b, unlike the above case, the first ferroelectric material layer 50 is disposed between the first intervening wiring blocking layer 195a and the first gate contact plug 165, thereby defining a ferroelectric capacitor.

The second conductive connection group 156 may include a second insert wiring 190. The second insert wiring 190 may be disposed between the first source/drain contact plug 160 and the second lower via plug 171.

The second insert wiring 190 may be formed on the first source/drain contact plug 160. The second insert wiring 190 may be connected to the first source/drain contact plug 160. The second insert wiring 190 may contact the first source/drain contact plug 160.

The second insert wiring 190 may be formed in the second insert wiring groove 190t inserted into the interlayer insulating layer 74. The second insert wiring trench 190t may expose the first source/drain contact plug 160.

The second insert wiring 190 may include a second insert wiring blocking layer 190a and a second insert wiring filling layer 190b on the first source/drain contact plug 160.

Referring to fig. 8, in the semiconductor device according to some embodiments of the present disclosure, the first gate structure 115 may further include a first capping pattern 145 on the first gate electrode 120.

An upper surface of the first capping pattern 145 may be placed on the same plane as the upper surface 140u of the first gate spacer 140.

The first gate contact hole 165t may pass through the first capping pattern 145 to expose the first gate electrode 120.

Fig. 9 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 10 to 12 are sectional views taken along line a-a, line B-B and line C-C in fig. 9. Fig. 13a to 13e are diagrams for explaining example shapes that the upper surface of the second gate contact plug may have.

For convenience of explanation, without describing interlayer wiring, the following example will be described: only the second gate contact plug 265 and the via plug 276 of the conductive connection group connected to the second gate structure 215_1 are used. Further, only the second source/drain contact plugs 260 in the set of conductive connections connected to the second source/drain regions 250 will be used to provide illustration.

In addition, although fig. 9 illustrates that one second gate contact plug 265 is formed, this is merely for convenience of explanation, and the embodiment is not limited thereto.

Referring to fig. 9 to 12, a semiconductor device according to some embodiments of the present disclosure may include: the fin patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6, the second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5, the second gate contact plugs 265, and the second source/drain contact plugs 260.

Substrate 100 may include first and second active regions ACT1 and ACT2 adjacent to each other, and a field region FX. A field region FX may be used to electrically isolate the first active region ACT1 and the second active region ACT2 from each other. Although the field region FX is illustrated as being defined only between the first and second active regions ACT1 and ACT2, this is for convenience of explanation, and the embodiment is not limited thereto. For example, a field region FX may surround each of the first active region ACT1 and the second active region ACT 2.

The fin patterns 210_1, 201_2, and 210_3 may be formed on the substrate 100 of the first active region ACT 1. In addition, the fin patterns 210_4, 201_5, and 210_6 may be formed on the substrate 100 of the second active region ACT 2.

The fin patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 may extend long in the first direction X, respectively.

It is illustrated that the same number of fin patterns are formed in the first and second active regions ACT1 and ACT2, but the present disclosure is not limited thereto.

The fin patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 may be a portion of the substrate 100. For example, the fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 may be epitaxially grown from the substrate 100, or may be formed by patterning the substrate 100. The fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 may include silicon or germanium as an elemental semiconductor material, respectively.

In addition, the fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound (including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn)), a ternary compound, or a compound obtained by doping these elements with a group IV element. For example, the III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed, for example, by a combination of at least one of aluminum (Al), gallium (Ga), and indium (In) As a group III element and one of phosphorus (P), arsenic (As), and antimony (Sb) As a group V element.

A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may define the fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_ 6. The field insulating layer 105 may be disposed on a portion of sidewalls of the fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_ 6.

The field insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5 may be formed on the substrate 100. The second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5 may extend long in the second direction Y.

The second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5 may be formed over the first active area ACT1, the field region FX, and the second active area ACT 2. The second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5 may be formed on the fin patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_ 6. The second gate structures 215_1, 215_2, 215_3, 215_4, and 215_5 may intersect the fin patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_ 6.

The second gate structure 215_1 may include a second interface layer 235_1, a second gate insulating layer 230_1, and a second gate electrode 220_ 1. The second gate structure 215_1 may include a second gate spacer 240_1 formed on a sidewall of the second gate electrode 220_ 1.

The second interface layer 235_1 may be formed along the profile of the fin patterns 210_1 and 210_4 protruding above the upper surface of the field insulating layer 105. The second gate insulating layer 230_1 may be formed along the profile of the fin patterns 210_1 and 210_4 protruding above the upper surface of the field insulating layer 105. The second gate electrode 220_1 may be formed on the second gate insulating layer 230_ 1.

The second source/drain regions 250 may be formed on the fin-type patterns 210_1, 210_2, and 210_3 disposed in the first active region ACT 1. Of course, the source/drain regions may be formed on the fin-type patterns 210_4, 210_5, and 210_6 disposed in the second active region ACT 2. Although the second source/drain regions 250 are illustrated as having shapes coupled to each other, embodiments are not limited thereto.

The first interlayer insulating layer 71 may include a first lower interlayer insulating layer 71a and a first upper interlayer insulating layer 71 b. The first lower interlayer insulating layer 71a and the first upper interlayer insulating layer 71b may be divided with reference to the upper surface 240u of the second gate spacer 240_ 1.

A second gate contact plug 265 may be formed on the second gate electrode 220_ 1. The second gate contact plug 265 may be connected to the second gate electrode 220_ 1. The second gate contact plug 265 may contact the second gate electrode 220_ 1.

A second gate contact plug 265 may be formed in the second gate contact hole 265t within the first upper interlayer insulating layer 71 b. The second gate contact hole 265t may expose a portion of the second gate electrode 220_ 1.

The second gate contact plug 265 may include a second gate contact blocking layer 265a, a second ferroelectric material layer 55, and a second gate contact filling layer 265b on the second gate electrode 220_ 1. The upper surface of the second gate contact plug 265 is higher than the upper surface of the second gate structure 215_ 1.

The second gate contact blocking layer 265a may extend along sidewalls and a bottom surface of the second gate contact hole 265 t.

The second ferroelectric material layer 55 may be formed on the second gate contact blocking layer 265 a. The second ferroelectric material layer 55 may extend along sidewalls and a bottom surface of the second gate contact hole 265 t. At least a portion of the second ferroelectric material layer 55 may be disposed over the upper surface 240u of the second gate spacer 240_ 1. In other aspects, the uppermost surface of the second ferroelectric material layer 55 is higher than the upper surface 240u of the second gate spacer 240_ 1.

A second gate contact fill layer 265b may be formed on the second ferroelectric material layer 55. The second gate contact filling layer 265b may fill the second gate contact hole 265 t.

Unlike the illustrated case, the second gate contact blocking layer 265a may be disposed between the second ferroelectric material layer 55 and the second gate contact filling layer 265 b.

Since the second gate contact hole 265t exposes a portion of the second gate electrode 220_1, the width W12 of the second gate contact plug 265 in the second direction Y is smaller than the width of the second gate electrode 220_1 in the second direction Y.

The second gate contact plug 265 may extend long in the first direction X. For example, the width W11 of the second gate contact plug 265 in the first direction X may be greater than the width W12 of the second gate contact plug 265 in the second direction Y.

In addition, the width W11 of the second gate contact plug 265 in the first direction X may be greater than not only the width of the second gate electrode 220_1 in the first direction X but also the width of the second gate structure 215_1 in the first direction X.

A second gate contact plug 265 may be disposed on the substrate 100 of the field region FX between the first active region ACT1 and the second active region ACT 2. The second gate contact plug 265 may contact the second gate electrode 220_1 disposed on the substrate 100 of the field region FX.

Unlike the illustrated case, the second gate contact plug 265 may be disposed on the substrate 100, instead of the first and second active regions ACT1 and ACT2, while the end of the second gate structure 215_1 is located on the second gate contact plug 265.

Via plugs 276 may be formed on the second gate contact plugs 265. The via plug 276 may be connected to the second gate contact plug 265. The via plug 276 may contact the second gate contact plug 265.

The via plug 276 may be formed in the via 276t within the second interlayer insulating layer 72. The via 276t may expose the second gate contact plug 265.

Via plug 276 may include a via blocking layer 276a and a via filling layer 276b on second gate contact plug 265.

Via blocking layer 276a may be formed along sidewalls and bottom surface of via 276 t. Via fill layer 276b may be formed on via blocking layer 276 a. Via fill layer 276b may fill vias 276 t.

The second source/drain contact plugs 260 may be formed on the fin-type patterns 210_1, 210_2, 210_3, 210_4, 210_5, and 210_6 between the adjacent second gate structures 215_1, 215_2, 215_3, 215_4, and 215_ 5.

Second source/drain contact plugs 260 may be formed on the second source/drain regions 250. The second source/drain contact plug 260 may be connected to the second source/drain region 250. The second source/drain contact plug 260 may contact the second source/drain region 250.

The second source/drain contact plugs 260 may be formed in the second source/drain contact holes 260t within the first interlayer insulating layer 71. The second source/drain contact hole 260t may expose the second source/drain region 250.

The second source/drain contact plug 260 may include a second source/drain contact blocking layer 260a and a second source/drain contact filling layer 260b on the second source/drain region 250.

The second source/drain contact blocking layer 260a may extend along sidewalls and a bottom surface of the second source/drain contact hole 260 t. A second source/drain contact filling layer 260b may be formed on the second source/drain contact blocking layer 260 a. The second source/drain contact filling layer 260b may fill the second source/drain contact holes 260 t.

The upper surface of the second source/drain contact plug 260 may be higher than the upper surface of the second gate structure 215_ 1. The upper surface of the second source/drain contact plug 260 may be placed on the same plane as the upper surface of the second gate contact plug 265.

The shape of the upper surface 265u of the second gate contact plug 265 will be described using fig. 13a to 13 e.

Fig. 13a to 13c illustrate a case where the second gate contact plug (265 of fig. 9) extends in a specific direction. Fig. 13d and 13e illustrate a case where the second gate contact plug 265 does not extend in a specific direction.

In fig. 13a, the boundary 265up of the upper surface of the second gate contact plug may have a rectangular shape.

In fig. 13b, the boundary 265up of the upper surface of the second gate contact plug may have a rectangular shape with rounded corners.

In fig. 13c, the boundary 265up of the upper surface of the second gate contact plug may have an elliptical shape.

In fig. 13d, the boundary 265up of the upper surface of the second gate contact plug may have a square shape.

In fig. 13e, the boundary 265up of the upper surface of the second gate contact plug may have a circular shape.

Unlike the shape shown in fig. 13d and 13e, the boundary 265up of the upper surface of the second gate contact plug may also be a square shape having rounded corners.

Fig. 14 and 15 are diagrams for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 9 to 12 will be mainly described.

Referring to fig. 14 and 15, in the semiconductor device according to some embodiments of the present disclosure, the second gate structure 215_1 may further include a second overlay pattern 245 on the second gate electrode 220_ 1.

The second gate contact hole 265t may penetrate a portion of the second overlay pattern 245 to expose a portion of the second gate electrode 220_ 1.

Fig. 16 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 17 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 9 to 12 will be mainly described.

Referring to fig. 16, in a semiconductor device according to some embodiments of the present disclosure, a first active region ACT1 and a second active region ACT2 may be defined by a deep trench DT.

In another manner, the portion where the deep trench DT is formed may be the field region FX.

The deep trench DT is deeper than the trenches defining the fin patterns 210_1 and 210_ 4.

Referring to fig. 17, in the semiconductor device according to some embodiments of the present disclosure, a protrusion pattern 200PF protruding from the substrate 100 may be formed in the field region FX.

The field insulating layer 105 may cover an upper surface of the protrusion pattern 200 PF. That is, the upper surface of the protrusion pattern 200PF does not protrude above the upper surface of the field insulating layer 105.

Fig. 18 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 19 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 20 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 9 to 12 will be mainly described, and the through-hole plug (276 of fig. 9) is not shown in fig. 18 to 20.

Referring to fig. 18, in the semiconductor device according to some embodiments of the present disclosure, the second gate contact plug 265 may extend long in the second direction Y.

A width W11 of the second gate contact plug 265 in the first direction X may be less than a width W12 of the second gate contact plug 265 in the second direction Y.

Referring to fig. 19, in the semiconductor device according to some embodiments of the present disclosure, the second gate contact plug 265 may be formed on the substrate 100 of the first active region ACT 1.

The second gate contact plugs 265 may be disposed between the second source/drain contact plugs 260 adjacent to each other.

Referring to fig. 20, in the semiconductor device according to some embodiments of the present disclosure, a second gate contact plug 265 may be formed over the first active region ACT1 and the field region FX.

A portion of the second gate contact plug 265 may be formed on the substrate 100 of the field region FX. The remaining portion of the second gate contact plug 265 may be formed on the substrate 100 of the first active region ACT 1.

Fig. 21 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 22 is a sectional view taken along line D-D of fig. 21. For convenience of explanation, differences from those described using fig. 9 to 12 will be mainly described.

Referring to fig. 21 and 22, the semiconductor device according to some embodiments of the present disclosure may further include a third insertion wiring 295.

The third insert wiring 295 may be disposed between the second gate contact plug 265 and the via plug 276. The third insert wiring 295 may be connected to the second gate contact plug 265 and the via plug 276. The third insert wiring 295 may contact the second gate contact plug 265.

The third insert wiring 295 may be formed in the third insert wiring groove 295t inserted in the interlayer insulating layer 74. The third insert wiring trench 295t may expose the second gate contact plug 265.

The third insert wiring 295 may include a third insert wiring blocking layer 295a and a third insert wiring filling layer 295b on the second gate contact plug 265. The third insert wiring blocking layer 295a may extend along sidewalls and a bottom surface of the third insert wiring trench 295 t. A third interwiring filling layer 295b may be formed on the third interwiring blocking layer 295 a.

The third insert wiring 295 may be formed over at least two or more second gate structures 215_1 and 215_ 2. For example, the third insert wiring 295 may extend onto an upper surface of the second gate structure 215_1 connected to the second gate contact plug 265 and onto an upper surface of the adjacent second gate structure 215_ 2. In example embodiments, a portion of the third insert wiring 295 may extend onto an upper surface of the second gate structure 215_1 connected to the second gate contact plug 265. Another portion of the third insert wiring 295 may extend onto an upper surface of the adjacent second gate structure 215_ 2.

The via plug 276 may be disposed on the substrate 100 between the second gate structures 215_1 and 215_2 adjacent to each other, but is not limited thereto.

Unlike the illustrated case, the third insert wiring 295 may also be formed on the three or more second gate structures 215_1, 215_2, 215_3, 215_4, and 215_ 5.

Fig. 23 is a diagram for explaining a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, differences from those described using fig. 21 and 22 will be mainly described.

Referring to fig. 23, in a semiconductor device according to some embodiments of the present disclosure, the third insertion wiring 295 may include a second ferroelectric material layer 55.

A ferroelectric capacitor may be defined by disposing the second ferroelectric material layer 55 between the third intervening wiring blocking layer 295a and the third intervening wiring filling layer 295 b.

Unlike the illustrated case, a ferroelectric capacitor may be defined by disposing the second ferroelectric material layer 55 between the third interposing wiring blocking layer 295a and the second gate contact plug 265.

Fig. 24 is a layout view for explaining a semiconductor device according to some embodiments of the present disclosure. Fig. 25 is a sectional view taken along line D-D of fig. 24. For convenience of explanation, differences from those described using fig. 21 and 23 will be mainly described.

Referring to fig. 24 and 25, the semiconductor device according to some embodiments of the present disclosure may further include a third gate contact plug 266 disposed between the third insert wiring 295 and the second gate structure 215_ 2.

The third gate contact plug 266 may be formed on the second gate electrode 220_ 2. The third gate contact plug 266 may be connected to the second gate electrode 220_ 2. The third gate contact plug 266 may contact the second gate electrode 220_ 2.

A third gate contact plug 266 may be formed in the third gate contact hole 266t within the first upper interlayer insulating layer 71 b. The third gate contact hole 266t may expose a portion of the second gate electrode 220_ 2.

The third gate contact plug 266 may include a third gate contact blocking layer 266a and a third gate contact filling layer 266b on the second gate electrode 220_ 2. The upper surface of the third gate contact plug 266 is higher than the upper surface of the second gate structure 215_ 2.

Third gate contact blocking layer 266a may extend along sidewalls and a bottom surface of third gate contact hole 266 t. A third gate contact fill layer 266b may be formed on the third gate contact blocking layer 266 a. The third gate contact filling layer 266b may fill the third gate contact holes 266 t.

The third gate contact plug 266 may be connected to the third insert wiring 295.

Unlike the case described with reference to fig. 9 to 25, the second ferroelectric material layer 55 may be included at least one position in a via plug and an interlayer wiring formed in a back end of line (BEOL) process, as shown in fig. 3 to 6.

Upon concluding the detailed description, those skilled in the art will understand that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present disclosure. Accordingly, the disclosed preferred embodiments of the present disclosure are used in a generic and descriptive sense only and not for purposes of limitation.