阅读说明：本技术 半导体工艺所用的方法 (Method for semiconductor processing ) 是由 李溢芸 赵晟博 于雄飞 张哲豪 黄才育 张惠政 陈弘耀 于 2019-06-11 设计创作，主要内容包括：本发明所述的实施例涉及半导体工艺所用的方法,具体涉及形成装置的栅极结构,比如置换栅极工艺与其形成的装置。在一些例子中,沉积界面介电层与栅极介电层之后,可在控制下的含氮环境中进行快速退火工艺如激光退火或闪光灯退火工艺,以形成氮化部分于栅极介电层中。氮化部分可钝化栅极介电层表面的缺陷,并可作为阻障以避免蚀刻化学剂与来自后续栅极堆叠层的缺陷/掺质影响或扩散穿过栅极介电层。具体而言,毫秒等级的快速热退火工艺可限制氮原子在栅极介电层中,而不会扩散至下方的界面介电层及/或任何相邻的结构如鳍状物。(Embodiments described herein relate generally to methods used in semiconductor processing, and more particularly, to forming gate structures for devices, such as replacement gate processes and devices formed thereby. In some examples, after depositing the interfacial dielectric layer and the gate dielectric layer, a rapid annealing process, such as a laser annealing process or a flash lamp annealing process, may be performed in a controlled nitrogen-containing ambient to form a nitride portion in the gate dielectric layer. The nitrided portion passivates the gate dielectric layer surface defects and acts as a barrier to etch chemistries and defects/dopants from subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Specifically, the millisecond rapid thermal anneal process may confine nitrogen atoms in the gate dielectric layer from diffusing to the underlying interfacial dielectric layer and/or any adjacent structures, such as fins.)

1. A method for semiconductor processing, comprising:

conformably forming a gate dielectric layer on a fin extending from a substrate, the gate dielectric layer conformably along sidewalls of gate spacers on the fin;

nitriding the gate dielectric layer by a laser annealing process or a flash annealing process in an ammonia-containing environment; and

one or more metal-containing layers are formed on the gate dielectric layer.

Technical Field

Embodiments of the present invention relate to gate structures for forming devices, such as high-k dielectric/metal gate semiconductor transistors.

Background

As the semiconductor industry moves to the nanometer technology node for higher device density, higher performance, and lower cost, challenges from fabrication and design issues have resulted in the development of three-dimensional designs, such as finfet transistors. Finfet transistors typically include high aspect ratio semiconductor fins with channel regions and source/drain regions formed therein. The advantage of forming gates along the sidewalls and upper side of the fin structure (e.g., cladding the fin structure) is that increased channel surface area results in faster, more reliable, and better controlled semiconductor transistor devices.

To reduce leakage current and to produce equivalent field effect performance, high dielectric constant materials may be employed in gate structures for finfet devices. However, as dimensions shrink, these approaches present new challenges.

Disclosure of Invention

The method for the semiconductor process provided by the embodiment of the invention comprises the following steps: conformably forming a gate dielectric layer on the fin extending from the substrate, the gate dielectric layer conformably along sidewalls of the plurality of gate spacers on the fin; nitriding the gate dielectric layer by adopting a laser annealing process or a flash lamp annealing process in an ammonia-containing environment; and forming one or more metal-containing layers on the gate dielectric layer.

An embodiment of the present invention provides a method for a semiconductor process, including: forming an interfacial dielectric layer along a fin surface extending from a substrate; forming a gate dielectric layer on the interfacial dielectric layer; nitridizing the gate dielectric layer in an ammonia-containing environment using a laser beam or a radiation emitting lamp; and forming a metal gate on the gate dielectric layer.

An embodiment of the present invention provides a structure including: a substrate having fins extending from the substrate; a nitrogen-free interfacial dielectric layer along a surface of the fin; a gate structure on the fin; a work function adjusting layer on the gate dielectric layer; and a gate metal fill layer on the work function adjusting layer, wherein the gate structure comprises: a gate dielectric layer on the interfacial dielectric layer and having a nitride portion with a nitrogen concentration of about 0.5 x 10²¹Atom/cm³To about 8X 10²¹Atom/cm³In the meantime.

Drawings

Figure 1 is a three-dimensional view of an intermediate structure of a finfet in some embodiments.

Fig. 2-5 and 8-10 are cross-sectional views along section a-a of fig. 1 of respective intermediate structures in a method of forming a semiconductor device in some embodiments.

Fig. 6 is a cross-sectional view taken along section a-a of fig. 1 of an intermediate structure of a partially nitrided region in a gate dielectric layer formed by a laser annealing process, in some embodiments.

Fig. 7 is a cross-sectional view along section a-a of fig. 1 of an intermediate structure of a nitride layer formed in a gate dielectric layer by a flash lamp anneal process in some embodiments.

Description of reference numerals:

A-A section

40 semiconductor device

42 semiconductor substrate

44 isolation region

46 fin

52a, 52b source/drain regions

62. 80 interfacial dielectric layer

63. 85 peak temperature region

64 dummy gate layer

65. 83 low temperature zone

66 mask layer

67 local nitride region

68 gate spacer

69 nitrided layer

70 source/drain region

72 first interlayer dielectric layer

73 side wall

74 recess

81 upper surface

82 gate dielectric layer

86 barrier layer

87. 95 thermal gradient

89. 93 insert drawing

91 laser annealing process

97 flash lamp annealing process

100 first work function adjusting layer

102 second work function adjusting layer

104 barrier/adhesion layer

106 gate metal filling layer

110 second interlayer dielectric layer

112 liner

114 silicide region

116 conductive material

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The specific components and arrangements are disclosed to simplify the present disclosure and not to limit the present disclosure. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the various examples of the present disclosure may be repeated with reference numbers, but such repetition is merely intended to simplify and clarify the description and does not imply that there is a similar correspondence between elements having the same reference numbers in different embodiments and/or arrangements.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

Embodiments of the present invention relate to gate structures for forming devices, such as high-k dielectric/metal gate semiconductor transistors. Specifically, some examples, after depositing the interfacial layer and the high-k dielectric layer on the semiconductor fin structure, the high-k dielectric layer is subjected to a thermal treatment (e.g., a high temperature millisecond anneal process) in a controlled nitrogen-containing ambient to incorporate nitrogen into the high-k dielectric layer. The millisecond anneal process may confine nitrogen in the high-k dielectric layer and reactivate dopants in the source/drain regions and minimize dopant diffusion from the source/drain regions. Thus, short channel effects can be avoided. The nitrogen containing ambient also prevents regrowth of the interfacial layer during the annealing process. Among other advantages, device degradation problems such as time-dependent dielectric breakdown may be improved, and device performance may be improved.

The foregoing has outlined broadly some embodiments of the invention. It is contemplated that the concepts of the embodiments of the present invention may be implemented in planar transistor devices or three-dimensional transistor devices, such as semiconductor device 40 described in embodiments of the present invention. Some examples of devices that may be implemented as described herein include fin field effect transistors, horizontally wrap-around gate field effect transistors, vertically wrap-around gate field effect transistors, nanowire channel field effect transistors, strained semiconductor devices, or silicon-on-insulator devices.

Fig. 1 is a three-dimensional view of a semiconductor device 40 in some embodiments. In one embodiment, the semiconductor device 40 is an intermediate structure of a finfet. It will be appreciated by those skilled in the art that the embodiments described herein may be modified to implement other content. Although the figures and the content illustrate various steps, the illustrations do not limit the order of the steps, nor do they imply whether there are additional intermediate steps between the steps. Unless otherwise specified, steps performed sequentially in the description are for illustrative purposes only and do not exclude the case where individual steps are actually performed simultaneously or at least partially (not completely) overlapped when performed.

Semiconductor device 40 includes fin 46 on semiconductor substrate 42. Fins 46 may extend upward from the surface of semiconductor substrate 42. Semiconductor substrate 42 includes isolation regions 44, and fins 46 project through and above isolation regions 44. In the illustrated example, fins 46 project from between adjacent isolation regions 44. A dummy gate stack comprising interfacial dielectric layer 62, dummy gate layer 64 over interfacial dielectric layer 62, and mask layer 66 over dummy gate layer 64 is situated on the top surface of fin 46 and along the sidewalls of fin 46. Source/drain regions 52a and 52b are located in both side regions of the fin (relative to the dummy gate stack). Fig. 1 also shows a reference section a-a used in subsequent figures. Cross-section a-a is a plane along the channel in fin 46 between source/drain regions 52a and 52b on both sides.

Fig. 2-10 are cross-sectional views, taken along section a-a of fig. 1, of respective intermediate structures in forming a semiconductor device, in some embodiments. The semiconductor device may be a field effect transistor, which may be the semiconductor device 40 shown in fig. 1, such as a finfet structure. As shown in fig. 2, the semiconductor substrate 42 has at least a portion on which a semiconductor device is formed. The semiconductor substrate 42 may be or include a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., with p-type dopants or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 42 may include a semiconductor element such as silicon or germanium, a semiconductor compound, a semiconductor alloy, or a combination thereof. Generally, fins 46 may be formed in semiconductor substrate 42 by etching trenches in semiconductor substrate 42 using photolithography and etching processes. An insulating material, such as silicon oxide, silicon nitride, the like, multiple layers thereof, or combinations thereof, may be deposited into the trench and recessed to form isolation region 44, and fin 46 may protrude from isolation region 44.

The interfacial dielectric layer 62, dummy gate layer 64, and mask layer 66 for the dummy gate stack may be formed or deposited sequentially by any suitable process, followed by patterning these layers into the dummy gate stack. For example, interfacial dielectric layer 62 may comprise or may be silicon oxide, silicon nitride, the like, or multiple layers thereof, while dummy gate layer 64 may comprise or may be silicon (e.g., amorphous silicon or polysilicon) or any suitable material. The masking layer 66 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The interfacial dielectric layer 62, dummy gate layer 64, and layers for the mask layer 66 may then be patterned to form a dummy gate stack. For example, the method of patterning the layer may employ photolithography and one or more etching processes.

As shown in fig. 2, gate spacers 68 are formed along sidewalls of the dummy gate stack (e.g., sidewalls of interfacial dielectric layer 62, dummy gate layer 64, and mask layer 66) and on fin 46 on semiconductor substrate 42. For example, the gate spacers 68 may be formed by conformably depositing one or more layers used for the gate spacers 68, rather than isotropically etching one or more layers. The one or more layers used for the gate spacers 68 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, multilayers thereof, or combinations thereof.

Source/drain regions 70 are then formed in fin 46 on both sides of the dummy gate stack. In some examples, source/drain regions 70 may be formed by masking dummy gate stack and gate spacers 68 and implanting dopants into fin 46. In other examples, an etch process may be performed using dummy gate stack and gate spacers 68 as a mask to recess fin 46, followed by epitaxial growth of epitaxial source/drain regions 70 in the recess, as shown. The epitaxial source/drain regions 70 may comprise or may be silicon germanium, silicon carbide, silicon phosphide, germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. As shown, epitaxial source/drain regions 70 may be raised (relative to fin 46). The epitaxial source/drain regions 70 may be doped in-situ during epitaxial growth and/or the epitaxial source/drain regions 70 may be implanted after epitaxial growth. The source/drain regions 70 may thus be epitaxially grown on both sides of the dummy gate stack and may be co-implanted.

As shown in fig. 3, a first interlayer dielectric layer 72 is formed on fin 46 of semiconductor substrate 42 and may be formed along gate spacers 68. Although not specifically illustrated, the contact etch stop layer of some embodiments may be conformably formed on fin 46 of semiconductor substrate 42 and along gate spacers 68. A first interlayer dielectric layer 72 may be formed on the contact etch stop layer. Generally, the etch stop layer provides a mechanism for stopping the etch process when forming contacts or vias. The etch stop layer may be comprised of a dielectric material and may have an etch selectivity different from that of an adjacent layer, such as the first interlayer dielectric layer 72. For example, a contact etch stop layer may be conformally deposited on fin 46, dummy gate stack, and gate spacer 68. The contact etch stop layer may comprise or may be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof. For example, a first interlevel dielectric layer 72 is then deposited over the contact etch stop layer. The first interlayer dielectric layer 72 may comprise or may be silicon oxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon oxide), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, carbon-silicon material, combinations thereof, the like, or combinations thereof.

After depositing the first interlayer dielectric layer 72, a chemical mechanical polishing process or the like may be used to planarize the first interlayer dielectric layer 72. The top surface of the first interlayer dielectric layer 72 may be planarized to be coplanar with the top surface of the dummy gate layer 64, i.e., the dummy gate layer 64 is exposed through the first interlayer dielectric layer 72. The planarization process may remove the mask layer 66 of the dummy gate stack (and in some instances the upper portion of the gate spacer 68), thereby exposing the upper surface of the dummy gate layer 64 of the dummy gate stack through the first interlayer dielectric layer 72.

As shown in fig. 4, the dummy gate stack is removed to form a recess 74 between the gate spacers 68. Once the dummy gate layer 64 is exposed from the first ild layer 72, the dummy gate layer 64 and interfacial dielectric layer 62 of the dummy gate stack are removed, and the removal process may be one or more etching processes.

As shown in fig. 5, an interfacial dielectric layer 80 and a gate dielectric layer 82 are formed in the recess 74. In some examples as shown, interfacial dielectric layer 80 is formed on fin 46 of semiconductor substrate 42 exposed by recess 74 and between gate spacers 68. Interfacial dielectric layer 80 may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride) formed by thermal or chemical oxidation of fin 46, and/or another dielectric layer formed using any suitable deposition technique. In some examples, interfacial dielectric layer 62 of the dummy gate stack may remain and be in the place of interfacial dielectric layer 80. In another example, the interfacial dielectric layer 80 may be formed from a variety of process steps, such as a native oxide formed by a cleaning process. In other examples, the interfacial dielectric layer 80 may be omitted.

Gate dielectric layer 82 is conformably deposited in recess 74, i.e., where the dummy gate stack is removed (e.g., over interfacial dielectric layer 80 and along sidewalls 73 of gate spacers 68). A gate dielectric layer 82 is also situated on the upper surfaces of gate spacers 68, first interlayer dielectric 72, and the contact etch stop layer (if employed). The gate dielectric layer 82 and the interfacial dielectric layer 80 may be referred to as a high-k gate stack. The gate dielectric layer 82 may be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other dielectric materials. The high-k dielectric material may have a dielectric constant greater than or equal to about 7.0 and may comprise a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. Some examples of gate dielectric layer 82 include, but are not limited to, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, or the like. In some embodiments, gate dielectric layer 82 is hafnium oxide. The deposition method for gate dielectric layer 82 may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of gate dielectric layer 82 may be between aboutTo aboutBetween, such as about

After forming gate dielectric layer 82 over interfacial dielectric layer 80, semiconductor device 40 may be heat treated in a controlled environment to dope nitrogen into gate dielectric layer 82. Doping gate dielectric layer 82 with nitrogen may be advantageous because nitrogen may passivate surface defects of gate dielectric layer 82, such as oxygen vacancies filled in gate dielectric layer 82 and/or dangling bonds connected to the surface of gate dielectric layer 82. The nitrogen may also increase the etch resistance of the gate dielectric layer 82 during subsequent patterning processes and provide a barrier against diffusion of defects/dopants from gate stack layers (e.g., work function adjusting layers, barrier/adhesion layers, and gate metal fill layers) subsequently formed on the gate dielectric layer. Various thermal processes described below may include a rapid anneal process using a high temperature to provide a desired nitrogen concentration in the gate dielectric layer 82. These thermal treatments may prevent nitrogen from diffusing into interfacial dielectric layer 80, the fins, and/or any underlying layers.

The rapid thermal annealing process may be any suitable thermal process, such as a laser annealing process, a flash lamp annealing process, or any advanced process using suitable optical radiation to perform the annealing process in a very short time, such as on the order of milliseconds or less, e.g., on the order of nanoseconds or even picoseconds. During the heat treatment, the semiconductor substrate 42 is preheated and maintained at the preheated temperature, so that a rapid thermal annealing process may be performed on the semiconductor substrate 42 having the increased temperature to reduce the thermal exposure of the semiconductor substrate 42 to the high temperature annealing process. The pre-heating temperature is low enough to avoid uncontrolled diffusion of dopants from the source/drain regions, such as less than or equal to about 800 ℃. The pre-heating stage may be combined with a rapid thermal anneal process to help limit the migration of nitrogen atoms in the gate dielectric layer 82.

Once the semiconductor substrate 42 reaches the preheat temperature, a rapid thermal anneal process may be performed to further heat the substrate surface or at least a portion of the substrate to the anneal temperature. The annealing temperature may be greater than or equal to the recrystallization temperature of gate dielectric layer 82, but less than the melting point of gate dielectric layer 82. The rapid thermal anneal process may produce a more crystalline structure from a region of the gate dielectric layer 82 (as compared to a previously deposited amorphous structure). In most cases, the rapid thermal anneal process may recrystallize the annealed region of the gate dielectric layer 82 to a crystallinity of at least 40% or more, such as between about 45% and about 100%, for example, between about 50% and about 70%.

The nitrogen may diffuse to a depth of the gate dielectric layer 82 and convert at least a portion of the gate dielectric layer to a nitride portion, depending on the type of rapid thermal anneal process. In the case where gate dielectric layer 82 is hafnium oxide, the nitride portion may be hafnium oxynitride having a hafnium-oxygen-nitrogen bond, or hafnium nitride having a hafnium-nitrogen bond. The ratio of the thickness of the nitrided portion to the total thickness of the gate dielectric layer 82 may be between about 1:1.1 and about 1: 2.5. If a laser anneal process is employed, a plurality of localized nitride regions (i.e., nitrided portions) may be formed along and across the exposed surface of the gate dielectric layer 82, as described in more detail below. If a flash lamp anneal process is used, a uniform nitride layer (i.e., nitrided portion) may be formed along and across the exposed surface of the gate dielectric layer 82. In any case, the concentration of the nitride portion in the gate dielectric layer 82 may be graded along the thickness direction of the gate dielectric layer 82. For example, an inner portion of the gate dielectric layer 82 toward the gate replacement structure (e.g., away from the respective gate spacers 68 on which vertical portions of the gate dielectric layer 82 are formed, or away from the semiconductor substrate 42 on which horizontal portions of the gate dielectric layer 82 are formed) may have a maximum nitrogen concentration, while the nitrogen concentration of the gate dielectric layer 82 decreases with increasing distance from the portion of maximum concentration (e.g., away from the replacement gate structure in an outward direction from the replacement gate structure).

Inset 89 of fig. 6 is a partial magnified view showing the thermal gradient 87 in the gate dielectric layer 82 formed by the laser annealing process 91 in some embodiments. Thermal gradient 87 may define localized nitrided region 67 in gate dielectric layer 82. It can be seen that a peak temperature region 85 can be formed at the upper surface 81 of the gate dielectric layer 82 (or near the upper surface 81), i.e., at the upper surface 81 where the laser beam impinges. The temperature drops significantly from the peak temperature region 85 to a low temperature region 83 away from the peak temperature region 85. Because the laser anneal process 91 is scanned over the top surface 81 and the dwell time of the laser beam is on the order of milliseconds, the thermal gradient 87 may be confined to the gate dielectric layer 82 and not extend into the interfacial dielectric layer 80. When the laser beam sweep ends or moves to the next point, the annealing energy (and thermal gradient 87) dissipates.

An inset 93 in fig. 7 is a partial enlarged view illustrating a thermal gradient 95 formed in the gate dielectric layer 82 by a flash lamp annealing process 97 according to other embodiments. Since flash illumination is a flood illumination process, the flash can illuminate all areas of the substrate surface in a single exposure. A thermal gradient 95 may define nitride layer 69 in gate dielectric layer 82. The thermal gradient 95 may have a peak temperature region 63 and a low temperature region 65 away from the peak temperature region 63. The temperature is reduced along the thickness direction of the gate dielectric layer 82. Likewise, since the flash lamp anneal process 97 is very short in duration, the thermal gradient 95 may be confined in the gate dielectric layer 82 and not extend to the interfacial dielectric layer 80. When the flash lamp is pulsed or turned off, the annealing energy and thermal gradient 95 dissipate.

In the laser annealing process 91 or the flash lamp annealing process 97, the energy may excite the movement of nitrogen atoms in the annealing region. As the annealing energy dissipates in the substrate, the nitrogen atoms are substantially frozen into the crystal lattice in the gate dielectric layer 82. The laser anneal process 91 or the flash lamp anneal process 97 may limit the movement of nitrogen atoms in the crystal lattice of the gate dielectric layer 82 and nitrogen atoms do not diffuse through the entire thickness of the gate dielectric layer 82. As such, nitrogen atoms are confined within gate dielectric layer 82 and do not diffuse into interfacial dielectric layer 80 and/or fin 46, which may otherwise result in degradation of semiconductor device 40. Interfacial dielectric layer 80 and/or fin 46 are free of nitrogen. In some embodiments, the dopant (e.g., nitrogen atom) concentration in the gate dielectric layer 82 may be between about 3 atomic% and about 20 atomic% (or between about 0.5 × 10)²¹Atom/cm³To about 8X 10²¹Atom/cm³In between).

In some embodiments, the thermal treatment is a laser annealing process performed in a nitrogen-containing ambient. The nitrogen-containing ambient may be created by introducing a nitrogen-containing gas, such as nitrogen, ammonia, a combination of nitrogen and hydrogen, and/or any combination thereof, into the process chamber. In some examples, ammonia is used to create a nitrogen-containing environment. If desired, the nitrogen-containing gas may optionally be mixed with one or more of a non-reactive gas such as helium, argon, neon, xenon, or the like. The process chamber may be any suitable process chamber or combination of process chambers suitable for forming and annealing gate dielectric layer 82.

The substrate support (e.g., a wafer pedestal supporting the semiconductor device 40) may be preheated and maintained at a preheated temperature while the nitrogen-containing gas is introduced into the process chamber and/or prior to introducing the nitrogen-containing gas into the process chamber. The pre-heating temperature may be between about 150 ℃ to about 650 ℃, such as between about 200 ℃ to about 600 ℃, for example between about 250 ℃ to about 500 ℃. The time that the substrate support is maintained at the pre-heat temperature may be between about 2 seconds and about 20 seconds, such as between about 8 seconds and about 10 seconds. A laser annealing process is then performed with a laser beam from an energy source that traverses the exposed portion of the gate dielectric layer 82 to form a plurality of locally nitrided regions (e.g., locally nitrided regions 67 of fig. 6) in the gate dielectric layer 82. The laser beam may be sequentially applied or scanned to portions of the gate dielectric layer 82 of the semiconductor device 40. For example, the laser beam may anneal a first portion of gate dielectric layer 82, and then semiconductor substrate 42 and/or the laser beam may be moved so that the laser beam may anneal a second portion of gate dielectric layer 82.

The energy source may be any kind of laser, such as a gas laser, an excimer laser, a solid-state laser, a fiber laser, a semiconductor laser, or the like. The laser beam may have a fixed energy flux. A laser beam may be applied to the surface of gate dielectric layer 82 while transferring or scanning semiconductor device 40 relative to the energy applied to the surface of gate dielectric layer 82 (and vice versa). In any case, the laser scan rate may be between about 15 mm/sec to about 650 mm/sec, which may depend on the residence time required for the application. The laser beam may be operated to achieve a desired wavelength range and intensity range. In some embodiments, the laser beam has a wavelength between about 200nm and about 20 microns, such as between about700nm to about 1200nm, for example between about 950nm to about 1000 nm. The energy density of the laser beam may be between about 0.1W/cm²To about 10W/cm²In the meantime. Performing the laser annealing process in this manner may allow each portion irradiated by the laser beam to be instantaneously heated to a temperature greater than or equal to about 600 ℃, such as greater than or equal to about 800 ℃, for example, between about 850 ℃ and about 1400 ℃.

The chamber pressure may be maintained at greater than or equal to about 40Torr, such as greater than or equal to about 450Torr, for example, between about 650Torr and about 850Torr during the laser annealing process. In some embodiments, the chamber pressure is maintained at atmospheric pressure (760 Torr). The dwell time of the laser beam may be between about 0.01 milliseconds and about 100 milliseconds, such as between about 0.1 milliseconds and about 1 millisecond, for example 0.2 milliseconds. In instances where nanosecond annealing is desired, the dwell time of the laser beam may be between about 1 nanosecond and about 100 nanoseconds.

The energy source is then turned off to cool the semiconductor device 40. The semiconductor device 40 may be cooled to cool the substrate using any suitable technique, such as by circulating nitrogen, argon, or any suitable cooling liquid, such as water, through the substrate support. It is contemplated that the adjustment of the above conditions will depend on the absorption properties of the material to be annealed, as well as the speed of transport and scanning of the substrate (relative to the laser beam applied to the desired area of the substrate).

In some embodiments, the heat treatment is a flash lamp annealing process performed in a nitrogen-containing environment containing ammonia and/or nitrogen. The nitrogen-containing ambient may be created by introducing a nitrogen-containing gas, such as nitrogen, ammonia, a combination of nitrogen and hydrogen, and/or any combination thereof, into the process chamber. In some examples, ammonia and nitrogen are used to create a nitrogen-containing environment. The nitrogen and ammonia may be introduced into the process chamber separately, in any desired order, or premixed as a gas mixture. In any case, the volume% of ammonia in the environment may be between about 10% and about 100%, such as between about 40% and about 95%, such as between about 50% and about 85%, or between about 65% and about 80%, and the other gas in the environment is nitrogen. In one embodiment, the volume% of ammonia in the environment is 50%. In one embodiment, the volume% ammonia in the environment is 70%. The volume% may be adjusted to achieve a desired crystallinity of gate dielectric layer 82. In general, the higher the volume% of ammonia, the lower the crystallinity of gate dielectric layer 82 may be. In most cases, the flash lamp annealing process may recrystallize the gate dielectric layer 82, which may have a crystallinity of at least 40% or more, such as between about 50% and about 90%, for example between about 50% and about 70%.

Similarly, the substrate support (e.g., a susceptor for supporting the semiconductor device 40) may be preheated and maintained at a preheating temperature, which may be between about 450 ℃ and about 850 ℃, such as between about 500 ℃ and about 820 ℃, for example between about 600 ℃ and about 800 ℃, while the nitrogen-containing gas is introduced into the process chamber and/or before the nitrogen-containing gas is introduced into the process chamber. The time the substrate support is maintained at the pre-heat temperature may be between about 3 seconds and about 20 seconds, such as between about 4 seconds and about 6 seconds. Once the semiconductor device 40 reaches the pre-heating temperature and is stabilized, the exposed surface of the gate dielectric layer 82 may be irradiated by light from a light source to perform a flash lamp annealing process. In some examples, all exposed surfaces of gate dielectric layer 82 are irradiated with light in the presence of ammonia and nitrogen to form a nitride layer (e.g., nitride layer 69 of fig. 7) in gate dielectric layer 82.

The light source may be a plurality of radiation emitting lamps such as xenon, argon, or krypton discharge lamps, or a tungsten halogen lamp. In some embodiments, the light source is a xenon flash lamp. During the flash lamp annealing process, the chamber pressure may be maintained at between about 1Torr to about 100Torr, such as between about 10Torr to about 100Torr, for example between about 20Torr to about 40 Torr. The energy density of the light irradiation may be between about 5J/cm²To about 60J/cm²Between, e.g., about 10J/cm²To about 45J/cm²In the meantime. A flash lamp anneal process is performed to temporarily elevate the exposed surface of the gate dielectric layer 82 having light irradiated thereon to a temperature greater than or equal to about 600 c, such as greater than or equal to about 800 c, for example, between about 850 c and about 1400 c. The irradiation time may be between about 0.1 milliseconds and about 100 milliseconds, such as between about 0.2 milliseconds and about 5 milliseconds, for exampleBetween about 1.4 milliseconds and about 2 milliseconds.

The light source is then turned off to cool the semiconductor device 40. The cooling method of the semiconductor device 40 may employ any technique for cooling the substrate, such as by circulating nitrogen, argon, or any suitable cooling liquid, such as water, through the substrate support. It is contemplated that the conditions and the ultimate temperature achievable for the portion having light incident thereon may depend on the intensity of the flash lamp and the optical properties of the material being annealed.

It will be appreciated by those skilled in the art that the above-described processes and parameters may be applied to other layers in the gate stack, such as one or more barrier and/or cap layers and one or more work function adjusting layers that are subsequently deposited on the gate dielectric layer 82. The parameters described herein may vary depending on the size and/or application of the individual components of the semiconductor device structure.

As shown in fig. 8, a barrier layer 86 is conformally deposited over the gate dielectric layer 82. The barrier layer 86 may comprise or may be tantalum nitride, tantalum silicon nitride, tantalum carbon nitride, tantalum aluminum nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. In some embodiments, the barrier layer 86 is titanium silicon nitride. The thickness of the barrier layer 86 may be between aboutTo aboutIn the meantime.

As shown in fig. 9, a first work function adjusting layer 100, a second work function adjusting layer 102, a barrier/adhesion layer 104, and a gate metal fill layer 106 are sequentially formed on the barrier layer 86. The first work function adjusting layer 100 may be conformably deposited on the barrier layer 86. The first work function adjustment layer 100 may comprise or may be titanium nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, tantalum silicon nitride, tantalum carbonitride, tungsten nitride, tungsten carbide, tungsten carbonitride, cobalt, platinum, and the likeOr a combination thereof, and the deposition method may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the first work function adjusting layer 100 may be between aboutTo aboutIn the meantime. The second work function adjusting layer 102 may be conformally deposited over the first work function adjusting layer 100. The second work function adjusting layer 102 may comprise or may be titanium aluminum carbide, titanium aluminum alloy, tantalum aluminum carbide, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the second work function adjusting layer 102 may be between aboutTo aboutIn the meantime. In some examples, the first and second work function adjusting layers 100, 102 may be omitted. Other examples may have various other arrangements of the work function adjusting layer to achieve the desired performance of the device to be formed. For example, a different number of work function adjusting layers may be employed, having multiple materials and/or thicknesses. In some examples, the p-type field effect transistor and the n-type field effect transistor may have different work function adjusting layers.

The barrier/adhesion layer 104 may be conformally deposited over the second work function adjusting layer 102. The barrier/adhesion layer 104 may comprise or may be titanium nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, tantalum silicon nitride, tantalum carbonitride, tungsten nitride, tungsten carbide, tungsten carbonitride, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the barrier/adhesion layer 104 may be between aboutTo aboutIn the meantime. A gate metal fill layer 106 may then be deposited over the barrier/adhesion layer 104. The gate metal fill layer 106 may fill the recess 74 where the dummy gate stack was removed. The gate metal fill layer 106 may be or include a metal-containing material such as tungsten, cobalt, ruthenium, aluminum, copper, multilayers thereof, or combinations thereof. The deposition method of the gate metal filling layer 106 may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, physical vapor deposition, or any suitable deposition technique.

As shown in fig. 10, the excess portions of the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function adjusting layer 102, the first work function adjusting layer 100, the barrier layer 86, and the gate dielectric layer 82 above the upper surfaces of the first interlayer dielectric layer 72 and the gate spacer 68 are removed. For example, a planarization process (e.g., chemical mechanical polishing) may be used to remove the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function tuning layer 102, the first work function tuning layer 100, the barrier layer 86, and portions of the gate dielectric layer 82 above the upper surfaces of the first interlayer dielectric layer 72 and the gate spacers 68. Thus, a replacement gate structure comprising the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function tuning layer 102, the first work function tuning layer 100, the barrier layer 86, and the gate dielectric layer 82 may be formed.

As shown in fig. 10, a second interlayer dielectric layer 110 is formed. A second interlayer dielectric layer 110 is deposited over the first interlayer dielectric layer 72, the replacement gate structure, and the gate spacers 68. An etch stop layer may be formed between the first interlayer dielectric layer 72 and the second interlayer dielectric layer 110. For example, an etch stop layer may be deposited on the first interlayer dielectric layer 72, the replacement gate structure, and the gate spacers 68. For example, a second interlayer dielectric layer 110 may then be deposited on the etch stop layer. The etch stop layer and the second interlayer dielectric layer 110 may be or comprise the same or similar materials, and the formation method thereof may employ any acceptable technique. Both of which may be as described above for the contact etch stop layer and the first interlayer dielectric layer 72, respectively. After depositing the second interlayer dielectric layer 110, the second interlayer dielectric layer 110 may be planarized by chemical mechanical polishing or the like.

As shown in fig. 10, a conductive structure is formed through the second interlayer dielectric layer 110 and the first interlayer dielectric layer 72 to the source/drain region 70. The opening may pass through the second interlayer dielectric layer 110 and the first interlayer dielectric layer 72. Each opening exposes a respective source/drain region 70. For example, the opening may be formed by suitable photolithography and etching processes. The gasket 112 may be formed in the opening. Liner 112 may be conformally deposited along the sidewalls of the opening and the upper surface of source/drain region 70. Liner 112 may be a diffusion barrier layer, adhesion layer, or the like. The liner 112 may comprise or may be titanium, titanium nitride, tantalum nitride, or the like, and its deposition method may be any suitable deposition technique. An annealing process may be performed to facilitate a reaction between at least respective portions of the liner 112 and the source/drain regions 70, thereby forming silicide regions 114 in the respective source/drain regions 70. A conductive material 116 is then formed over the liner 112 in the opening. The conductive material 116 may be or include a metal such as cobalt, tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or combinations thereof, and may be deposited by any suitable deposition technique. A planarization process, such as chemical mechanical polishing, may be performed to remove the excess conductive material 116 and the liner 112 from the top surface of the second ild layer 110. The remaining spacers 112, silicide regions 114, and conductive material 116 form conductive structures to the respective source/drain regions 70.

Subsequent processing may be performed on the semiconductor device to form various structures and regions. For example, subsequent processing may form multiple layers (e.g., metal layers or intermetal dielectric layers) of various contact/via/line and interconnect structures on the semiconductor substrate 42 containing the semiconductor device 40 configured to connect various structures to form functional circuitry. The functional circuitry may contain one or more devices, such as one or more semiconductor devices 40.

Embodiments described herein relate to forming a gate structure of a device, such as a replacement gate process and the device formed thereby. In some examples, after depositing the interfacial dielectric layer and the gate dielectric layer, a rapid annealing process, such as a laser annealing process or a flash lamp annealing process, may be performed in a controlled nitrogen-containing ambient to form a nitride portion in the gate dielectric layer. The nitrided portion passivates the gate dielectric layer surface defects and acts as a barrier to etch chemistries and defects/dopants from subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Specifically, the millisecond rapid thermal anneal process may confine nitrogen atoms in the gate dielectric layer from diffusing to the underlying interfacial dielectric layer and/or any adjacent structures, such as fins. A millisecond anneal process is performed in a controlled nitrogen containing ambient to achieve the desired nitrogen concentration in the gate dielectric without unnecessarily regrowing the interfacial layer. The ultra-short anneal process may also reactivate dopants in the source/drain regions and minimize dopant diffusion from the source/drain regions during the formation of the initial interlayer dielectric layer (e.g., the first interlayer dielectric layer 72) or the gate spacers. Thus, short channel effects can be avoided. Among other advantages, device degradation problems such as time-dependent dielectric breakdown may be improved, and device performance may be improved.

In one embodiment, a method for semiconductor processing is provided. The method includes conformably forming a gate dielectric layer on a fin extending from a substrate, the gate dielectric layer conformably along sidewalls of a plurality of gate spacers on the fin; nitriding the gate dielectric layer by adopting a laser annealing process or a flash lamp annealing process in an ammonia-containing environment; and forming one or more metal-containing layers on the gate dielectric layer.

In some embodiments, the step of nitridizing the gate dielectric layer is a laser annealing process with a chamber pressure between 650Torr and 850Torr and a laser beam dwell time between 0.1 milliseconds and 1 millisecond.

In some embodiments, the method further comprises preheating the substrate support on which the substrate is positioned at a temperature between 200 ℃ and 600 ℃ for between 2 seconds and 20 seconds before performing the laser annealing process.

In some embodiments, the laser beam is scanned across the exposed surface of the gate dielectric layer at a scan rate between 15 mm/sec and 650 mm/sec.

In some embodiments, the laser annealing process heats each portion of the gate dielectric layer having the laser beam irradiated thereon to between 850 ℃ and 1400 ℃.

In some embodiments, the step of nitridizing the gate dielectric layer is a flash lamp annealing process with a chamber pressure between 10Torr and 100Torr and a radiation lamp with an exposure time between 0.2 milliseconds and 5 milliseconds.

In some embodiments, flash lamp annealing is performed to raise the exposed surface of the gate dielectric layer having the radiation irradiated thereon to between 850 ℃ and 1400 ℃.

In some embodiments, the ammonia-containing environment further comprises nitrogen, and the volume% of nitrogen in the ammonia-containing environment is between about 10% and about 100%.

In some embodiments, the method further comprises preheating the substrate support on which the substrate is positioned at a temperature between about 450 ℃ and about 850 ℃ for between about 3 seconds and about 20 seconds before performing the flash lamp annealing process.

In another embodiment, a method for semiconductor processing is provided. The method includes forming an interfacial dielectric layer along a fin surface extending from a substrate; forming a gate dielectric layer on the interfacial dielectric layer; nitridizing the gate dielectric layer in an ammonia-containing environment using a laser beam or a radiation emitting lamp; and forming a metal gate on the gate dielectric layer.

In some embodiments, the environment further comprises nitrogen.

In some embodiments, the method further comprises preheating the substrate support on which the substrate is positioned before nitriding the gate dielectric layer, and the preheating is at a temperature between 450 ℃ and 850 ℃.

In some embodiments, the volume% of ammonia in the environment is between 10% and 100%.

In some embodiments, the step of nitridizing the gate dielectric layer comprises irradiating the exposed surface of the gate dielectric layer with radiation from a radiation lamp to raise the temperature of the exposed surface of the gate dielectric layer irradiated with the radiation to 850to 1400 ℃, wherein the irradiation time is between 0.2 to 5 milliseconds.

In some embodiments, the step of nitridizing the gate dielectric layer is sequentially scanning the laser beam across the portions of the gate dielectric layer such that each portion of the gate dielectric layer on which the laser beam is irradiated is heated to between 850 ℃ and 1400 ℃, and the irradiation time is between 0.1 milliseconds and 1 millisecond.

In another embodiment, a structure is provided. The structure includes a substrate having fins extending from the substrate; a nitrogen-free interfacial dielectric layer along a surface of the fin; a gate structure on the fin; a work function adjusting layer on the gate dielectric layer; and a gate metal fill layer on the work function adjusting layer. The gate structure includes: a gate dielectric layer on the interfacial dielectric layer and having a nitride portion with a nitrogen concentration of about 0.5 x 10²¹Atom/cm³To about 8X 10²¹Atom/cm³In the meantime.

In some embodiments, the crystallinity of the gate dielectric layer is between about 45% to about 100%.

In some embodiments, the gate structure is located between a first gate spacer and a second gate spacer, the first gate spacer and the second gate spacer are located on the fin, the gate dielectric layer is also along respective sidewalls of the first gate spacer and the second gate spacer, and the gate structure further comprises: a barrier layer on the gate dielectric layer, and a work function adjusting layer on the barrier layer; and a barrier/adhesion layer on the work function adjusting layer, and a gate metal filling layer is located on the barrier/adhesion layer.

In some embodiments, the gate dielectric layer comprises hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, or zirconium silicon oxide.

In some embodiments, the nitride portion includes a plurality of localized nitrided regions distributed across or along the exposed surface of the gate dielectric layer, or a nitride layer formed across or along the exposed surface of the gate dielectric layer.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalent substitutions and alterations can be made without departing from the spirit and scope of the present invention, and that these changes, substitutions and alterations can be made without departing from the spirit and scope of the present invention.