阅读说明：本技术 有机发光二极管显示装置及形成显示装置半导体层的方法 (Organic light emitting diode display device and method of forming semiconductor layer of display device ) 是由 郑宇镐 权世明 金允镐 成硕济 崔埈厚 于 2019-06-12 设计创作，主要内容包括：本公开涉及一种有机发光显示装置及形成显示装置半导体层的方法,该有机发光显示装置包括：第一薄膜晶体管,设置在基底上；和第二薄膜晶体管,设置在所述基底上并且与所述第一薄膜晶体管间隔开。所述第一薄膜晶体管包括第一半导体层、设置在所述第一半导体层上并且与所述第一半导体层重叠的第一导电层和设置在所述第一半导体层和所述第一导电层之间的第一绝缘层。所述第二薄膜晶体管包括第二半导体层和设置在所述第二半导体层上并且与所述第二半导体层重叠的第二导电层。所述第一半导体层设置在比所述第二半导体层高的层上,所述第一半导体层包括氧化物半导体,所述第二半导体层包括低温多晶硅(LTPS),并且所述第一绝缘层覆盖整个所述第一半导体层。(The present disclosure relates to an organic light emitting display device and a method of forming a semiconductor layer of the display device, the organic light emitting display device including: a first thin film transistor disposed on the substrate; and a second thin film transistor disposed on the substrate and spaced apart from the first thin film transistor. The first thin film transistor includes a first semiconductor layer, a first conductive layer provided on and overlapping the first semiconductor layer, and a first insulating layer provided between the first semiconductor layer and the first conductive layer. The second thin film transistor includes a second semiconductor layer and a second conductive layer disposed on and overlapping the second semiconductor layer. The first semiconductor layer is disposed on a higher layer than the second semiconductor layer, the first semiconductor layer includes an oxide semiconductor, the second semiconductor layer includes Low Temperature Polysilicon (LTPS), and the first insulating layer covers the entire first semiconductor layer.)

1. An organic light emitting display device, wherein the device comprises:

a first thin film transistor disposed on a substrate; and

a second thin film transistor disposed on the substrate and spaced apart from the first thin film transistor,

wherein the first thin film transistor includes a first semiconductor layer, a first conductive layer provided on and overlapping with the first semiconductor layer, and a first insulating layer provided between the first semiconductor layer and the first conductive layer,

wherein the second thin film transistor includes a second semiconductor layer and a second conductive layer which is provided over and overlaps with the second semiconductor layer,

wherein the first semiconductor layer is provided on a layer higher than the second semiconductor layer,

wherein the first semiconductor layer includes an oxide semiconductor,

wherein the second semiconductor layer comprises low temperature polysilicon, an

Wherein the first insulating layer covers the entire first semiconductor layer.

2. The apparatus of claim 1, wherein the apparatus further comprises:

a third conductive layer disposed on the second conductive layer and overlapping the second semiconductor layer; and

a second insulating layer disposed on the third conductive layer,

wherein the second insulating layer is provided on a layer lower than the first semiconductor layer.

3. The device of claim 2, wherein the second insulating layer has a thickness greater than or equal to

4. The apparatus of claim 3, wherein the second insulating layer comprises silicon oxide.

5. The device of claim 4, wherein the second insulating layer comprises less than or equal to 9 x 10²⁰Atom/cm³The hydrogen concentration of (c).

6. The apparatus of claim 2, wherein the apparatus further comprises: a third insulating layer disposed on the first conductive layer and formed on an entire surface of the substrate.

7. The device of claim 6, wherein the third insulating layer has a thickness greater than or equal to

8. The apparatus of claim 6, wherein the third insulating layer comprises multiple layers of silicon oxide and silicon nitride layers.

9. The device of claim 8, wherein the silicon oxide layer has a thickness greater than or equal toAnd the thickness of the silicon nitride layer is fromToWithin the range of (1).

10. The device of claim 1, wherein the oxide semiconductor is indium gallium zinc oxide.

11. The apparatus of claim 1, wherein the first semiconductor layer includes a source region and a drain region at a first end and an opposite second end of the first semiconductor layer, respectively, and includes a channel region between the source region and the drain region, and

wherein the source region and the drain region are doped with n-type impurity ions.

12. The device of claim 1, wherein the first insulating layer is formed on an entire surface of the substrate.

13. The device of claim 1, wherein the first insulating layer is formed over a portion of the substrate where the first insulating layer overlaps the first semiconductor layer.

14. The device of claim 13, wherein the first insulating layer overlaps the second semiconductor layer.

15. The device of claim 1, wherein the first insulating layer has a thickness greater than or equal toAnd the surface resistance of the first semiconductor layer is equal to or less than 1000 Ω/□.

16. The apparatus of claim 1, wherein a drive range of the second thin film transistor is greater than or equal to 2.9V.

17. An organic light emitting display device comprising:

a buffer layer disposed on a substrate;

a first semiconductor layer disposed on the buffer layer;

a first insulating layer disposed on the first semiconductor layer;

a first conductive layer disposed on the first insulating layer and overlapping the first semiconductor layer;

a second insulating layer disposed on the first conductive layer;

a second conductive layer disposed on the second insulating layer and overlapping the first semiconductor layer;

a third insulating layer disposed on the second conductive layer;

a second semiconductor layer disposed on the third insulating layer and not overlapping the first semiconductor layer;

a fourth insulating layer disposed on the second semiconductor layer;

a third conductive layer disposed on the fourth insulating layer and overlapping the second semiconductor layer; and

a fifth insulating layer disposed on the third conductive layer,

wherein the first semiconductor layer comprises low temperature polysilicon,

wherein the second semiconductor layer comprises an oxide semiconductor, an

Wherein the fourth insulating layer covers the entire second semiconductor layer.

18. The device of claim 17, wherein the oxide semiconductor is indium gallium zinc oxide.

19. The apparatus of claim 17, wherein the fourth insulating layer is formed over an entire surface of the substrate,

wherein the fourth insulating layer has a thickness greater than or equal toA thickness of, and

wherein the fourth insulating layer has a thickness of 9 × 10 or less²⁰Atom/cm³The hydrogen concentration of (c).

20. A method of forming a semiconductor layer of a display device, comprising the steps of:

sequentially stacking an oxide semiconductor, a first insulating layer, a conductive layer, and a second insulating layer on a third insulating layer, wherein the oxide semiconductor is a metal oxide semiconductor, and the second insulating layer includes a plurality of layers of silicon oxide and silicon nitride; and

subjecting a first end and an opposite second end of the oxide semiconductor to a reduction treatment by a heat treatment without etching the first insulating layer,

wherein hydrogen ions present in the second insulating layer are diffused into the first and second ends of the oxide semiconductor, wherein a conductive source region and a conductive drain region are formed at the first and second ends, respectively, and a low-conductivity region is formed in a central region of the oxide semiconductor overlapping the conductive layer,

wherein the heat treatment is performed at a temperature ranging from 90 ℃ to 110 ℃, and the surface resistances of the conductive source region and the conductive drain region are less than 1000 Ω/□.

Technical Field

Embodiments of the present disclosure are directed to an organic light emitting diode display device.

Background

Various types of electronic devices, including mobile phones, tablet computers, laptop computers, and the like, employ Flat Panel Displays (FPDs). Flat panel display devices, hereinafter referred to as display devices, include Liquid Crystal Display (LCD) devices, Plasma Display Panel (PDP) devices, Organic Light Emitting Display (OLED) devices, and the like. Recently, electrophoretic display (EPD) devices have also become widely used.

The organic light emitting display device displays an image by using an organic light emitting element that emits light due to recombination of electrons and holes. The organic light emitting display device includes a plurality of transistors that supply a driving current to the organic light emitting elements.

In general, a PMOS transistor is used as a transistor of the organic light emitting display device. However, there have been studies on the use of NMOS transistors alone or in combination with PMOS transistors.

Disclosure of Invention

Embodiments of the present disclosure can provide an organic light emitting display device capable of doping a semiconductor layer of an NMOS transistor with n-type impurity ions only by a heat treatment without a pretreatment.

According to an embodiment of the present disclosure, there is provided an organic light emitting display device. The organic light emitting display device includes: a first thin film transistor disposed on a substrate; and a second thin film transistor disposed on the substrate and spaced apart from the first thin film transistor. The first thin film transistor includes a first semiconductor layer, a first conductive layer provided on and overlapping the first semiconductor layer, and a first insulating layer provided between the first semiconductor layer and the first conductive layer. The second thin film transistor includes a second semiconductor layer and a second conductive layer disposed on and overlapping the second semiconductor layer. The first semiconductor layer is disposed on a higher layer than the second semiconductor layer, the first semiconductor layer includes an oxide semiconductor, the second semiconductor layer includes Low Temperature Polysilicon (LTPS), and the first insulating layer covers the entire first semiconductor layer.

According to an embodiment of the present disclosure, there is provided an organic light emitting display device. The organic light emitting display device includes: a buffer layer disposed on a substrate; a first semiconductor layer disposed on the buffer layer; a first insulating layer disposed on the first semiconductor layer; a first conductive layer disposed on the first insulating layer and overlapping the first semiconductor layer; a second insulating layer disposed on the first conductive layer; a second conductive layer disposed on the second insulating layer and overlapping the first semiconductor layer; a third insulating layer disposed on the second conductive layer; a second semiconductor layer disposed on the third insulating layer and not overlapping the first semiconductor layer; a fourth insulating layer disposed on the second semiconductor layer; a third conductive layer disposed on the fourth insulating layer and overlapping the second semiconductor layer; and a fifth insulating layer disposed on the third conductive layer. The first semiconductor layer includes Low Temperature Polysilicon (LTPS), the second semiconductor layer includes an oxide semiconductor, and the fourth insulating layer covers the entire second semiconductor layer.

According to another embodiment of the present disclosure, a method of forming a semiconductor layer of a display device is provided. The method comprises the following steps: sequentially stacking an oxide semiconductor, a first insulating layer, a conductive layer, and a second insulating layer on a third insulating layer, wherein the oxide semiconductor is a metal oxide semiconductor, and the second insulating layer includes silicon oxide (SiO)_x) And silicon nitride (SiN)_x) A plurality of layers of (a); and subjecting the first end and the opposite second end of the oxide semiconductor to a reduction treatment by heat treatment without etching the first insulating layer. Hydrogen ions (H +) present in the second insulating layer diffuse into the first and second ends of the oxide semiconductor, wherein a conductive source region and a conductive drain region are formed at the first and second ends, respectively, and a low-conductivity region is formed in a central region of the oxide semiconductor overlapping the conductive layer. The heat treatment is performed at a temperature ranging from 90 ℃ to 110 ℃, and the surface resistances of the conductive source region and the conductive drain region are less than 1,000 Ω/□.

According to the embodiments of the present disclosure, the semiconductor layer of the NMOS transistor may be ion-doped with n-type impurities only by the heat treatment, and the dehydrogenation of the PMOS transistor may be improved to increase the driving range.

Drawings

Fig. 1 illustrates an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Fig. 2 is a block diagram of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Fig. 3 is an equivalent circuit diagram of a pixel of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Fig. 4 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Fig. 5 to 7 are cross-sectional views illustrating a process of forming source and drain regions of an upper semiconductor layer according to an exemplary embodiment of the present disclosure.

Fig. 8 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Fig. 9 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Detailed Description

Features of embodiments of the inventive concepts and methods of accomplishing the same may be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.

In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. Throughout the specification, the same reference numerals may be used for the same or similar components.

The display device according to various exemplary embodiments of the present disclosure may be used as a display screen of various devices that present video or still images or a stereoscopic display device including a portable electronic device such as a mobile communication terminal, a smart phone, a tablet computer, a smart watch, or a navigation device and a device such as a television, a laptop computer, a monitor, an electronic billboard, or a device for the internet of things.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, an organic light emitting display device is described as an example of a display device. However, it will be understood that embodiments of the present disclosure are not so limited. The display device according to the embodiment may be included in other display devices such as a liquid crystal display device, a Field Emission Display (FED) panel, or an electrophoretic display device without departing from the spirit of the embodiments of the present disclosure. Like reference numerals may indicate like elements throughout the drawings.

Fig. 1 illustrates an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 1, an organic light emitting display device 60 according to an exemplary embodiment of the present disclosure includes a display area DA and a non-display area NDA.

According to an embodiment, the display area DA is an area in which an image is displayed. The display area DA may also be used to detect the external environment. That is, the display area DA may be used as an area for displaying an image or recognizing a touch or fingerprint of a user. According to an exemplary embodiment of the present disclosure, the display area DA has a generally flat area FA and an at least partially curved area BA. However, it will be understood that embodiments of the present disclosure are not so limited. The display area DA may have a completely flat shape.

According to an embodiment, the organic light emitting display device 60 includes a plurality of pixels 1 in the display area DA. Each of the pixels 1 includes an organic light emitting diode. The organic light emitting display device 60 displays an image using the pixels 1.

According to an embodiment, the non-display area NDA is an area in which an image is not displayed and is disposed at least one side of the display area DA. In an exemplary embodiment, a speaker module, a camera module M1, a sensor module M2, and the like are disposed in the non-display area NDA. In an exemplary embodiment, the sensor module M2 includes at least one of an illumination sensor, a proximity sensor (proximitiysensor), an infrared sensor, or an ultrasonic sensor.

Fig. 2 is a block diagram of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 2, the organic light emitting display device 60 includes a plurality of pixels 1 in a display area DA, a scan driver 20, a data driver 30, an emission control driver 40, and a controller 50 according to an embodiment.

According to an embodiment, the display area DA includes a plurality of pixels 1 arranged in a matrix form, wherein each of the pixels 1 is located at an intersection of a plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn.

According to an embodiment, a plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n and a plurality of emission control lines EL1 to ELn extend in a row direction, and a plurality of data lines DL1 to DLm extend in a column direction. The row and column directions are interchangeable. The initialization Voltage (VINT) supply line branches into a plurality of lines extending in the row direction. The first power voltage (ELVDD) supply line branches into a plurality of lines extending in a column direction. However, it will be understood that embodiments of the present disclosure are not so limited. The initialization Voltage (VINT) supply line and the first power supply voltage (ELVDD) supply line may be modified in various ways.

According to the embodiment, in the pixel 1 in the first row and the first column, three scan lines SL11, SL21, and SL31, one data line DL1, one emission control line EL1, one initialization Voltage (VINT) supply line, and one first power voltage (ELVDD) supply line pass through. The other pixels have similar lines as the pixels in the first row and the first column.

According to an embodiment, the controller 50 receives a plurality of externally supplied signals including a red image signal R, a green image signal G, and a blue image signal B, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal MCLK. Based on these signals, the controller 50 generates and transmits an emission control signal ESC to the emission control driver 40, generates and transmits red, green, and blue data signals DR, DG, and DB and a data control signal DCS to the data driver 30, and generates and transmits a scan control signal SCS to the scan driver 20.

According to an embodiment, the scan driver 20 generates three scan signals based on the received scan control signal SCS and transmits the three scan signals to each pixel 1 through the plurality of scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3 n. That is, the scan driver 20 sequentially transmits scan signals to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, and the third scan lines SL31 to SL3 n.

According to an embodiment, the data driver 30 transmits a data signal to each pixel 1 through a plurality of data lines DL1 to DLm based on the received red, green, and blue data signals DR, DG, and DB and the data control signal DCS. Each time the first scan signal is transmitted to the first scan lines SL11 to SL1n, the data signal is transmitted to the pixel 1 selected by the first scan signal.

According to the embodiment, the emission control driver 40 generates an emission control signal based on the emission control signal ECS received from the controller 50 and transmits the emission control signal to each pixel 1 through the respective emission control lines EL1 to ELn. The emission control signal controls the emission time of the pixel 1. The emission control driver 40 may be removed according to the internal structure of the pixel 1 or when the scan driver 20 generates the emission control signal as well as the scan signal.

According to an embodiment, each of the plurality of pixels 1 receives the first power supply voltage ELVDD and the second power supply voltage ELVSS. The first power supply voltage ELVDD has a predetermined high voltage level, and the second power supply voltage ELVSS has a voltage level lower than that of the first power supply voltage ELVDD.

According to the embodiment, each of the plurality of pixels 1 emits light of a predetermined luminance by receiving a driving current transmitted to the light emitting element according to a data signal transmitted through the respective data lines DL1 to DLm.

According to an embodiment, the first power supply voltage ELVDD, the second power supply voltage ELVSS, the initialization voltage VINT, and the like may be received from an external voltage source.

Fig. 3 is an equivalent circuit diagram of a pixel of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 3, according to an embodiment, a circuit of the pixel 1 of the organic light emitting display device 60 includes an organic light emitting diode OLED, a plurality of transistors T1 to T7, and a storage capacitor Cst. The circuit of the pixel 1 receives a DATA signal DATA, a first scan signal GW, a second scan signal GI, a third scan signal GB, an emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT.

According to an embodiment, the organic light emitting diode OLED includes an anode electrode and a cathode electrode. The storage capacitor Cst includes a first electrode and a second electrode.

According to an embodiment, the plurality of transistors includes first to seventh transistors T1 to T7. Each of the transistors T1 to T7 includes a gate electrode, a first electrode, and a second electrode. One of the first electrode and the second electrode of each of the transistors T1 to T7 is a source electrode and the other is a drain electrode.

According to an embodiment, each of the transistors T1 to T7 is a thin film transistor. Each of the transistors T1 to T7 may be a PMOS transistor or an NMOS transistor. In an exemplary embodiment, the first transistor T1 is a driving transistor, the second transistor T2 is a data transfer transistor, the fifth transistor T5 is a first emission control transistor, the sixth transistor T6 is a second emission control transistor, and the seventh transistor T7 is a bypass transistor, and each of the foregoing transistors is a PMOS transistor. On the other hand, the third transistor T3 is a compensation transistor, and the fourth transistor T4 initializes the transistors, and the third transistor T3 and the fourth transistor T4 are NMOS transistors. The PMOS transistor and the NMOS transistor have different characteristics. The NMOS transistors for implementing the third and fourth transistors T3 and T4 have relatively good turn-off characteristics that reduce leakage of the driving current Id during the emission period of the organic light emitting diode OLED.

Hereinafter, each of the elements will be described in detail.

According to an embodiment, the gate electrode of the first transistor T1 is connected to the first electrode of the storage capacitor Cst. A first electrode of the first transistor T1 is connected to the first power supply voltage ELVDD via a fifth transistor T5. A second electrode of the first transistor T1 is connected to an anode electrode of the organic light emitting diode OLED via a sixth transistor T6. The first transistor T1 receives the DATA signal DATA through the switching operation of the second transistor T2 to transmit the driving current Id to the organic light emitting diode OLED.

According to an embodiment, a gate electrode of the second transistor T2 is connected to a first scan signal (GW) terminal. A first electrode of the second transistor T2 is connected to a DATA signal (DATA) terminal. A second electrode of the second transistor T2 is connected to a first electrode of the first transistor T1 and to a first power supply voltage (ELVDD) terminal through the fifth transistor T5. The second transistor T2 is turned on according to the first scan signal GW and performs a switching operation to transfer the DATA signal DATA to the first electrode of the first transistor T1.

According to an embodiment, a gate electrode of the third transistor T3 is connected to the first scan signal GW terminal. A first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and to an anode electrode of the organic light emitting diode OLED via the sixth transistor T6. A second electrode of the third transistor T3 is coupled to a first electrode of the storage capacitor Cst, a first electrode of the fourth transistor T4, and a gate electrode of the first transistor T1. The third transistor T3 is turned on by the first scan signal GW to connect the gate electrode and the second electrode of the first transistor T1 so as to diode-connect the first transistor T1. Accordingly, a voltage difference equal to the threshold voltage of the first transistor T1 is generated between the first electrode and the gate electrode of the first transistor T1. The deviation of the threshold voltage of the first transistor T1 may be compensated for by supplying the DATA signal DATA compensating the threshold voltage to the gate electrode of the first transistor T1.

According to an embodiment, a gate electrode of the fourth transistor T4 is connected to a second scan signal (GI) terminal. A second electrode of the fourth transistor T4 is connected to an initialization Voltage (VINT) terminal. A first electrode of the fourth transistor T4 is coupled to the first electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on by the second scan signal GI to transmit the initialization voltage VINT to the gate electrode of the first transistor T1 so as to initialize the voltage at the gate electrode of the first transistor T1.

According to an embodiment, a gate electrode of the fifth transistor T5 is connected to the emission control signal EM terminal. A first electrode of the fifth transistor T5 is connected to the first power supply voltage ELVDD terminal. A second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2.

According to an embodiment, a gate electrode of the sixth transistor T6 is connected to the emission control signal EM terminal. A first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3. A second electrode of the sixth transistor T6 is connected to the anode electrode of the organic light emitting diode OLED.

According to an embodiment, the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM such that the driving current Id flows through the organic light emitting diode OLED.

According to an embodiment, a gate electrode of the seventh transistor T7 is connected to the third scan signal GB terminal. A first electrode of the seventh transistor T7 is connected to an anode electrode of the organic light emitting diode OLED. A second electrode of the seventh transistor T7 is connected to the initialization voltage VINT terminal. The seventh transistor T7 is turned on by the third scan signal GB to initialize the anode electrode of the organic light emitting diode OLED. In order to display the black image, the emission current of the organic light emitting diode OLED, which is reduced by the amount of the bypass current Ibp flowing from the anode electrode of the organic light emitting diode OLED through the seventh transistor T7, has the minimum current amount required for reliably presenting the black image. Therefore, it is possible to realize an image having accurate black luminance by using the seventh transistor T7, thereby improving contrast.

According to the embodiment, although the third scan signal GB is transmitted to the gate electrode of the seventh transistor T7, in other embodiments, the pixel circuit may be configured such that the emission control signal EM is transmitted to the gate electrode of the seventh transistor T7.

Further, according to the embodiment, although the second scan signal GI and the third scan signal GB are independent from each other, in other embodiments, the circuit may be configured such that the second scan signal GI and the third scan signal GB are the same signal electrically connected to each other.

According to an embodiment, the second electrode of the storage capacitor Cst is connected to the first power voltage ELVDD terminal. The first electrode of the storage capacitor Cst is connected to the gate electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the fourth transistor T4. The cathode electrode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS terminal. The organic light emitting diode OLED receives the driving current Id from the first transistor T1 and emits light to display an image.

According to an embodiment, each of the transistors T1 to T7 includes a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, which are PMOS transistors, are thin film transistors using Low Temperature Polysilicon (LTPS). The third transistor T3 and the fourth transistor T4 which are NMOS transistors are thin film transistors using an oxide semiconductor layer.

In the exemplary embodiment, a thin film transistor having a top gate structure in which a gate electrode of each of the transistors T1 to T7 is disposed over a semiconductor layer will be described as an example. However, it will be understood that embodiments of the present disclosure are not so limited. At least some of the transistors T1 to T7 may be thin film transistors having a bottom gate structure in which a gate electrode is disposed under a semiconductor layer.

Hereinafter, the pixel will be described in more detail with reference to a cross-sectional structure of the pixel.

Fig. 4 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 4, according to an embodiment, the respective layers of the pixel 1 include: the semiconductor device includes a substrate 110, a buffer layer 121, a lower semiconductor layer, a first insulating layer 122, a first conductive layer G1, a second insulating layer 123, a second conductive layer G2, a third insulating layer 124, an upper semiconductor layer, a fourth insulating layer 125, a third conductive layer G3, and a fifth insulating layer 126. Each of the respective layers disclosed above may be composed of a single layer or a plurality of layers, and another layer may be further provided between the respective layers.

According to an embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the organic light emitting display device 60 is a bottom emission organic light emitting display device or a dual emission organic light emitting display device, the transparent substrate 110 is used. When the organic light emitting display device 60 is a top emission organic light emitting display device, a translucent or opaque substrate 110 and a transparent substrate 110 may be used.

According to an embodiment, the substrate 110 is made of an insulating material such as glass, quartz, or polymer resin. Examples of polymeric materials include: polyethersulfone (PES), Polyacrylate (PA), Polyacrylate (PAR), Polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate (polyallylate), Polyimide (PI), Polycarbonate (PC), cellulose triacetate (CAT), Cellulose Acetate Propionate (CAP), or combinations thereof. The substrate 110 may include a metal.

According to an embodiment, the substrate 110 may be a rigid substrate 110 or a flexible substrate 110 that may be bent, folded, rolled, etc. Examples of the flexible material for the flexible substrate 110 include Polyimide (PI), but are not limited thereto.

According to an embodiment, the buffer layer 121 is disposed on the entire surface of the substrate 110. The buffer layer 121 prevents diffusion of impurity ions, penetration of moisture or external air, and provides a flat surface. The buffer layer 121 includes silicon nitride, silicon oxide, silicon oxynitride, or the like. The buffer layer 121 may be removed according to the type of the substrate 110, process conditions, and the like.

According to an embodiment, the lower semiconductor layer is an active layer forming channels of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

According to an embodiment, the lower semiconductor layer comprises Low Temperature Polysilicon (LTPS). However, it will be understood that embodiments of the present disclosure are not so limited. The lower semiconductor layer may include single crystal silicon, amorphous silicon, or the like.

According to an embodiment, a thin film transistor (LTPS TFT) including low temperature polysilicon generally exhibits excellent carrier mobility even with a small profile, and thus is suitable for implementing an integrated driving circuit. A low temperature polysilicon thin film transistor (LTPS TFT) is used for a component having a high operation speed because the low temperature polysilicon thin film transistor (LTPS TFT) has excellent carrier mobility. Despite the above-mentioned features, a low temperature polysilicon thin film transistor (LTPS TFT) has a different initial threshold voltage due to grain boundaries of a polysilicon semiconductor layer.

According to an embodiment, the lower semiconductor layer includes a source region S1 disposed at one side, a drain region D1 disposed at the other side, and a channel region a1 disposed between the source region S1 and the drain region D1. Portions of the lower semiconductor layer connected to the source electrode SE1 and the drain electrode DE1 of each of the transistors T1, T2, T5, T6, and T7, i.e., the source region S1 and the drain region D1, are doped with impurity ions, specifically, p-type impurity ions in the case of a PMOS transistor. A trivalent dopant such as boron (B) may be used as the p-type impurity ions.

According to an embodiment, the first insulating layer 122 is disposed on the lower semiconductor layer, and is typically disposed on the entire surface of the substrate 110. The first insulating layer 122 is a gate insulating layer having a gate insulating function.

According to an embodiment, the first insulating layer 122 includes a silicon compound, a metal oxide, or the like. For example, the first insulating layer 122 includes silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like. They may be used alone or in combination. The first insulating layer 122 may have a single layer or have a plurality of layers of different materials stacked on each other.

According to an embodiment, the first conductive layer G1 is disposed on the first insulating layer 122. At least a portion of the first conductive layer G1 overlaps with the lower semiconductor layer. As used herein, unless explicitly stated to the contrary, the phrase "one element overlaps another element" means that one element is over the other element in the thickness direction of the organic light emitting display device, that is, in the direction perpendicular to the surface of the substrate 110 in the drawing.

According to an embodiment, the first conductive layer G1 includes: a scan line for transmitting the first scan signal (GW in fig. 3), a scan line for transmitting the third scan signal (GB in fig. 3), a gate electrode of the first transistor T1, an emission control line for transmitting an emission control signal (EM in fig. 3), or an initialization voltage line for transmitting an initialization voltage (VINT in fig. 3).

According to an embodiment, the first conductive layer G1 includes at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer G1 may have a single layer or a plurality of layers.

According to an embodiment, the second insulating layer 123 covers the first conductive layer G1. The second insulating layer 123 is generally disposed on the entire surface of the substrate 110. The second insulating layer 123 is a gate insulating layer having a gate insulating function. The second insulating layer 123 may include the same material as the first insulating layer 122, or may include one or more other materials selected from the materials listed above for the first insulating layer 122. The second insulating layer 123 may have a single layer or a plurality of layers of different materials stacked on each other.

According to an embodiment, a second conductive layer G2 is disposed on the second insulating layer 123. The second conductive layer G2 overlaps at least part of the lower semiconductor layer and the first conductive layer G1. The second conductive layer G2 may include the same material as the first conductive layer G1, or may include at least one other material selected from the materials listed above for the first conductive layer G1. The second conductive layer G2 may have a single layer or multiple layers of different materials stacked on each other.

According to an embodiment, the second conductive layer G2 includes a storage capacitor (Cst in fig. 3) electrode line and another emission control line for transmitting an emission control signal EM.

According to an embodiment, the third insulating layer 124 insulates the second conductive layer G2 from an upper semiconductor layer to be described below. The third insulating layer 124 is disposed on the first conductive layer G1 and is generally formed on the entire surface of the substrate 110. The third insulating layer 124 is an interlayer dielectric layer.

According to an embodiment, the third insulating layer 124 includes, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or an inorganic insulating material such as polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutaneAn organic insulating material of alkene (BCB). The third insulating layer 124 may have a single layer or a plurality of layers of different materials stacked on each other.

According to an embodiment, an upper semiconductor layer is disposed on the third insulating layer 124. Specifically, the upper semiconductor layer is disposed on the third insulating layer 124, but does not overlap with the lower semiconductor layer. The upper semiconductor layer may include one of amorphous silicon (a-Si), polycrystalline silicon (p-Si), an oxide semiconductor, and an organic semiconductor. The oxide semiconductor includes at least one of Zn, In, Ga, Sn, or a mixture thereof. The oxide semiconductor is a metal oxide semiconductor, and is made of: a metal oxide such as a metal oxide formed of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or an oxide thereof. For example, the oxide semiconductor material may be one of zinc oxide (ZnO), Zinc Tin Oxide (ZTO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiO), Indium Gallium Zinc Oxide (IGZO), and Indium Zinc Tin Oxide (IZTO).

According to an embodiment, the upper semiconductor layer includes a source region S2 disposed at one side, a drain region D2 disposed at an opposite side, and a channel region a2 disposed between the source region S2 and the drain region D2. Portions of the upper semiconductor layer connected to the source electrode SE2 and the drain electrode DE2 of each of the transistors T3 and T4, i.e., the source region S2 and the drain region D2, are doped with impurity ions, specifically, n-type impurity ions in the case of NMOS transistors. The n-type impurity ions may be alkali metals, alkaline earth metals, or n-type organic dopants. Examples of n-type organic dopants include: cr2hpp4(hpp: anion of 1,3,4,6,7, 8-hexahydro-2H-pyrimido [1,2-a ] pyrimidine), Fe2hpp4, Mn2hpp4, Co2hpp4, Mo2hpp4, W2hpp4, Ni2hpp4, Cu2hpp4, Zn2hpp4, W (hpp)4, and the like. In addition, examples include other organic dopant compounds, such as 4,4',5,5' -tetracyclohexyl-1, 1',2,2',3,3 '-hexamethyl-2, 2',3, 3-tetrahydro-1H, 1'H2,2' -biimidazole; 2,2' -diisopropyl-1, 1',3,3' -tetramethyl-2, 2',3,3',4,4',5,5',6,6',7,7' -dodecahydro-1H, 1' H-2,2' -bibenzo [ d ] imidazole; 2,2' -diisopropyl-4, 4',5,5' -tetrakis (4-methoxyphenyl) -1,1',3,3' -tetramethyl-2, 2',3,3' -tetrahydro-1H, 1' H-2,2' -biimidazole; 2,2' -diisopropyl-4, 5-bis (2-methoxyphenyl) -4',5' -bis (4-methoxyphenyl) -1,1',3,3' -tetramethyl-2, 2',3,3' -tetrahydro-1H, 1' H-2,2' -biimidazole); or 2,2' -diisopropyl-4, 5-bis (2-methoxyphenyl) -4',5' -bis (3-methoxyphenyl) -1,1',3,3' -tetramethyl-2, 2',3,3' -tetrahydro-1H, 1' H-2,2' -biimidazole.

According to an embodiment, when the upper semiconductor layer includes an oxide semiconductor, a light blocking layer blocking light from the upper semiconductor layer is formed on and under the upper semiconductor layer.

According to an embodiment, the fourth insulating layer 125 is disposed on the upper semiconductor layer. The fourth insulating layer 125 covers the entire upper semiconductor layer. For example, the fourth insulating layer 125 is disposed on the upper semiconductor layer and formed on the entire surface of the substrate 110.

According to an embodiment, the fourth insulating layer 125 is a gate insulating layer having a gate insulating function. The fourth insulating layer 125 may include the same material as the first insulating layer 122, or may include one or more other materials selected from the materials listed above for the first insulating layer 122. The second insulating layer 123 may have a single layer or a plurality of layers of different materials stacked on each other.

According to an embodiment, the third conductive layer G3 is disposed on the fourth insulating layer 125. The third conductive layer G3 overlaps with at least a part of the upper semiconductor layer. The third conductive layer G3 may include the same material as the first conductive layer G1 or may include at least one other material selected from the materials listed above for the first conductive layer G1. The third conductive layer G3 may have a single layer or multiple layers of different materials stacked on each other.

According to an embodiment, the third conductive layer G3 includes a scan line for transmitting a first scan signal (GW in fig. 3), a gate electrode of the third transistor T3, and a gate electrode of the fourth transistor T7.

According to an embodiment, the fifth insulating layer 126 covers the fourth conductive layer. The fifth insulating layer 126 is disposed on the first conductive layer G1 and generally on the entire surface of the substrate 110. The fifth insulating layer 126 is an interlayer dielectric layer. The fifth insulating layer 126 comprises silicon oxide (SiO)_x) And silicon nitride (SiN)_x) A plurality of layers of (a). However, it will be understood that embodiments of the present disclosure are not so limited. The fifth insulating layer 126 may have a structure including silicon oxide (SiO)_x) Silicon nitride (SiN)_x) A single layer of silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, or a plurality of layers of different materials stacked on each other.

According to an embodiment, the fifth insulating layer 126 serves to supply hydrogen ions (H +) so that n-type impurity ions can be doped into the upper semiconductor layer through heat treatment. This will be described in detail below with reference to fig. 5 to 7. In addition, the fifth insulating layer 126 provides a flat surface.

According to an embodiment, the plurality of source electrodes SE1 and SE2 and the plurality of drain electrodes DE1 and DE2 are disposed on the fifth insulating layer 126. Each of the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 is formed of a conductive metal. For example, the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 may include aluminum (Al), copper (Cu), titanium (Ti), or molybdenum (Mo).

According to an embodiment, the first source electrode SE1 is electrically connected to the source region S1 of the lower semiconductor layer, and the first drain electrode DE1 is electrically connected to the drain region D1 of the lower semiconductor layer. More specifically, the first source electrode SE1 and the first drain electrode DE1 are electrically connected to the source region S1 and the drain region D1 of the lower semiconductor layer, respectively, through contact holes penetrating the first to fifth insulating layers 122 to 126, respectively.

According to an embodiment, the second source electrode SE2 is electrically connected to the source region S2 of the upper semiconductor layer, and the second drain electrode DE2 is electrically connected to the drain region D2 of the upper semiconductor layer. More specifically, the second source electrode SE2 and the second drain electrode DE2 are electrically connected to the source region S2 and the drain region D2 of the upper semiconductor layer, respectively, through contact holes penetrating the fourth insulating layer 125 and the fifth insulating layer 126.

According to an embodiment, a first through layer (first via layer)127 is disposed on the fifth insulating layer 126 and formed on the entire surface of the substrate 110 to cover the plurality of source electrodes SE1 and SE2 and the plurality of drain electrodes DE1 and DE 2. The first through layer 127 is made of an insulating material. For example, the first through layer 127 may include a single layer or a plurality of layers of an inorganic material, an organic material, or an organic/inorganic composite material, and may be formed by various deposition methods. In some exemplary embodiments, the first through layer 127 is made of one or more of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

According to an embodiment, the second through layer 128 is disposed on the first through layer 127. The second through layer 128 is formed on the entire surface of the substrate 110. The second through layer 128 may comprise the same material as the first through layer 127, or may comprise one or more of the other materials listed above for the first through layer 127.

According to an embodiment, a Contact Metal (CM) is disposed between the first through layer 127 and the second through layer 128. The pixel electrode 140 is electrically connected to the contact metal CM through the contact hole in the second through layer 128. The contact metal CM is electrically connected to the first drain electrode DE1 through the contact hole in the first through layer 127. The contact metal CM electrically connects the pixel electrode 140 and the first drain electrode DE 1. Note that the first through layer 127 and the contact metal CM may be removed. Then, the pixel electrode 140 may be directly connected to the first drain electrode DE1 through the contact hole in the second through layer 128.

According to an embodiment, the pixel electrode 140 is disposed on the second through layer 128. The pixel electrode 140 is an anode electrode of the organic light emitting diode.

According to an embodiment, the pixel electrode 140 includes a material having a high work function. The pixel electrode 140 includes Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) And the like. The conductive materials listed above have relatively high work functions and are transparent. When the organic light emitting display device is a top emission organic light emitting display device, the pixel electrode 140 may include a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof, in addition to the above-listed conductive materials. Accordingly, the pixel electrode 140 may have a single-layer structure of the conductive material and the reflective material listed above, or may have a multi-layer structure in which individual layers are stacked on each other.

According to an embodiment, the pixel defining layer 130 is disposed on the pixel electrode 140. The pixel defining layer 130 includes an opening through which at least a portion of the pixel electrode 140 is exposed. The pixel defining layer 130 may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 130 includes a material such as photoresist, polyimide resin, acrylic resin, silicon compound, or polyacrylic resin.

According to an embodiment, an organic emission layer is disposed on a portion of the pixel electrode 140 exposed by the pixel defining layer 130, and a common electrode is disposed on the organic emission layer. The common electrode is a cathode electrode of the organic light emitting diode.

According to an embodiment, the common electrode includes a material having a low work function. The common electrode includes one of Li, Ca, LiF/Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof, for example, a mixture of Ag and Mg. The common electrode further includes an auxiliary electrode. The auxiliary electrode includes a layer formed by depositing a low work function material and a transparent metal oxide such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), or Indium Tin Zinc Oxide (ITZO) on the layer.

According to an embodiment, when the organic light emitting diode display device 60 is a top emission organic light emitting diode display device, a thin conductive layer having a low work function is formed as a common electrode, and a conductive layer such as an Indium Tin Oxide (ITO) layer, an Indium Zinc Oxide (IZO) layer, a zinc oxide (ZnO) layer, or an indium oxide (In) layer is formed₂O₃) A transparent conductive layer of layers is formed on the thin conductive layer.

According to an embodiment, the pixel electrode 140, the organic emission layer, and the common electrode form an organic light emitting diode.

Hereinafter, a method of manufacturing the source region a2 and the drain region D2 of the upper semiconductor layer will be described.

Fig. 5 to 7 are cross-sectional views illustrating a process of forming source and drain regions of an upper semiconductor layer.

Referring now to fig. 5 to 7, according to an embodiment, an oxide semiconductor a2_ a, aA fourth insulating layer 125, a third conductive layer G3, and a fifth insulating layer 126 are sequentially stacked on the third insulating layer 124. The oxide semiconductor a2_ a is a metal oxide semiconductor such as Indium Gallium Zinc Oxide (IGZO) as described above. The fifth insulating layer 126 comprises silicon oxide (SiO) as described above_x) And silicon nitride (SiN)_x) A plurality of layers are produced. For example, the fifth insulating layer 126 has a plurality of layers in which a silicon oxide layer 126b is stacked on a silicon nitride layer 126 a. The stack structure of the fifth insulating layer 126 is not limited thereto. In another exemplary embodiment, the fifth insulating layer 126 includes a plurality of layers formed by stacking a silicon nitride layer on a silicon oxide layer, or may be a single layer including silicon oxide or silicon nitride.

Next, according to an embodiment, the first end and the opposite second end of the oxide semiconductor a2_ a are subjected to the reduction process by the heat treatment without a separate etching process such as a process of etching the fourth insulating layer 125. When heat is applied from above the substrate, hydrogen ions (H +) present in the fifth insulating layer 126 diffuse into the oxide semiconductor a2 — a. In an exemplary embodiment, as shown in fig. 6, during the heat treatment, hydrogen ions (H +) are mainly generated in the silicon nitride layer 126b of the fifth insulating layer 126 and diffused into the oxide semiconductor a2_ a.

According to the embodiment, by performing the heat treatment, hydrogen ions (H +) are diffused into the first and second ends of the oxide semiconductor a2_ a so that reduction starts, so that the conductive source region S2 and the conductive drain region D2 are formed. Since the oxide semiconductor includes a region overlapping with the third conductive layer G3, reduction becomes weaker toward the center of the oxide semiconductor a2 — a, so that a low conductive region is formed. After reduction by heat treatment, a source region S2 and a drain region D2 are formed at the first and second ends of the oxide semiconductor a2_ a, respectively, and as shown in fig. 7, a channel region a2, which is a low conductive region, is formed between the source region S2 and the drain region D2.

According to an embodiment, the heat treatment is performed at about 90 ℃ to about 110 ℃. However, the temperature is not limited thereto, and the heat treatment may be performed at a temperature higher than 110 ℃. It will be understood that hydrogen ions (H +) do not have to be generated in the fifth insulating layer 126. Hydrogen ions (H +) present in the third insulating layer 124 and the fourth insulating layer 125 may diffuse into the oxide semiconductor a2 — a.

According to an embodiment, the fourth insulating layer 125 has a minimum thickness such that hydrogen ions (H +) generated in the fifth insulating layer 126 do not substantially reach the lower semiconductor layer. In an exemplary embodiment, if the heat treatment temperature is about 95 ℃, the thickness of the fourth insulation layer 125 is equal to or greater thanThe hydrogen concentration in the fourth insulating layer 125 is less than or equal to about 9 x 10²⁰Atom/cm³。

According to an embodiment, the third insulating layer 124 has a thickness of greater than or equal to aboutIs measured. The hydrogen concentration in the third insulating layer 124 is less than or equal to about 9 x 10²⁰Atom/cm³. The thickness of the fifth insulating layer 126 is aboutIn an exemplary embodiment, the fifth insulating layer 126 includes silicon oxide (SiO)_x) Layer and layer arranged on silicon oxide (SiO)_x) Silicon nitride (SiN) on a layer_x) Layer of said silicon oxide (SiO)_x) The layer has a thickness of greater than or equal to aboutOf silicon nitride (SiN)_x) The layer has a thickness of about 1500 to aboutIs measured.

According to the embodiment, the surface resistance of the upper semiconductor layer doped with n-type impurity ions by the heat treatment is less than 1000 Ω/□. Specifically, the surface resistance of the source region S2 and the drain region D2 is less than or equal to about 1000 Ω/□.

In this way, according to the embodiment, by doping the oxide semiconductor with n-type impurity ions only through the heat treatment without an additional etching process, it is possible to prevent side effects such as an increase in sharp corners (taper), a short circuit in the third conductive layer G3 and the upper semiconductor, and the like, which may be generated during the etching process. Further, according to the doping scheme according to the embodiment described above, it is possible to reduce the wiring resistance of the upper semiconductor layer by increasing the temperature during the heat treatment. Since the heat treatment temperature can be increased, the dehydrogenation effect in the lower semiconductor layer can be improved, so that the driving ranges of the transistors T1, T2, T5, T6, and T7 including the lower semiconductor layer can be increased. Even if the heat treatment temperature is increased, it is possible to prevent hydrogen ions (H +) from diffusing into the transistors T1, T2, T5, T6, and T7 by adjusting the thickness of the fourth insulating layer 125. In an exemplary embodiment, the driving range of the transistors T1, T2, T5, T6, and T7 is greater than or equal to about 2.9V.

Next, an organic light emitting display device according to an exemplary embodiment of the present disclosure will be described. The elements already described above with reference to fig. 1 to 7 will not be described again. Furthermore, like reference numerals may refer to features similar to those described above with reference to fig. 1-7.

Fig. 8 is a cross-sectional view of an organic light emitting display device 61 according to an exemplary embodiment of the present disclosure.

According to an embodiment, the organic light emitting display device 61 shown in fig. 8 is different from the organic light emitting display device 60 shown in fig. 1 to 7 in that a fourth insulating layer 125_1 is formed only in a portion of the substrate 110 to cover the upper semiconductor layer, not on the entire surface of the substrate 110.

According to an embodiment, the fourth insulating layer 125_1 includes the same material as the first insulating layer 122 illustrated in fig. 4, or may include one or more other materials selected from the materials listed above for the first insulating layer 122.

According to an embodiment, the fourth insulating layer 125_1 covers the upper and side portions of the upper semiconductor layer. Since the fourth insulating layer 125_1 covers the upper semiconductor layer, the fourth insulating layer 125_1 performs the same function of supplying hydrogen ions (H +) as in the exemplary embodiment shown in fig. 1 to 7, so that the upper semiconductor layer may be doped with n-type impurity ions through heat treatment.

Fig. 9 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment of the present disclosure.

According to an embodiment, the organic light emitting display device 62 shown in fig. 9 is different from the organic light emitting display device 60 shown in fig. 1 to 7 in that a fourth insulating layer 125_2 is formed in a portion of the substrate 110 to cover the upper semiconductor layer, not on the entire surface of the substrate 110. Further, the organic light emitting display device 62 shown in fig. 9 is different from the organic light emitting display device 61 shown in fig. 8 in that the fourth insulating layer 125_2 includes a portion overlapping and covering the lower semiconductor layer.

According to an embodiment, the fourth insulating layer 125_2 may include the same material as the first insulating layer 122 illustrated in fig. 4, or may include one or more other materials selected from the materials listed above for the first insulating layer 122.

According to an embodiment, the fourth insulating layer 125_2 covers the upper and side portions of the upper semiconductor layer. In addition, the fourth insulating layer 125_2 extends to a region overlapping with the lower semiconductor layer.

According to the embodiment, since the fourth insulating layer 125_2 covers the upper semiconductor layer, the fourth insulating layer 125_2 performs the same function of supplying hydrogen ions (H +) as in the exemplary embodiment shown in fig. 1 to 7, so that the upper semiconductor layer may be doped with n-type impurity ions through heat treatment. Further, since the fourth insulating layer 125_2 extends to a region overlapping with the lower semiconductor layer, it is possible to prevent hydrogen ions (H +) from diffusing into the lower semiconductor layer, thereby increasing the driving range of the transistors T1, T2, T5, T6, and T7 including the lower semiconductor layer.

The effects of the embodiments of the present disclosure are not limited by the foregoing, and other various effects are contemplated herein.

Although the exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the embodiments of the disclosure as disclosed in the accompanying claims.