阅读说明：本技术 有机发光显示面板及其制备方法 (Organic light emitting display panel and method of manufacturing the same ) 是由 林振国 周星宇 徐源竣 吕伯彦 于 2019-08-22 设计创作，主要内容包括：本发明提供一种有机发光显示面板及其制备方法,所述有机发光显示面板包括：基板、第一电极、遮光层、缓冲层以及第二电极。本发明的技术效果在于,第一电极采用透明的IZO和IGZO等组成,可以将透明第一电极放置于发光区的底部,降低像素区的尺寸,提高有机发光显示面板的分辨率。(The invention provides an organic light emitting display panel and a preparation method thereof, wherein the organic light emitting display panel comprises: the display device comprises a substrate, a first electrode, a shading layer, a buffer layer and a second electrode. The invention has the technical effects that the first electrode is composed of transparent IZO, IGZO and the like, and can be placed at the bottom of the luminous zone, so that the size of the pixel zone is reduced, and the resolution of the organic light-emitting display panel is improved.)

1. An organic light emitting display panel, comprising:

a substrate including a thin film transistor and a light emitting region;

a first electrode disposed on the substrate, the first electrode being a transparent electrode;

a light shielding layer disposed on the first electrode;

a buffer layer disposed on the light-shielding layer; and

the second electrode is arranged on the buffer layer and is a transparent electrode;

and the first electrode and the second electrode form a transparent capacitor in the light emitting area.

2. The organic light emitting display panel of claim 1,

the first electrode is made of at least one of transparent indium-doped zinc oxide, aluminum-doped zinc oxide and aluminum-doped indium zinc oxide.

3. The organic light emitting display panel of claim 1,

the second electrode is made of at least one of indium gallium zinc oxide, indium zinc titanium oxide and indium gallium zinc titanium oxide.

4. The organic light emitting display panel of claim 1,

the first electrode extends from below the second electrode in the light emitting region to below the light shielding layer.

5. The organic light emitting display panel of claim 1,

the thin film transistor includes:

an active layer disposed on the buffer layer;

a gate insulating layer disposed on the active layer;

a gate electrode disposed on the gate insulating layer;

a dielectric layer disposed over the gate;

a first via hole penetrating the dielectric layer; and

and the source drain layer is arranged on the dielectric layer and is electrically connected to the active layer through the first through hole.

6. The organic light emitting display panel according to claim 4, further comprising:

a passivation layer disposed on the dielectric layer;

a planarization layer disposed on the passivation layer;

the second through hole is recessed in the flat layer and a part of the passivation layer;

the anode layer is arranged on the inner side wall of the second through hole and extends to the light emitting area of the flat layer;

a pixel defining layer disposed on the planarization layer and the anode layer; and

and a third via hole penetrating the pixel defining layer.

7. The organic light emitting display panel of claim 6, further comprising

The color resistance layer is arranged on the passivation layer of the light emitting area and is opposite to the third through hole;

wherein the planarization layer is disposed on the passivation layer and the color resist layer.

8. The organic light emitting display panel of claim 6,

the second electrode and the third through hole are arranged oppositely.

9. A preparation method of an organic light-emitting display panel is characterized by comprising the following steps:

providing a substrate;

preparing a first electrode and a shading layer on the upper surface of the substrate;

preparing a buffer layer on the upper surfaces of the substrate, the first electrode and the light shielding layer; and

and preparing a thin film transistor and a second electrode on the upper surface of the buffer layer, wherein the thin film transistor is arranged above the second electrode, so that the first electrode and the second electrode form a transparent capacitor in the light emitting area.

10. The method of manufacturing an organic light emitting display panel according to claim 9, wherein the first electrode is manufactured by a process comprising:

coating a first electrode material on the upper surface of the substrate;

coating a light shielding material on the upper surface of the first electrode material;

coating a layer of photoresist on the upper surface of the shading material; and

etching a first electrode and a shading layer;

the preparation step of the second electrode comprises the following steps:

preparing a semiconductor layer on the upper surface of the buffer layer, and etching a semiconductor pattern;

preparing a gate insulating layer on the upper surface of the semiconductor pattern;

preparing a grid layer on the upper surface of the grid insulating layer;

etching a grid electrode layer pattern, and etching a grid electrode insulating layer pattern to enable the grid electrode insulating layer pattern and the grid electrode layer pattern to be arranged oppositely;

carrying out plasma treatment on the upper surface of the whole substrate, so that a conductor layer is formed on the semiconductor pattern which is not covered by the grid insulation layer, and a thin film transistor channel is formed on the semiconductor pattern which is covered by the grid insulation layer; and

and conducting the conductor layer above the light emitting area to form a second electrode.

Technical Field

The invention relates to the field of display, in particular to an organic light-emitting display panel and a preparation method thereof.

Background

With the continuous development of the display panel industry, large-size high-resolution display panels become the mainstream, however, one of the main problems of the large-size high-resolution display panels is that the size of the pixel region is too large, resulting in insufficient resolution of the display panel.

As shown in fig. 1, the conventional display panel is divided into a tft region 110, a light emitting region 120 and a capacitor region 130. The first capacitor layer 140 is disposed between the buffer layer and the insulating layer of the capacitor region 130, the second capacitor layer 150 is disposed between the insulating layer and the passivation layer of the capacitor region 130, and the second capacitor layer 150 is disposed opposite to the first capacitor layer 140.

The lengths of the light emitting region 120 and the capacitor region 130 are large, and to reduce the size of the pixel region, the sizes of the thin film transistor region, the capacitor region and the light emitting region need to be reduced, but the reduction range is limited because a certain size is required to ensure the capacitance and the thin film transistor.

Disclosure of Invention

The invention aims to solve the technical problems of overlarge pixel area size, small light emitting area size and the like in the prior art.

To achieve the above object, the present invention provides an organic light emitting display panel including: a substrate including a thin film transistor and a light emitting region; a first electrode disposed on the substrate, the first electrode being a transparent electrode; a light shielding layer disposed on the first electrode; a buffer layer disposed on the light-shielding layer; the second electrode is arranged on the buffer layer and is a transparent electrode; and the first electrode and the second electrode form a transparent capacitor in the light emitting area.

Furthermore, the material of the first electrode comprises at least one of transparent indium-doped zinc oxide, aluminum-doped zinc oxide and aluminum-doped indium zinc oxide.

Furthermore, the material of the second electrode comprises at least one of indium gallium zinc oxide, indium zinc titanium oxide and indium gallium zinc titanium oxide.

Further, the first electrode extends from below the second electrode in the light emitting region to below the light shielding layer.

Further, the thin film transistor includes: an active layer disposed on the buffer layer; a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; a dielectric layer disposed over the gate; a first via hole penetrating the dielectric layer; and a source drain layer disposed on the dielectric layer and electrically connected to the active layer through the first via hole.

Further, the organic light emitting display panel further includes: a passivation layer disposed on the dielectric layer; a planarization layer disposed on the passivation layer; the second through hole is recessed in the flat layer and a part of the passivation layer; the anode layer is arranged on the inner side wall of the second through hole and extends to the light emitting area of the flat layer; a pixel defining layer disposed on the planarization layer and the anode layer; and a third via hole penetrating the pixel defining layer.

Furthermore, the organic light-emitting display panel further comprises a color resistance layer which is arranged on the passivation layer of the light-emitting area and is opposite to the third through hole; wherein the planarization layer is disposed on the passivation layer and the color resist layer.

Further, the second electrode is arranged opposite to the third through hole.

In order to achieve the above object, the present invention also provides a method for manufacturing an organic light emitting display panel, including: providing a substrate; preparing a first electrode and a shading layer on the upper surface of the substrate; preparing a buffer layer on the upper surfaces of the substrate, the first electrode and the light shielding layer; and preparing a thin film transistor and a second electrode on the upper surface of the buffer layer, wherein the thin film transistor is arranged above the second electrode, so that the first electrode and the second electrode form a transparent capacitor in the light emitting area.

Further, the preparing step of the first electrode comprises: coating a first electrode material on the upper surface of the substrate; coating a light shielding material on the upper surface of the first electrode material; coating a layer of photoresist on the upper surface of the shading material; etching the first electrode and the shading layer; the preparation step of the second electrode comprises the following steps: preparing a semiconductor layer on the upper surface of the buffer layer, and etching a semiconductor pattern; preparing a gate insulating layer on the upper surface of the semiconductor pattern; preparing a grid layer on the upper surface of the grid insulating layer; etching a grid electrode layer pattern, and etching a grid electrode insulating layer pattern to enable the grid electrode insulating layer pattern and the grid electrode layer pattern to be arranged oppositely; carrying out plasma treatment on the upper surface of the whole substrate, so that a conductor layer is formed on the semiconductor pattern which is not covered by the grid insulation layer, and a thin film transistor channel is formed on the semiconductor pattern which is covered by the grid insulation layer; and conducting the conductor layer above the light emitting region to form a second electrode.

The invention has the technical effects that the original first capacitance layer is removed in the pixel area, the bottom of the display panel is provided with a new first electrode which is made of at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO) and aluminum-doped indium zinc oxide (IAZO), and the oxide has good volatility, so that material residue in etching can be avoided, and the etching effect is improved. The invention arranges the capacitor in the original capacitor area in the original luminous area, removes the original capacitor area, reduces the size of the pixel area and further improves the resolution of the display panel.

Drawings

FIG. 1 is a schematic diagram of a display panel in the prior art;

fig. 2 is a schematic structural diagram of an organic light emitting display panel according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of another organic light emitting display panel according to an embodiment of the invention;

fig. 4 is a flowchart illustrating a method of fabricating an organic light emitting display panel according to an embodiment of the present invention;

FIG. 5 is a flow chart of a first electrode preparation step according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an organic light emitting display panel before the etching step according to the embodiment of the invention;

fig. 7 is a schematic structural diagram of the organic light emitting display panel after the light shielding layer is etched for the first time according to the embodiment of the invention;

fig. 8 is a schematic structural diagram of the organic light emitting display panel after the first electrode is etched according to the embodiment of the invention;

fig. 9 is a schematic structural diagram of an organic light emitting display panel after photoresist treatment according to an embodiment of the invention;

fig. 10 is a schematic structural diagram of the organic light-emitting display panel after the light-shielding layer is etched for the second time according to the embodiment of the invention;

FIG. 11 is a flow chart illustrating a second electrode preparation step according to an embodiment of the present invention.

Some of the components are identified as follows:

110. a thin film transistor region; 120. a light emitting region; 130. a capacitive region; 140. a first capacitor layer; 150. a second capacitive layer;

1. a substrate; 2. a first electrode; 3. a light-shielding layer; 4. a buffer layer; 5. a second electrode; 6. a source drain layer; 7. a dielectric layer; 8. a passivation layer; 9. a color resist layer; 10. a planarization layer; 11. an anode layer; 12. a pixel defining layer;

100. a thin film transistor; 200. a light emitting region;

101. a fully exposed region; 102 incompletely exposed regions; 103. the areas are not exposed at all.

Detailed Description

The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to make and use the present invention in a complete manner, and is provided for illustration of the technical disclosure of the present invention so that the technical disclosure of the present invention will be more clearly understood and appreciated by those skilled in the art how to implement the present invention. The present invention may, however, be embodied in many different forms of embodiment, and the scope of the present invention should not be construed as limited to the embodiment set forth herein, but rather construed as being limited only by the following description of the embodiment.

The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only directions in the drawings, and are used for explaining and explaining the present invention, but not for limiting the scope of the present invention.

In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.

When certain components are described as being "on" another component, the component can be directly on the other component; there may also be an intermediate component disposed on the intermediate component and the intermediate component disposed on another component. When an element is referred to as being "mounted to" or "connected to" another element, they are directly "mounted to" or "connected to" the other element or "mounted to" or "connected to" the other element through an intermediate element.

As shown in fig. 2, the present embodiment provides an organic light emitting display panel including: the pixel structure comprises a substrate 1, a first electrode 2, a shading layer 3, a buffer layer 4, a second electrode 5, a source drain layer 6, a dielectric layer 7, a passivation layer 8, a color resistance layer 9, a flat layer 10, an anode layer 11 and a pixel definition layer 12.

The substrate 1 includes a thin film transistor 100 and a light emitting region 200, and in the prior art, the display panel includes a thin film transistor region 11, a light emitting region 12 and a capacitor region 13, in this embodiment, a capacitor in the original capacitor region is disposed in the original light emitting region, and the original capacitor region is removed, so as to reduce the size of the pixel region, and further improve the resolution of the display panel.

The first electrode 2 is disposed on the upper surface of the substrate 1, the material of the first electrode 2 includes at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO), and aluminum-doped indium zinc oxide (IAZO), and the thickness of the first electrode 2 is 300-.

The conductivity of the doped film is greatly improved, the resistivity is reduced, and the stability of the transparent indium-doped zinc oxide (IZO), the aluminum-doped zinc oxide (AZO) and the aluminum-doped zinc oxide (IAZO) in hydrogen plasma is superior to that of Indium Tin Oxide (ITO), and the film has photoelectric characteristics similar to that of the ITO. The aluminum-doped zinc oxide (AZO) is convenient to prepare, rich in element resources compared with indium, and non-toxic, and gradually becomes the best substitute for the ITO film. The material in this embodiment is soft, and the storage time after the sculpture is short, so material residue during the sculpture can be avoided, improves the sculpture effect.

The light shielding layer 3 is disposed on the upper surface of the thin film transistor 100 of the first electrode 2, the material of the light shielding layer 3 includes at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or an alloy, the thickness of the light shielding layer 3 is 500-10000A, and the light shielding layer 3 is used for shielding light to ensure that the property of the first electrode below the light shielding layer is not changed.

The buffer layer 4 is disposed on the upper surfaces of the substrate 1, the first electrode 2 and the light shielding layer 3, the material of the buffer layer 4 includes silicon oxide (SiO) or silicon nitride (SiN) or a mixture of the two, the thickness of the buffer layer 4 is 500-.

The second electrode 5 is disposed on the upper surface of the buffer layer 4, and has a second electrode located on the thin film transistor 100, a second electrode located in the light emitting region 200, and the first electrode 2 and the second electrode 5 form a transparent capacitor in the light emitting region 12. The material of the second electrode 5 is the same as the material and the same position of the capacitor layer in the prior art (see fig. 1), and the material of the second electrode 5 includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Titanium Oxide (IZTO), and Indium Gallium Zinc Titanium Oxide (IGZTO).

The source-drain layer 6 is disposed on the upper surface of the second electrode of the thin film transistor 100, wherein the gate insulating layer is disposed on the upper surface of the second electrode 5, the gate insulating layer is made of silicon oxide (SiOx) or nitrogen oxide (SiNx) or a multi-layer structure film, and the thickness of the gate insulating layer is 1000-3000A. The grid electrode layer is arranged on the upper surface of the grid electrode insulating layer, the material of the grid electrode layer comprises at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or alloy, and the thickness of the grid electrode layer is 2000-10000A.

The dielectric layer 7 is disposed on the upper surfaces of the buffer layer 4, the source/drain layer 6, and the second electrode 5. The dielectric layer 7 is made of SiOx, SiNx or a multilayer film, and the thickness of the dielectric layer 7 is 2000-10000A. The dielectric layer 7 is provided with a first through hole, which penetrates through the dielectric layer 7 and is disposed opposite to the active layer 5. The first through hole provides a channel for the subsequent source and drain.

The source of the source drain electrode layer 6 is disposed in a first through hole, one end of the source drain electrode layer is electrically connected to the second electrode 5, the other end of the source drain electrode layer is connected to the light shielding layer, the drain of the source drain electrode layer 6 is disposed in another first through hole and is electrically connected to the second electrode 5, the source and the drain are made of at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or an alloy, and the thickness is 2000-8000A.

The passivation layer 8 is disposed on the upper surfaces of the source drain layer 6 and the dielectric layer 7, and the material of the passivation layer 8 includes silicon oxide (SiOx) or nitrogen oxide (SiNx) or a multi-layer structure film, and the thickness is 1000A-.

The color resistance layer 9 is disposed on the upper surface of the passivation layer of the light emitting region 200, and the color resistance layer 9 is an R/G/B color resistance. The color resist layer 9 can be removed as required (see fig. 3), and the display effect of the display panel is not affected.

The planarization layer 10 is disposed on the upper surfaces of the passivation layer 8 and the color resist layer 9 or on the upper surface of the passivation layer 8. The flat layer 10 is provided with a second via hole, and the second via hole penetrates through the flat layer 10 and a part of the passivation layer to expose the source electrode of the source drain layer 6.

The anode layer 11 is disposed on the inner sidewall of the second via hole and extends to the upper surface of the light emitting region of the planarization layer 10. The anode layer 11 is made of Indium Tin Oxide (ITO).

The pixel defining layer 12 is disposed on the upper surface of the planarization layer 10 and the upper surface of the anode layer 11 for defining the size of the light emitting region. The pixel defining layer 12 is provided with a third through hole, and the third through hole is disposed opposite to a second electrode 5 for preventing the light emitting material.

The organic light emitting display panel described in this embodiment has the technical effects that, in the pixel region, the original first capacitor layer is removed, and the bottom of the display panel is provided with a new first electrode made of at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO) and aluminum-doped indium zinc oxide (IAZO), and the oxide has good volatility, so that material residue during etching can be avoided, and the etching effect is improved. The invention arranges the capacitor in the original capacitor area in the original luminous area, removes the original capacitor area, reduces the size of the pixel area and further improves the resolution of the display panel.

As shown in fig. 4, the present embodiment further provides a method for manufacturing an organic light emitting display panel, including the following steps S1 to S6.

S1A step of arranging a substrate, wherein the substrate comprises a thin film transistor and a light emitting area. The capacitor in the original capacitor area is arranged in the original luminous area, the original capacitor area is removed, the size of the pixel area is reduced, and the resolution of the display panel is improved

S2 a first electrode preparing step of preparing a first electrode and a light shielding layer on the upper surface of the substrate. The first capacitor layer in the prior art is arranged at the bottom of the display panel to form a new first electrode, the material of the first electrode is changed from original indium tin oxide into at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO) and aluminum-doped indium zinc oxide (IAZO), the storage time after etching is short, and therefore material residue during etching can be avoided, and the etching effect is improved.

S3 buffer layer preparing step, preparing a buffer layer on the upper surface of the substrate, the first electrode and the light shielding layer, wherein the buffer layer is made of silicon oxide (SiO) or silicon nitride (SiN) or a mixed material of the two materials, and the thickness is 500-6000A.

S4 step of preparing a second electrode, in which a thin film transistor and a second electrode are prepared on the upper surface of the buffer layer, the thin film transistor is disposed above a second electrode, and the material and position of the second electrode are the same as those of the prior art, so that the first electrode and the second electrode form a transparent capacitor in the light emitting region.

S5 preparing a dielectric layer, wherein the dielectric layer is prepared on the second electrode and the thin film transistor, the material of the dielectric layer is silicon oxide (SiOx) or nitrogen oxide (SiNx) or a multilayer structure film, and the thickness of the dielectric layer is 2000-10000A. Depositing a metal layer on the upper surface of the dielectric layer, and etching a source electrode pattern and a drain electrode pattern to ensure that one end of the source electrode penetrates through the dielectric layer to be connected to the second electrode, and the other end of the source electrode penetrates through the dielectric layer to be connected to the light shielding layer; a drain electrode is connected to the second electrode through the dielectric layer.

S6 preparing a passivation layer on the upper surface of the dielectric layer, wherein the passivation layer is made of silicon oxide (SiOx), nitrogen oxide (SiNx) or a multilayer film with a thickness of 1000-5000A.

S7 color resistance layer preparation, namely preparing a color resistance layer on the upper surface of the luminous area of the passivation layer, wherein the color resistance layer is R/G/B color resistance and is used for color display. In other embodiments, the color resist layer preparation step can be omitted, and the display effect of the display panel is not affected.

S8, preparing a flat layer on the upper surface of the passivation layer and the color resistance layer.

And S9, perforating the flat layer downwards to form a through hole through the flat layer and part of the passivation layer, wherein the through hole penetrates through the flat layer and part of the passivation layer to expose the source electrode of the thin film transistor, so that the subsequent thin film layer can be conveniently connected with the thin film transistor.

S10 preparing an anode layer on the inner side wall of the through hole and extending to the light emitting region of the flat layer, wherein the anode layer is made of Indium Tin Oxide (ITO).

And S11 preparing a pixel definition layer on the flat layer and the upper surface of the anode layer of the thin film transistor.

The thin film layer is the same as the transparent capacitor layer in the prior art, and therefore, the description is only briefly made here.

In the organic light emitting display panel prepared in this embodiment, the original first capacitor layer is removed in the pixel region, and the new first electrode is disposed at the bottom of the display panel and is made of at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO), and aluminum-doped indium zinc oxide (IAZO), where the oxide has good volatility, so that material residue during etching can be avoided, and the etching effect can be improved. The invention arranges the capacitor in the original capacitor area in the original luminous area, removes the original capacitor area, reduces the size of the pixel area and further improves the resolution of the display panel.

As shown in fig. 5, the above-mentioned S2 first electrode preparing step includes steps S21 to S24.

S21 coating a first electrode material, namely coating the first electrode material on the upper surface of the substrate, wherein the first electrode material comprises at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO) and aluminum-doped indium zinc oxide (IAZO), the thickness of the first electrode material is 300-2000A, and the first electrode material is soft and has short existence time after etching and is not easy to remain.

S22 light shielding material coating step, coating light shielding material on the upper surface of the first electrode material, wherein the light shielding material comprises at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or alloy, and the thickness is 500-10000A.

S23 step of coating photoresist, in which a layer of photoresist is coated on the upper surface of the light-shielding material (see fig. 6), and a yellow light process (Half-tone process) is adopted, and the photoresist divides the display panel into a fully exposed area 101, an incompletely exposed area 102, and a completely unexposed area 103, thereby facilitating the subsequent etching exposure.

And S24, etching to obtain the first electrode and the light shielding layer. As shown in fig. 7 to 10, the etching step specifically includes: the light-shielding layer of the fully exposed region 101 is first etched (see fig. 7), and the first electrode of the fully exposed region 101 is wet etched using oxalic acid (see fig. 8). The photoresist is subjected to Ash processing so that the photoresist of the incompletely exposed regions 102 is etched away (see fig. 9). And finally, etching the shading layer for the second time, etching away the shading layer in the incomplete exposure area 102, and only leaving the shading layer in the complete unexposed area 103 (see fig. 10), thereby completing the preparation of the shading layer and the first electrode.

The first electrode prepared by the method has the advantages that the material texture is soft, the storage time after etching is short, etching traces are not easy to leave, and the etching effect is improved.

As shown in fig. 11, the second electrode preparing step includes steps S41 to S46.

S41 semiconductor layer preparation, coating a layer of metal oxide semiconductor material including at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Titanium Oxide (IZTO) and Indium Gallium Zinc Titanium Oxide (IGZTO) on the upper surface of the buffer layer to prepare a semiconductor layer, wherein the thickness of the semiconductor layer is 100-1000A, and etching a semiconductor pattern.

S42 step of preparing gate insulation layer, depositing a layer of metal on the upper surface of the semiconductor pattern to prepare a gate insulation layer, wherein the gate insulation layer is made of silicon oxide (SiOx), nitrogen oxide (SiNx) or multilayer structure film, and the thickness of the gate insulation layer is 1000-3000A.

S43 preparing a gate layer on the upper surface of the gate insulating layer, wherein the gate layer is made of at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or alloy, and the thickness of the gate layer is 2000-10000A.

And S44, etching a gate layer pattern by using a yellow light process, and etching a gate insulating layer pattern to make the gate insulating layer pattern and the gate layer pattern oppositely arranged.

And a step of S45 plasma treatment, in which the upper surface of the substrate is plasma treated to significantly reduce the resistance of the semiconductor pattern not covered by the gate insulating layer, thereby forming an N + conductor layer, and the semiconductor pattern covered by the gate insulating layer forms a thin film transistor channel to maintain the semiconductor characteristics.

And S46, conducting the conductor layer above the light-emitting area to form a second electrode.

The second electrode is made the same as the transparent capacitor layer in the prior art, and therefore, it is only briefly described here.

The method for manufacturing the organic light emitting display panel has the technical effects that the original first capacitor layer is removed in the pixel area, the new first electrode is arranged at the bottom of the display panel and is made of at least one of transparent indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO) and aluminum-doped indium zinc oxide (IAZO), and the oxide has good volatility, so that material residue during etching can be avoided, and the etching effect is improved. The invention arranges the capacitor in the original capacitor area in the original luminous area, removes the original capacitor area, reduces the size of the pixel area and further improves the resolution of the display panel.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.