阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 金煐勋 梁在锡 李海王 于 2019-04-01 设计创作，主要内容包括：提供了一种半导体器件。该半导体器件包括：第一鳍图案和第二鳍图案,通过第一隔离沟槽分离并在第一方向上延伸；第三鳍图案,在与第一方向相交的第二方向上与第一鳍图案间隔开并在第一方向上延伸；第四鳍图案,通过第二隔离沟槽与第三鳍图案分离；第一栅结构,与第一鳍图案相交,并且具有沿第一鳍图案的上表面延伸的部分；第二栅结构,与第二鳍图案相交,并且具有沿第二鳍图案的上表面延伸的部分；以及第一元件隔离结构,填充第二隔离沟槽,并且面对第一栅结构的短边。(A semiconductor device is provided. The semiconductor device includes: a first fin pattern and a second fin pattern separated by the first isolation trench and extending in a first direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern separated from the third fin pattern by a second isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; and a first element isolation structure filling the second isolation trench and facing a short side of the first gate structure.)

1. A semiconductor device, comprising:

a first fin pattern and a second fin pattern separated by a first isolation trench and extending in a first direction;

a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction;

a fourth fin pattern separated from the third fin pattern by a second isolation trench;

a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern;

a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; and

a first element isolation structure filling the second isolation trench and facing a short side of the first gate structure.

2. The semiconductor device of claim 1, further comprising:

a field insulating layer disposed between the first fin pattern and the third fin pattern; and

a gate insulating support formed on the field insulating layer between the first element isolation structure and the first gate structure to contact the first element isolation structure and the first gate structure.

3. The semiconductor device of claim 2, wherein a width of the gate insulating support in the first direction is greater than a width of the first gate structure in the first direction.

4. The semiconductor device of claim 2, wherein the first gate structure comprises a high-permittivity insulating layer extending along an upper surface of the field insulating layer and a gate electrode disposed on the high-permittivity insulating layer, wherein the high-permittivity insulating layer does not extend along sidewalls of the gate insulating support.

5. The semiconductor device of claim 1, wherein the first element isolation structure contacts the first gate structure, and the first element isolation structure and the first gate structure are aligned in the second direction.

6. The semiconductor device of claim 1, further comprising:

a fifth fin pattern separated from the fourth fin pattern by a third isolation trench; and

a second element isolation structure filling the third isolation trench.

7. The semiconductor device of claim 6, further comprising: a connection isolation structure connecting an upper portion of the first element isolation structure and an upper portion of the second element isolation structure.

8. The semiconductor device according to claim 7, further comprising an interlayer insulating film provided between the connection isolation structure and the fourth fin pattern.

9. The semiconductor device of claim 6, further comprising an epitaxial pattern disposed on the fourth fin pattern.

10. The semiconductor device of claim 1, wherein the second gate structure intersects the fourth fin pattern.

11. The semiconductor device of claim 1, wherein an upper surface of the first element isolation structure is at the same height as an upper surface of the first gate structure.

12. A semiconductor device, comprising:

a first fin pattern and a second fin pattern aligned in a first direction as a longitudinal direction;

a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction;

a fourth fin pattern separated from the third fin pattern by a first isolation trench;

a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern;

a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern;

a third gate structure intersecting the first fin pattern and the third fin pattern; and

a first element isolation structure filling the first isolation trench,

wherein an upper surface of the first element isolation structure is higher than an upper surface of the third fin pattern.

13. The semiconductor device of claim 12, further comprising: a gate insulating support formed between the first element isolation structure and the first gate structure to contact the first element isolation structure and the first gate structure, wherein a width of the gate insulating support in the first direction is greater than a width of the first gate structure in the first direction.

14. The semiconductor device of claim 12, wherein the second gate structure intersects the fourth fin pattern.

15. The semiconductor device of claim 12, further comprising:

a fifth fin pattern separated from the fourth fin pattern by a second isolation trench; and

a second element isolation structure filling the second isolation trench and connected to the first element isolation structure.

16. A semiconductor device, comprising:

a first fin pattern and a second fin pattern disposed in an n-type metal oxide semiconductor (NMOS) region and aligned in a first direction as a longitudinal direction;

a third fin pattern disposed in a p-type metal oxide semiconductor (PMOS) region, spaced apart from the first fin pattern in a second direction intersecting the first direction, and extending in the first direction;

a fourth fin pattern separated from the third fin pattern by a first isolation trench;

a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern;

a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern;

a first element isolation structure filling the first isolation trench; and

a gate insulating support formed between and contacting the first gate structure and the first element isolation structure.

17. The semiconductor device of claim 16, wherein a width of the gate insulating support in the first direction is greater than a width of the first gate structure in the first direction.

18. The semiconductor device of claim 16, further comprising:

a fifth fin pattern separated from the fourth fin pattern by a second isolation trench; and

a second element isolation structure filling the second isolation trench.

19. The semiconductor device of claim 18, further comprising: a connection isolation structure connecting an upper portion of the first element isolation structure and an upper portion of the second element isolation structure.

20. The semiconductor device of claim 18, wherein the gate insulating support passes between the second element isolation structure and the second gate structure.

Technical Field

The present disclosure relates to semiconductor devices.

Background

As one of the shrinking techniques for increasing the density of semiconductor devices, a multi-gate transistor has been proposed. A multi-gate transistor may be obtained by forming a fin-shaped or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming a gate on a surface of the multi-channel active pattern.

The multi-gate transistor can be easily scaled down because it uses a three-dimensional (3D) channel. In addition, the current control capability of the multi-gate transistor can be improved without increasing the gate length of the multi-gate transistor. In addition, a Short Channel Effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

Disclosure of Invention

Aspects of the present disclosure provide a semiconductor device with increased element integration density and improved reliability and performance.

However, aspects of the present disclosure are not limited to those set forth herein. The foregoing and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by reference to the detailed description of the present disclosure given below.

According to some embodiments of the present disclosure, there is provided a semiconductor device including: a first fin pattern and a second fin pattern separated by the first isolation trench and extending in a first direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern separated from the third fin pattern by a second isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; and a first element isolation structure filling the second isolation trench and facing a short side of the first gate structure.

According to some embodiments of the present disclosure, there is provided a semiconductor device including: a first fin pattern and a second fin pattern aligned in a first direction as a longitudinal direction; a third fin pattern spaced apart from the first fin pattern in a second direction intersecting the first direction and extending in the first direction; a fourth fin pattern separated from the third fin pattern by the first isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; a third gate structure intersecting the first fin pattern and the third fin pattern; and a first element isolation structure filling the first isolation trench, wherein an upper surface of the first element isolation structure is higher than an upper surface of the third fin pattern.

According to some embodiments of the present disclosure, there is provided a semiconductor device including: a first fin pattern and a second fin pattern disposed in an n-type metal oxide semiconductor (NMOS) region and aligned in a first direction as a longitudinal direction; a third fin pattern disposed in a p-type metal oxide semiconductor (PMOS) region, spaced apart from the first fin pattern in a second direction intersecting the first direction, and extending in the first direction; a fourth fin pattern separated from the third fin pattern by the first isolation trench; a first gate structure intersecting the first fin pattern and having a portion extending along an upper surface of the first fin pattern; a second gate structure intersecting the second fin pattern and having a portion extending along an upper surface of the second fin pattern; a first element isolation structure filling the first isolation trench; and a gate insulating support formed between the first gate structure and the first element isolation structure to contact the first gate structure and the first element isolation structure.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic plan view of a semiconductor device according to an embodiment;

FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;

FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1;

FIG. 4 is a cross-sectional view taken along line C-C of FIG. 1;

FIG. 5 is a cross-sectional view taken along line D-D of FIG. 1;

FIG. 6 is a cross-sectional view taken along line E-E of FIG. 1;

fig. 7 shows a semiconductor device according to an embodiment;

fig. 8 shows a semiconductor device according to an embodiment;

fig. 9 shows a semiconductor device according to an embodiment;

fig. 10 shows a semiconductor device according to an embodiment;

fig. 11 shows a semiconductor device according to an embodiment;

fig. 12 and 13 show a semiconductor device according to an embodiment;

fig. 14 and 15 show a semiconductor device according to an embodiment;

fig. 16 shows a semiconductor device according to an embodiment;

fig. 17 and 18 show a semiconductor device according to an embodiment;

fig. 19 is a schematic plan view of a semiconductor device according to an embodiment;

FIG. 20 is a cross-sectional view taken along line D-D of FIG. 19;

fig. 21 is a schematic plan view of a semiconductor device according to an embodiment;

FIG. 22 is a cross-sectional view taken along line B-B of FIG. 21;

FIG. 23 is a cross-sectional view taken along line D-D of FIG. 21;

FIG. 24 is a cross-sectional view taken along line F-F of FIG. 21;

fig. 25 shows a semiconductor device according to an embodiment;

fig. 26 shows a semiconductor device according to an embodiment;

fig. 27 is a schematic plan view of a semiconductor device according to an embodiment;

FIG. 28 is a cross-sectional view taken along line B-B of FIG. 27;

fig. 29 is a schematic plan view of a semiconductor device according to the embodiment;

FIG. 30 is a cross-sectional view taken along line C-C of FIG. 29; and

fig. 31 to 34 are views illustrating some steps of a method of manufacturing a semiconductor device according to an embodiment.

Detailed Description

In the drawings related to a semiconductor device according to an embodiment, a fin field effect transistor (FinFET) including a channel region in a fin pattern shape is shown as an example. However, embodiments are not limited to finfets. A semiconductor device according to an embodiment may also include a tunneling FET, a transistor including a nanowire, a transistor including a nanoplate, or a three-dimensional (3D) transistor. In addition, the semiconductor device according to the embodiment may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), and the like.

Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 2 is a sectional view taken along line a-a of fig. 1. Fig. 3 is a sectional view taken along line B-B of fig. 1. Fig. 4 is a sectional view taken along line C-C of fig. 1. Fig. 5 is a sectional view taken along line D-D of fig. 1. Fig. 6 is a sectional view taken along line E-E of fig. 1. For convenience of description, the lower interlayer insulating film 191 and the upper interlayer insulating film 192 are not shown in fig. 1.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, for example, as a naming convention. Thus, a first element, component, region, layer or section discussed below in one section of the specification could be termed a second element, component, region, layer or section in the claims or another section of the specification without departing from the teachings of the present invention. Furthermore, in some cases, even if the terms "first", "second", etc. are not used in the specification to describe terms, the terms may be referred to as "first" or "second" in the claims so as to distinguish different elements claimed from each other.

Referring to fig. 1 to 6, the semiconductor device according to the embodiment includes a first fin pattern 110, a second fin pattern 210, a third fin pattern 310, and a fourth fin pattern 410, a first gate structure 120, a second gate structure 220, a third gate structure 320, a fourth gate structure 420, a gate insulating support 160, and a first element isolation structure 180.

The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In addition, the substrate 100 may be, but is not limited to, a silicon substrate or a substrate made of other materials such as silicon germanium, Silicon Germanium On Insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

Each of the first to fourth fin patterns 110, 210, 310, and 410 may protrude from the substrate 100. Each of the first to fourth fin patterns 110, 210, 310, and 410 may extend in the first direction X on the substrate 100. For example, each of the first to fourth fin patterns 110, 210, 310, and 410 may include a long side extending in a first direction X and a short side extending in a second direction Y perpendicular to the first direction X. Each of the first to fourth fin patterns 110, 210, 310, and 410 may be defined by a fin trench FT. For example, each of the long sides 110a, 210a, 310a, and 410a of the first to fourth fin patterns 110, 210, 310, and 410 may be defined by the fin trench FT.

The first fin pattern 110 and the second fin pattern 210 may be aligned in a first direction X as a longitudinal direction. The first fin pattern 110 and the second fin pattern 210 may be spaced apart in the first direction X. The short side 110b of the first fin pattern 110 and the short side 210b of the second fin pattern 210 may face each other. The first fin pattern 110 and the second fin pattern 210 may be separated by a fin cutting trench ST.

The third fin pattern 310 and the fourth fin pattern 410 may be aligned in the first direction X as a longitudinal direction. The third fin pattern 310 and the fourth fin pattern 410 may be spaced apart in the first direction X. A short side 310b of the third fin pattern 310 and a short side 410b of the fourth fin pattern 410 may face each other. The third fin pattern 310 and the fourth fin pattern 410 may be separated by the first isolation trench 180 t. For example, based on the upper surfaces of the first to fourth fin patterns 110, 210, 310 and 410, the width W11 of the fin cutting trench ST in the first direction X is greater than the width W12 of the first isolation trench 180t in the first direction X.

The third fin pattern 310 and the fourth fin pattern 410 may be spaced apart from the first fin pattern 110 in the second direction Y. A long side 310a of the third fin pattern 310 may face the long side 110a of the first fin pattern 110, and a long side 410a of the fourth fin pattern 410 may face the long side 210a of the second fin pattern 210. Although each of the first to fourth fin patterns 110, 210, 310, and 410 is illustrated as a plurality, the embodiment is not limited to this case.

When the first and second fin patterns 110 and 210 are formed in the first region and the third and fourth fin patterns 310 and 410 are formed in the second region, the first and second regions may be regions where transistors of the same conductivity type are formed or may be regions where transistors of different conductivity types are formed.

In the following description, it is assumed that the first and second fin patterns 110 and 210 are formed in an n-type metal oxide semiconductor (NMOS) region, and the third and fourth fin patterns 310 and 410 are formed in a p-type metal oxide semiconductor (PMOS) region.

Each of the first to fourth fin patterns 110, 210, 310, and 410 may be a portion of the substrate 100 or may include an epitaxial layer grown from the substrate 100. Each of the first to fourth fin patterns 110, 210, 310, and 410 may include an elemental semiconductor material such as silicon or germanium. In addition, each of the first to fourth fin patterns 110, 210, 310, and 410 may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping the binary or ternary compound with a group IV element. The III-V compound semiconductor may be, for example, a binary, ternary, or quaternary compound composed of at least one of aluminum (Al), gallium (Ga), and indium (In) (i.e., a group III element) In combination with at least one of phosphorus (P), arsenic (As), and antimony (Sb) (i.e., a group V element).

A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may at least partially fill the fin cut trench ST and the fin trench FT. The field insulating layer 105 may be disposed on a portion of sidewalls of each of the first to fourth fin patterns 110, 210, 310, and 410.

Upper surfaces of the first to fourth fin patterns 110, 210, 310, and 410 may protrude above an upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In the semiconductor device according to the embodiment, the field insulating layer 105 may fill a portion of the fin cut trench ST.

Each of the first to fourth gate structures 120, 220, 320 and 420 may extend in the second direction Y on the field insulating layer 105. The first gate structure 120 may be disposed on the first fin pattern 110 to intersect the first fin pattern 110. The first gate structure 120 may overlap an end portion of the first fin pattern 110 including the short side 110b of the first fin pattern 110. A portion of the first gate structure 120 may extend along an upper surface of each of the first fin patterns 110.

The second gate structure 220 may be disposed on the second fin pattern 210 and the fourth fin pattern 410 to intersect the second fin pattern 210 and the fourth fin pattern 410. The second gate structure 220 may overlap an end portion of the second fin pattern 210 including the short side 210b of the second fin pattern 210. A portion of the second gate structure 220 may extend along an upper surface of each of the second fin patterns 210.

The third gate structure 320 may be disposed on the first and third fin patterns 110 and 310 to intersect the first and third fin patterns 110 and 310. The fourth gate structure 420 may be disposed on the second fin pattern 210 and the fourth fin pattern 410 to intersect the second fin pattern 210 and the fourth fin pattern 410. The third and fourth gate structures 320 and 420 do not overlap with the end portions of the first and second fin patterns 110 and 210, respectively.

In the semiconductor device according to the embodiment, the first gate structure 120 may cover an end portion of the first fin pattern 110, and the second gate structure 220 may cover an end portion of the second fin pattern 210. The first gate structure 120 may cover sidewalls of the first fin pattern 110 defining the short side 110b of the first fin pattern 110. The second gate structure 220 may cover sidewalls of the second fin pattern 210 defining the short side 210b of the second fin pattern 210.

The first to fourth gate structures 120, 220, 320 and 420 may include first to fourth gate electrodes 130, 230, 330 and 430, first to fourth gate insulating layers 135, 235, 335 and 435, first to fourth gate spacers 140, 240, 340 and 440, first to fourth gate trenches 140t, 240t, 340t and 440 defined by the first to fourth gate spacers 140, 240, 340 and 440, and first to fourth capping patterns 145, 245, 345 and 445, respectively.

The first to fourth gate insulating layers 135, 235, 335 and 435 may extend along sidewalls and bottom surfaces of the first to fourth gate trenches 140t, 240t, 340t and 440t, respectively. Each of the first to fourth gate insulating layers 135, 235, 335 and 435 may include a high dielectric constant insulating layer.

The high dielectric constant insulating layer may include a high dielectric material having a higher dielectric constant than the silicon oxide layer. Each of the first to fourth gate insulating layers 135, 235, 335 and 435 may include one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

The first to fourth gate electrodes 130, 230, 330 and 430 may be disposed on the first to fourth gate insulating layers 135, 235, 335 and 435, respectively. The first to fourth gate electrodes 130, 230, 330 and 430 may at least partially fill the first to fourth gate trenches 140t, 240t, 340t and 440t, respectively.

Each of the first to fourth gate electrodes 130, 230, 330 and 430 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (0s), At least one of silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

The first to fourth gate spacers 140, 240, 340 and 440 may be formed on sidewalls of the first to fourth gate electrodes 130, 230, 330 and 430, respectively. Each of the first to fourth gate spacers 140, 240, 340 and 440 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2) and silicon oxycarbonitride (SiOCN).

The first to fourth capping patterns 145, 245, 345 and 445 may be formed on the first to fourth gate electrodes 130, 230, 330 and 430 and the first to fourth gate spacers 140, 240, 340 and 440, respectively.

Each of the first to fourth capping patterns 145, 245, 345 and 445 may include, for example, silicon oxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN).

In fig. 2, 3 and 5, the first to fourth capping patterns 145, 245, 345 and 445 are shown to not fill a portion of the first to fourth gate trenches 140t, 240t, 340t and 440t, respectively. However, this is merely an example used for convenience of description, and the embodiments are not limited to this example.

A first epitaxial pattern 150 may be formed on each of the first fin patterns 110. A second epitaxial pattern 250 may be formed on each of the second fin patterns 210. A third epitaxial pattern 350 may be formed on each of the third fin patterns 310. A fourth epitaxial pattern 450 may be formed on each fourth fin pattern 410.

The first epitaxial pattern 150 may be included in a source/drain of a transistor using the first fin pattern 110 as a channel region. The second epitaxial pattern 250 may be included in a source/drain of a transistor using the second fin pattern 210 as a channel region. The third epitaxial pattern 350 may be included in a source/drain of a transistor using the third fin pattern 310 as a channel region. The fourth epitaxial pattern 450 may be included in a source/drain of a transistor using the fourth fin pattern 410 as a channel region.

The lower interlayer insulating film 191 may be formed on the field insulating layer 105 and may cover the first to fourth epitaxial patterns 150, 250, 350 and 450. The lower interlayer insulating film 191 may be formed around the first to fourth gate structures 120, 220, 320 and 420. The lower interlayer insulating film 191 may at least partially cover sidewalls of the first to fourth gate structures 120, 220, 320 and 420.

An upper surface of the lower interlayer insulating film 191 may be located in the same plane as an upper surface of each of the first to fourth capping patterns 145, 245, 345 and 445. A lower surface of the lower interlayer insulating film 191 may be positioned below a lower surface of each of the first to fourth capping patterns 145, 245, 345 and 445.

Although not shown, the lower interlayer insulating film 191 may further include an etch stop layer extending along the upper surfaces of the first to fourth epitaxial patterns 150, 250, 350 and 450.

The first element isolation structure 180 may be disposed between the third fin pattern 310 and the fourth fin pattern 410. The first element isolation structure 180 may be disposed between the short side 310b of the third fin pattern 310 and the short side 410b of the fourth fin pattern 410. The first element isolation structure 180 may separate the third fin pattern 310 and the fourth fin pattern 410. The first element isolation structure 180 may be disposed between the second gate structure 220 and the third gate structure 320.

The first element isolation structure 180 includes a first side 180a extending in the first direction X and a second side 180b extending in the second direction Y. The first side 180a of the first element isolation structure 180 may face the short side 120b of the first gate structure 120. The second side 180b of the first element isolation structure 180 may face the short side 310b of the third fin pattern 310 and the short side 410b of the fourth fin pattern 410.

The first element isolation structure 180 and the first gate structure 120 may be aligned in the second direction Y. The first element isolation structure 180 is disposed on an extension line of the first gate structure 120 extending in the second direction Y.

The first element isolation structure 180 may be disposed in the first isolation trench 180t included in the lower interlayer insulating film 191. The first element isolation structure 180 may fill the first isolation trench 180 t. The first isolation trench 180t may be formed between the third and fourth epitaxial patterns 350 and 450.

Sidewalls of the first isolation trench 180t extending in the second direction Y between the third and fourth epitaxial patterns 350 and 450 may be defined by the first dummy spacer 185, the lower interlayer insulating film 191, and the third and fourth fin patterns 310 and 410.

An upper surface of the first element isolation structure 180 is higher than upper surfaces of the third and fourth fin patterns 310 and 410. For example, the upper surface of the first element isolation structure 180 may be located in the same plane as the upper surface of the lower interlayer insulating film 191. The upper surface of the first element isolation structure 180 may be located in the same plane as the upper surfaces of the second to fourth gate structures 220, 320 and 420.

In fig. 3, the width between the sidewalls of the first isolation trench 180t defined by the third fin pattern 310 and the fourth fin pattern 410 increases as the distance from the substrate 100 increases. For example, the width of the first isolation trench 180t between sidewalls of the first isolation trench 180t defined by the third and fourth fin patterns 310 and 410 in the first direction X may gradually increase in an upward direction away from the upper surface of the substrate 100. However, the embodiments are not limited to this case. For example, according to an alternative embodiment, the width between the sidewalls of the first isolation trench 180t defined by the third and fourth fin patterns 310 and 410 may not change as the distance from the substrate 100 increases.

In fig. 4, a portion of the sidewall of the first isolation trench 180t extending in the first direction X may be defined by the field insulating layer 105. A portion of the first isolation trench 180t may be, but is not necessarily, recessed into the field insulating layer 105.

The bottom surface of the first isolation trench 180t may be defined by the field insulation layer 105, the substrate 100, and the remaining fin RF. The remaining fin RF may be a portion remaining after removing the fin pattern portion in an etching process for forming the first isolation trench 180 t. Unlike the drawing, the remaining fin RF may not exist.

The first element isolation structure 180 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the first element isolation structure 180 is illustrated as a single layer, this is only an example used for convenience of description, and the first element isolation structure 180 is not limited to a single layer.

The material composition of the first dummy spacers 185 and the first gate spacers 140 may be the same. Unlike the drawing, the first dummy spacers 185 may not be disposed on sidewalls of the first element isolation structure 180.

The gate insulating support 160 may be disposed on the field insulating layer 105 between the first fin pattern 110 and the third fin pattern 310. The gate insulating support 160 may be spaced apart from the first and third fin patterns 110 and 310 in the second direction Y.

The gate insulating support 160 may be disposed between the first gate structure 120 and the first element isolation structure 180. The gate insulating support 160 may be disposed on the field insulating layer 105 between the first gate structure 120 and the first element isolation structure 180.

The gate insulating support 160 may separate the first gate structure 120 and the first element isolation structure 180. The gate insulating supporter 160 may pass between the first gate structure 120 and the first element isolation structure 180. The first gate structure 120 and the first element isolation structure 180 may be disposed along the second direction Y with the gate insulating support 160 interposed between the first gate structure 120 and the first element isolation structure 180.

The gate insulating support 160 contacts the first gate structure 120 and the first element isolation structure 180.

It will be understood that when an element is referred to as being "in contact with" or "in contact with" another element, there are no intervening elements present at the point of contact.

The gate insulating support 160 includes a first side 160a extending in the first direction X and a second side 160b extending in the second direction Y. The first gate structure 120 and the first element isolation structure 180 contact the first side 160a of the gate insulating support 160.

In the semiconductor device according to the embodiment, the width W22 (see fig. 5) of the gate insulating supporter 160 in the first direction X may be greater than or equal to the width W21 (see fig. 2) of the first gate structure 120 in the first direction X.

In fig. 1 and 5, the width W22 of the gate insulating supporter 160 in the first direction X is greater than the width W21 of the first gate structure 120 in the first direction X.

In addition, in fig. 1 and 5, the gate insulating support 160 does not contact the second and third gate structures 220 and 320. However, the embodiments are not limited to this case.

The gate insulating supporter 160 may be disposed in the insulating trench 160t included in the lower interlayer insulating film 191. The gate insulating supporter 160 may fill the insulating trench 160 t. In fig. 4 and 5, a portion of the sidewall of the insulation trench 160t may be recessed into the field insulation layer 105 and defined by the field insulation layer 105. However, the embodiments are not limited to this case.

In fig. 4, the bottom surface of the first isolation trench 180t defined by the field insulation layer 105 is shown closer to the substrate 100 than the bottom surface of the insulation trench 160 t. However, the embodiments are not limited to this case.

The gate insulating support 160 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the gate insulating support 160 is illustrated as a single layer in fig. 4 and 5, this is merely an example used for convenience of description, and the gate insulating support 160 is not limited to a single layer.

In fig. 4, the first gate insulating layer 135 does not extend along the sidewalls of the gate insulating support 160. The first gate electrode 130 may contact the gate insulating support 160. For example, the sidewall of the first gate electrode 130 extending in the first direction X may contact the sidewall of the gate insulating support 160 extending in the first direction X. In fig. 5, the upper surface of the gate insulating support 160 may be located in the same plane as the upper surface of the lower interlayer insulating film 191. The upper surface of the gate insulating support 160 may be located in the same plane as the upper surfaces of the second to fourth gate structures 220, 320 and 420.

The upper interlayer insulating film 192 is formed on the lower interlayer insulating film 191, the gate insulating support 160, the first element isolation structure 180, and the first to fourth gate structures 120, 220, 320, and 420. The interlayer insulating film 190 includes a lower interlayer insulating film 191 and an upper interlayer insulating film 192. Each of the lower interlayer insulating film 191 and the upper interlayer insulating film 192 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, Flowable Oxide (FOX), Tosozasilazane (TOSZ), Undoped Silicate Glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Plasma Enhanced Tetraethylorthosilicate (PETEOS), fluorosilicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous carbon fluoride, organosilicate glass (OSG), parylene, bis-benzocyclobutene (BCB), SiLK, polyimide, porous polymer material, or a combination thereof.

Fig. 7 illustrates a semiconductor device according to an embodiment. Fig. 8 illustrates a semiconductor device according to an embodiment. Fig. 9 illustrates a semiconductor device according to an embodiment. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 7, in the semiconductor device according to the embodiment, the first gate insulating layer 135 includes a portion extending along a sidewall of the gate insulating support 160 in the first direction X.

The first gate insulating layer 135 may extend between the first gate electrode 130 and the gate insulating support 160.

Referring to fig. 8, in the semiconductor device according to the embodiment, the first to fourth gate electrodes 130, 230, 330 and 430 may partially fill the first to fourth gate trenches 140t, 240t, 340t and 440t, respectively.

The first to fourth capping patterns 145, 245, 345 and 445 may fill the first to fourth gate trenches 140t, 240t, 340t and 440t remaining after the first to fourth gate electrodes 130, 230, 330 and 430 are formed, respectively. The upper surfaces of the first to fourth gate spacers 140, 240, 340 and 440 may be located in the same plane as the upper surfaces of the first to fourth capping patterns 145, 245, 345 and 445.

Although the first to fourth gate insulating layers 135, 235, 335 and 435 are illustrated in the drawings not to extend between the first to fourth capping patterns 145, 245, 345 and 445 and the first to fourth gate spacers 140, 240, 340 and 440, the embodiment is not limited to this case.

Referring to fig. 9, in the semiconductor device according to the embodiment, the upper surfaces of the first to fourth gate electrodes 130, 230, 330 and 430 may be located in the same plane as the upper surface of the lower interlayer insulating film 191.

The upper surfaces of the first to fourth gate electrodes 130, 230, 330 and 430 may be located in the same plane as the upper surfaces of the gate insulating supports 160 (see fig. 5) and the upper surface of the first element isolating structure 180 (see fig. 3). The first to fourth gate structures 120, 220, 320 and 420 may not include capping patterns 145, 245, 345 and 445, respectively.

Fig. 10 illustrates a semiconductor device according to an embodiment. Fig. 11 illustrates a semiconductor device according to an embodiment. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 10, the semiconductor device according to the embodiment may further include a connection spacer 120cs protruding from an upper surface of the field insulating layer 105 between the gate insulating supporter 160 and the field insulating layer 105.

The connection spacer 120cs may be recessed into the gate insulating support 160. For example, the height of the connection spacer 120cs in the vertical direction is less than the height of the second to fourth gate spacers 240 to 440 in the vertical direction. The bottom surface of the connection spacer 120cs and the bottom surfaces of the second to fourth gate spacers 240, 340 and 440 may contact the field insulating layer 105. Accordingly, the upper surfaces of the second to fourth gate spacers 240, 340 and 440 are higher than the upper surface of the connection spacer 120 cs.

In addition, the connection spacer 120cs is directly connected to the first gate structure 120. The connection spacers 120cs are directly connected to the first dummy spacers 185 disposed on the sidewalls of the first element isolation structure 180. The connection spacer 120cs contacts the first gate structure 120. The material composition of the connection spacer 120cs and the first gate spacer 140 may be the same.

The bottom surface of the gate insulating support 160 may be defined by the field insulating layer 105 and the connection spacer 120 cs.

Referring to fig. 11, in the semiconductor device according to the embodiment, a portion of the lower interlayer insulating film 191 may be interposed between the gate insulating supporter 160 and the field insulating layer 105.

The bottom surface of the gate insulating support 160 includes a first portion defined by the field insulating layer 105 and a second portion defined by the lower interlayer insulating film 191. The second portions of the gate insulating supports 160 may be disposed along the first direction X with the first portions of the gate insulating supports 160 interposed therebetween.

The gate insulating support 160, the bottom surface of which is defined by the field insulating layer 105, may contact the field insulating layer 105. The gate insulating support 160 whose bottom surface is defined by the lower interlayer insulating film 191 may not contact the field insulating layer 105.

Fig. 12 and 13 show a semiconductor device according to an embodiment. Fig. 14 and 15 show a semiconductor device according to an embodiment. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 12 and 13, a deep trench DT may be formed in the substrate 100 between the first fin pattern 110 and the third fin pattern 310.

The deep trench DT may be deeper than the fin trenches FT defining the long sides 110a (see fig. 1) of the first fin pattern 110 and the long sides 310a (see fig. 1) of the third fin pattern 310. The field insulating layer 105 fills the deep trench DT.

The gate insulating supporter 160 may be formed on the field insulating layer 105 filling the deep trench DT.

Referring to fig. 14 and 15, the semiconductor device according to the embodiment may further include a protrusion pattern FP protruding from the substrate 100 between the first fin pattern 110 and the third fin pattern 310.

The height of the protrusion pattern FP is less than the height of the first fin pattern 110 and the height of the third fin pattern 310. The height of the protrusion pattern FP is less than the height of the portion of the field insulating layer 105 overlapping the first gate electrode 130.

For example, the upper surface of the protrusion pattern FP may be covered by the field insulating layer 105. The protrusion pattern FP may extend in the first direction X, but need not necessarily be so (see fig. 1).

Although the bottom surface of the gate insulating support 160 is shown to be higher than the upper surface of the protrusion pattern FP, the embodiment is not limited to this case. The gate insulating supporter 160 may also contact the protrusion pattern FP. In this case, the upper surface of the protrusion pattern FP is not covered with the field insulating layer 105.

Fig. 16 shows a semiconductor device according to an embodiment. Fig. 17 and 18 show a semiconductor device according to an embodiment. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 16, the semiconductor device according to the embodiment may include a contact 195 penetrating the interlayer insulating film 190.

The contact 195 may be connected to the first and second epitaxial patterns 150 and 250, respectively. Although the contact 195 is illustrated as not contacting the first to fourth gate structures 120, 220, 320 and 420, the embodiment is not limited to this case.

Although each contact 195 is shown as a single structure, embodiments are not limited in this context. Each contact 195 may also include a plurality of structures arranged in the thickness direction of the substrate 100.

The contact 195 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and doped polysilicon. Unlike in the drawing, a silicide layer may also be formed between the contact 195 and the epitaxial patterns 150 and 250.

Referring to fig. 17 and 18, in the semiconductor device according to the embodiment, an upper surface of the field insulating layer 105 filling the fin cut trench ST may be at the same height or a higher height as an upper surface of the first fin pattern 110 and an upper surface of the second fin pattern 210.

Sidewalls of the first fin pattern 110 defining the short side 110b of the first fin pattern 110 and sidewalls of the second fin pattern 210 defining the short side 210b of the second fin pattern 210 may be covered with the field insulating layer 105.

For example, the first gate structure 120 does not cover sidewalls of the first fin pattern 110 defining the short side 110b (see fig. 1) of the first fin pattern 110. The second gate structure 220 does not cover sidewalls of the second fin pattern 210 defining the short side 210b (see fig. 1) of the second fin pattern 210.

Fig. 19 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 20 is a sectional view taken along line D-D of fig. 19. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 19 and 20, in the semiconductor device according to the embodiment, the width of the gate insulating support 160 in the first direction X may be less than or equal to the width of the first gate structure 120 in the first direction X.

The gate insulating supports 160 may be formed between the first dummy spacers 185. The first dummy spacer 185 may be disposed on a sidewall of the gate insulating support 160. The first dummy spacers 185 may extend along sidewalls of the gate insulating supports 160 and sidewalls of the first element isolation structures 180.

The insulation trench 160t may be aligned with the first dummy spacer 185. In the semiconductor device manufacturing process, the insulation trench 160t may be formed using the first dummy spacer 185 as a mask.

Fig. 21 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 22 is a sectional view taken along line B-B of fig. 21. Fig. 23 is a sectional view taken along line D-D of fig. 21. Fig. 24 is a sectional view taken along line F-F of fig. 21. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 21 to 24, the semiconductor device according to the embodiment may further include a fifth fin pattern 510, a second element isolation structure 181, and a connection isolation structure 182.

The fifth fin pattern 510 may protrude from the substrate 100. The fifth fin pattern 510 may extend in the first direction X on the substrate 100. The fifth fin pattern 510 may include a long side 510a extending in the first direction X and a short side 510b extending in the second direction Y.

The fifth fin pattern 510 may be aligned with the third fin pattern 310 and the fourth fin pattern 410 in the first direction X as a longitudinal direction. The third to fifth fin patterns 310 to 510 may be sequentially arranged in the first direction X. The fourth fin pattern 410 may be disposed between the third fin pattern 310 and the fifth fin pattern 510. The fourth fin pattern 410 and the fifth fin pattern 510 may be separated by the second isolation trench 181 t. The third to fifth fin patterns 310 to 510 are disposed in regions where the same conductive type transistors are formed.

The second gate structure 220 may intersect the second fin pattern 210, but may not intersect the fourth fin pattern 410 and the fifth fin pattern 510. The second gate structure 220 may extend up to the gate insulating support 160. The fourth gate structure 420 may be disposed on the second and fifth fin patterns 210 and 510 to intersect the second and fifth fin patterns 210 and 510.

A fourth epitaxial pattern 450 may be formed on each fourth fin pattern 410. A fifth epitaxial pattern 550 may be formed on each fifth fin pattern 510.

The second element isolation structure 181 may be disposed between the fourth fin pattern 410 and the fifth fin pattern 510. The fourth fin pattern 410 may be disposed between the first element isolation structure 180 and the second element isolation structure 181. The second element isolation structure 181 may be disposed between short sides of the fourth fin pattern 410 and the fifth fin pattern 510.

The second element isolation structure 181 may separate the fourth fin pattern 410 and the fifth fin pattern 510. The first element isolation structure 180 and the second element isolation structure 181 may be disposed between the third gate structure 320 and the fourth gate structure 420.

The second element isolation structure 181 includes a first side 181a extending in the first direction X and a second side 181b extending in the second direction Y. The first side 181a of the second element isolation structure 181 may face the short side 220b of the second gate structure 220. The second side 181b of the second element isolation structure 181 may face the short sides of the fourth and fifth fin patterns 410 and 510.

The second element isolation structure 181 and the second gate structure 220 may be aligned in the second direction Y. The second element isolation structure 181 is disposed on an extension line of the second gate structure 220 extending in the second direction Y.

The second element isolation structure 181 may be disposed in the second isolation trench 181t included in the lower interlayer insulating film 191. The second element isolation structure 181 may fill the second isolation trench 181 t.

The second isolation trench 181t may be formed between the fourth and fifth epitaxial patterns 450 and 550. Sidewalls of the second isolation trench 181t extending in the second direction Y between the fourth and fifth epitaxial patterns 450 and 550 may be defined by the second dummy spacer 186, the lower interlayer insulating film 191, and the fourth and fifth fin patterns 410 and 510.

An upper surface of the second element isolation structure 181 is higher than upper surfaces of the fourth and fifth fin patterns 410 and 510. For example, the upper surface of the second element isolation structure 181 may be located in the same plane as the upper surface of the lower interlayer insulating film 191.

The upper surface of the second element isolation structure 181 may be located in the same plane as the upper surfaces of the third and fourth gate structures 320 and 420.

In fig. 22, the width between the sidewalls of the second isolation trench 181t defined by the fourth and fifth fin patterns 410 and 510 increases as the distance from the substrate 100 increases. For example, the width between the sidewalls of the second isolation trench 181t defined by the fourth and fifth fin patterns 410 and 510 in the first direction X gradually increases as the distance from the substrate 100 increases. However, the embodiments are not limited to this case. For example, the width in the first direction X between sidewalls of the second isolation trench 181t defined by the fourth and fifth fin patterns 410 and 510 may remain the same as the distance from the substrate 100 increases.

In fig. 24, a portion of the sidewall of the second isolation trench 181t extending in the first direction X may be defined by the field insulating layer 105. A portion of the second isolation trench 181t may be, but is not necessarily, recessed into the field insulating layer 105.

The bottom surface of the second isolation trench 181t may be defined by the field insulation layer 105, the substrate 100, and the remaining fin RF. The remaining fin RF may be a portion remaining after removing the fin pattern portion in an etching process for forming the second isolation trench 181 t. Unlike the drawing, the remaining fin RF may not exist.

In fig. 24, the bottom surface of the second isolation trench 181t defined by the field insulation layer 105 is shown closer to the substrate 100 than the bottom surface of the insulation trench 160 t. However, the embodiments are not limited to this case.

The second element isolation structure 181 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the second element isolation structure 181 is illustrated as a single layer, this is only an example used for convenience of description, and the second element isolation structure 181 is not limited to a single layer.

The material composition of the second dummy spacers 186 and the second gate spacers 240 may be the same. Unlike the drawing, the second dummy spacers 186 may not be disposed on the sidewalls of the second element isolation structure 181.

The connection isolation structure 182 may be disposed between the first element isolation structure 180 and the second element isolation structure 181. The connection isolation structure 182 may connect the first element isolation structure 180 and the second element isolation structure 181. The second element isolation structure 181 may be connected to the first element isolation structure 180 by a connection isolation structure 182.

The connection isolation structure 182 may connect an upper portion of the first element isolation structure 180 and an upper portion of the second element isolation structure 181. The upper surface of the connection isolation structure 182 may be located in the same plane as the upper surfaces of the first and second element isolation structures 180 and 181.

The connection isolation structure 182 may cover the fourth fin pattern 410 and the fourth epitaxial pattern 450. A portion of the lower interlayer insulating film 191 may be disposed between the connection isolation structure 182 and each of the fourth fin patterns 410.

For example, a portion of the lower interlayer insulating film 191 may be disposed between the connection isolation structure 182 and each of the fourth epitaxial patterns 450. For example, the lower surface of the connection isolation structure 182 is higher than the upper surface of the fourth fin pattern 410 and the upper surface of the fourth epitaxial pattern 450 based on the bottom surfaces of the first and second element isolation structures 180 and 181.

The first and second element isolation structures 180 and 181 and the connection isolation structure 182 may be included in the integrated isolation structure 180 ST. For example, the first and second element isolation structures 180 and 181 and the connection isolation structure 182 may be formed in the same process to produce a unitary structure.

The connection isolation structure 182 may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide.

The gate insulating support 160 may be disposed between the first gate structure 120 and the first element isolation structure 180 and between the second gate structure 220 and the second element isolation structure 181. The gate insulating support 160 may be disposed on the field insulating layer 105 between the first gate structure 120 and the first element isolation structure 180 and between the second gate structure 220 and the second element isolation structure 181.

The gate insulating support 160 may separate the second gate structure 220 and the second element isolation structure 181. The gate insulating supporter 160 may pass between the second gate structure 220 and the second element isolation structure 181. The second gate structure 220 and the second element isolation structure 181 may be disposed along the second direction Y with the gate insulating support 160 interposed between the second gate structure 220 and the second element isolation structure 181.

The gate insulating support 160 contacts the second gate structure 220 and the second element isolation structure 181. The gate insulating support 160 may contact the connection isolation structure 182.

The gate insulating support 160 includes a first side 160a extending in the first direction X and a second side 160b extending in the second direction Y. The second gate structure 220 and the second element isolation structure 181 contact the first side 160a of the gate insulating support 160. The connection isolation structure 182 may contact the first side 160a of the gate insulating support 160.

In the semiconductor device according to the embodiment, the width of the gate insulating support 160 in the first direction X is greater than the width of the first gate structure 120 and the width of the second gate structure 220 in the first direction X. Although the gate insulating support 160 is illustrated as not contacting the third and fourth gate structures 320 and 420 in fig. 23, embodiments are not limited to this case.

Fig. 25 shows a semiconductor device according to an embodiment. Fig. 26 shows a semiconductor device according to an embodiment. For ease of description, the following description of the embodiments focuses mainly on differences from the elements and features described above with reference to fig. 21 to 24.

Referring to fig. 25, in the semiconductor device according to the embodiment, the connection isolation structure 182 may contact the fourth epitaxial pattern 450.

In the etching process for forming the connection isolation structure 182, an upper surface of the fourth epitaxial pattern 450 may be exposed. The connection isolation structure 182 may be formed on the exposed fourth epitaxial pattern 450.

Referring to fig. 26, in the semiconductor device according to the embodiment, a portion of the connection isolation structure 182 may be recessed into the fourth epitaxial pattern 450.

In the etching process for forming the connection isolation structure 182, a portion of the fourth epitaxial pattern 450 may be etched. The connection isolation structure 182 may be formed on the partially etched fourth epitaxial pattern 450.

Fig. 27 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 28 is a sectional view taken along line B-B of fig. 27. For ease of description, the following description of the embodiments focuses mainly on differences from the elements and features described above with reference to fig. 21 to 24.

Referring to fig. 27 and 28, in the semiconductor device according to the embodiment, the first element isolation structure 180 is separated from the second element isolation structure 181.

A connection isolation structure for connecting the first element isolation structure 180 and the second element isolation structure 181 is not provided between the first element isolation structure 180 and the second element isolation structure 181.

Connection isolation structures for connecting the first element isolation structure 180 and the second element isolation structure 181 are not disposed on the fourth fin pattern 410 and the fourth epitaxial pattern 450.

Fig. 29 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 30 is a sectional view taken along line C-C of fig. 29. For ease of description, the following description of the embodiments focuses primarily on differences from the elements and features described above with reference to fig. 1-6.

Referring to fig. 29 and 30, in the semiconductor device according to the embodiment, the first gate structure 120 may contact the first element isolation structure 180.

The short side 120b of the first gate structure 120 may contact the first side 180a of the first element isolation structure 180. The first gate structure 120 and the first element isolation structure 180 contacting each other may be aligned in a line along the second direction Y.

The first gate electrode 130, the first gate insulating layer 135, and the first capping pattern 145 may contact the first element isolation structure 180.

Fig. 31 to 34 are views illustrating some steps of a method of manufacturing a semiconductor device according to an embodiment.

Referring to fig. 31, a first fin pattern 110 and a second fin pattern 210 aligned in a first direction X are formed. The first and second fin patterns 110 and 210 are spaced apart from each other in the first direction X.

A Pre-fin (Pre-fin) F1 extending in the first direction X is formed. The pre-fin F1 is spaced apart from the first fin pattern 110 and the second fin pattern 210 in the second direction Y.

Referring to fig. 32, a pre-gate structure 120G and a third gate structure 320 are formed on the first fin pattern 110 and the pre-fin F1.

Each of the pre-gate structure 120G and the third gate structure 320 intersects the first fin pattern 110 and the pre-fin F1. The pre-gate structure 120G overlaps an end portion of the first fin pattern 110 including the short side 110b of the first fin pattern 110. The third gate structure 320 does not overlap the end of the first fin pattern 110.

A second gate structure 220 and a fourth gate structure 420 are formed on the second fin pattern 210 and the pre-fin F1.

Each of the second gate structure 220 and the fourth gate structure 420 intersects the second fin pattern 210 and the pre-fin F1. The second gate structure 220 overlaps an end portion of the second fin pattern 210 including the short side 210b of the second fin pattern 210. The fourth gate structure 420 does not overlap with the end of the second fin pattern 210.

In an example, the pre-gate structure 120G may include a gate electrode formed by a Replacement Metal Gate (RMG) process. In another example, the pre-gate structure 120G may include a dummy molded gate prior to the RMG process.

In the method of manufacturing the semiconductor device according to the embodiment, the pre-gate structure 120G is described as including a gate electrode formed by the RMG process.

Referring to fig. 33, a gate insulating supporter 160 for cutting the pre-gate structure 120G is formed.

The gate insulating support 160 may divide the pre-gate structure 120G into a first gate structure 120 and a fifth gate structure 120 RG.

The first gate structure 120 may intersect the first fin pattern 110. Fifth gate structure 120RG intersects with pre-fin F1.

Referring to fig. 34, the fifth gate structure 120RG and the pre-fin F1 may be partially removed.

As a result of partially removing the pre-fin F1, the pre-fin F1 may be separated into the third fin pattern 310 and the fourth fin pattern 410.

The first element isolation structure 180 may be formed at a position where the fifth gate structure 120RG and the pre-fin F1 have been removed.

The gate insulating support 160 may contact the first element isolation structure 180 and the first gate structure 120.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than to the foregoing description to indicate the scope of the invention.