阅读说明：本技术 一种低时延与低开销的dbpsk解调器 (DBPSK demodulator with low time delay and low overhead ) 是由 卢有亮 胡再青 姜书艳 向新明 任伟 卢鹏宇 陈勇 郑伟生 于 2019-09-25 设计创作，主要内容包括：本发明公开一种低时延与低开销的DBPSK解调器,应用于通信领域,针对现有DBPSK解调中存在时延过大和开销过大的缺陷,本发明通过传统cordic算法将前N/3次的迭代运算结果存储至小容量ROM查找表中,并结合概率加法器,若当前迭代次数i小于或等于N/3时,通过ROM查找表地址得到在ROM查找表中存储的迭代结果；若当前迭代次数i大于N/3时,通过在ROM查找表中找到第N/3次迭代结果,利用概率加法器和移位寄存器进行i-N/3次迭代运算；所述校正模块对当前迭代结果采用最佳一致逼近法进行校正；从而降低dbpsk解调器的时延与开销。(The invention discloses a DBPSK demodulator with low time delay and low cost, which is applied to the field of communication, and aims at the defects of overlarge time delay and overlarge cost in the conventional DBPSK demodulation.A traditional cordic algorithm is used for storing the previous N/3 times of iterative operation results into a small-capacity ROM lookup table, and a probability adder is combined, if the current iterative times i are less than or equal to N/3, the iterative results stored in the ROM lookup table are obtained through the ROM lookup table address; if the current iteration number i is larger than N/3, an N/3 th iteration result is found in a ROM lookup table, and a probability adder and a shift register are used for performing i-N/3 times of iteration operation; the correction module corrects the current iteration result by adopting an optimal consistent approximation method; thereby reducing the delay and overhead of the dbpsk demodulator.)

1. A cordic module that replaces a conventional adder with a probabilistic adder, further comprising: the device comprises a ROM lookup table, a shift register and a correction module, wherein the ROM lookup table is used for storing the operation result of previous N/3 times of iteration, and if the current iteration time i is less than or equal to N/3, the iteration result stored in the ROM lookup table is obtained through the address of the ROM lookup table; if the current iteration number i is larger than N/3, an N/3 th iteration result is found in a ROM lookup table, and then a probability adder and a shift register are utilized to carry out i-N/3 iteration operation; and the correction module corrects the current iteration result by adopting an optimal consistent approximation method.

2. A cordic module according to claim 1, in which the results of the first N/3 iterations stored in the ROM lookup table are calculated by conventional cordic algorithms.

3. A cordic module according to claim 2, in which N is less than or equal to 16.

4. The cordic module of claim 3, wherein the ROM lookup table maximum address is less than or equal to 63.

5. A low-latency and low-overhead DBPSK demodulator, characterized in that it comprises at least a cordic module according to any of claims 1 to 4.

6. The low latency and low overhead DBPSK demodulator according to claim 5, further comprising: the device comprises a modulation signal input module, a forming filter and a phase difference module, wherein a signal modulated by the modulation signal input module is input into the forming filter, the signal subjected to forming filtering is input into a cordic module for phase solving, and a phase result output by the cordic module is sent into the difference module for phase difference.

Technical Field

The invention belongs to the field of communication, and particularly relates to a DBPSK demodulator.

Background

The rapid development of digital communication technology provides important support for national economic development and modern national defense construction, and the modem technology has gained more and more attention as an important component part of digital signal processing. The meaning of modem is that in order for a digital signal to be transmitted in a band pass channel, the carrier must be modulated with the digital baseband signal to match the signal to the characteristics of the channel.

The process of converting a digital baseband signal into a digital baseband signal by controlling a carrier wave with the digital baseband signal is called digital modulation, and the process of restoring the digital baseband signal to a digital baseband signal by a demodulator at a receiving end is called digital demodulation. Digital modulation comprises multiple modes such as PSK, ASK and FSK, wherein BPSK is the simplest one of PSK, but in the BPSK signal carrier recovery process, the condition that coherent carrier and received signal are completely inverted can occur, the demodulated digital baseband signal is exactly opposite to the transmitted digital baseband signal, all symbol symbols output by a decision device are wrong, in order to avoid the phenomenon, differential phase shift keying, namely DBPSK, is often used in practical application, and therefore, the research on DBPSK modulation and demodulation technology has important significance.

In DBPSK demodulation, a cordic algorithm is commonly used for solving the phase, the conventional cordic algorithm can calculate the square root, sine and cosine, a mode and the phase through steps of shifting, adding and subtracting and the like and complete coordinate transformation, and the method is easy to realize in VLSI devices such as an FPGA and the like. However, the existing cordic algorithm needs to perform iterative operation to solve the phase, so that the following problems exist in DBPSK demodulation:

1. the overhead is too large;

2. the time delay is too large.

Disclosure of Invention

In order to solve the technical problem, the invention provides a low-delay and low-overhead DBPSK demodulator, which helps to reduce overhead and delay by using a method of combining a small-capacity lookup table with a probability adder.

The technical scheme adopted by the invention is as follows: a low-latency and low-overhead DBPSK demodulator, comprising: the device comprises a modulation signal input module, a forming filter, a cordic module and a phase difference module, wherein a signal modulated by the modulation signal input module is input into the forming filter, the signal subjected to forming filtering is input into the cordic module to be subjected to phase solving, and a phase result output by the cordic module is sent into the difference module to be subjected to phase difference.

The invention introduces a probability adder into a cordic module in DBPSK demodulation to solve the problem of excessive overhead of the existing DBPSK demodulation; specifically, the method comprises the following steps: replacing a traditional adder in the cordic module by a probability adder; considering that a plurality of iterative operations are required in the cordic module, and the problem of time delay can occur due to high clock frequency required when the probability adder is used, the invention introduces a small-capacity lookup table to reduce the iterative times in the cordic algorithm, thereby reducing the problem of time delay caused by the use of the probability adder; specifically, the method comprises the following steps:

the cordic module further comprises: the device comprises a ROM lookup table, an iterative operation module and a correction module, wherein the ROM lookup table is used for storing the previous N/3 times of iterative operation results, the iterative operation module comprises a probability adder and a shift register, and if the current iterative times i are less than or equal to N/3, the iterative results stored in the ROM lookup table are obtained through the ROM lookup table address; if the current iteration number i is larger than N/3, an N/3 th iteration result is found in a ROM lookup table, and a probability adder and a shift register are used for performing i-N/3 times of iteration operation; and the correction module corrects the current iteration result by adopting an optimal consistent approximation method.

The result of the first N/3 times of iterative operation stored in the ROM lookup table is calculated by a traditional cordic algorithm.

Said N is less than or equal to 16; the ROM lookup table maximum address is less than or equal to 63.

The invention has the beneficial effects that: the small-capacity lookup table is combined with the probability adder to be introduced into the DBPSK demodulator hardware, the probability adder has the advantage of low cost, the small-capacity lookup table can help solve the problem of time delay caused by the use of the probability adder, and the time delay and cost of the DBPSK demodulator can be optimized by effectively combining the small-capacity lookup table and the probability adder.

Drawings

FIG. 1 is a cordic hardware implementation based on a small ROM lookup table in combination with a probability adder;

FIG. 2 is a functional block diagram of a small ROM look-up table storage;

fig. 3 is a low-delay and low-overhead hardware design of a DBPSK demodulator according to the present invention.

Detailed Description

In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.

The invention relates to a DBPSK demodulator design for realizing low time delay and low cost based on a small-capacity lookup table and a probability adder, wherein a cordic algorithm is commonly used for solving phases in DBPSK demodulation, and the cordic algorithm can calculate square roots, sine and cosine, a mode and phases and complete coordinate transformation through steps of shifting, adding and subtracting and the like, and is easy to realize in VLSI (very large scale integration) devices such as FPGA (field programmable gate array) and the like.

The cordic module introducing the probability adder into the DBPSK demodulation can help to save resource occupation, but the probability adder has higher clock requirement, and each clock processing n bits needs 2ⁿClock period, and a cordic module in the DBPSK demodulator needs to use a large number of adders, so using the probabilistic adder can help to save resources and reduce overhead. However, in the cordic module, a plurality of iterations are required, and when the probabilistic adder is used, the required clock frequency is high, and a delay problem occurs, so that the delay problem needs to be solved by considering to reduce the number of input data bits or reduce the number of iterations as much as possible.

As shown in FIG. 1, the cordic module is implemented by using a small-capacity ROM lookup table in combination with a probability adder, and the invention introduces the small-capacity ROM lookup table to help reduce the number of iterations in the cordic algorithm, thereby reducing the number of iterations in the case of using the probability adderConsidering the limitation of the angle of the input signal to 0, pi/4 when performing N iterations]Within the range, the result x of the first N/3 times of iterative operation_i,y_i,z_i(i<N/3) is stored in a ROM look-up table.

The iteration number N is generally not more than 16, the data stored in the table is the result of the initial iteration operation of not more than 6 times, therefore, the maximum address required by the small-capacity ROM lookup table is not more than 2⁰+2¹+2²+2³+2⁴+2⁵＝63。

And the rest iterative operation uses a probability adder to realize addition operation, when the iteration times are more than N/3 times, the probability adder can be used to realize the iterative operation, and finally, the optimal consistent approximation method is used for result correction.

As shown in FIG. 2, a storage principle block diagram of a small-capacity ROM lookup table is shown, the invention adopts a traditional cordic algorithm to calculate an operation result of iteration times i < ═ N/3, converts the previous N/3 iteration operation result into a probability domain and stores the result into the ROM lookup table, when the iteration times of inputting x, y and z are less than N/3, the result stored in the ROM lookup table can be obtained through the ROM lookup table address, and when i > N/3, the address of the N/3 th iteration result is found in the lookup table, thereby realizing the i-N/3 iteration operation by using a probability adder and a shift register.

Applying the cordic module to DBPSK demodulation, as shown in fig. 3, performing shaping filtering on the modulated signal, sending the filtered signal to the cordic module to solve the phase of the signal, where the formula of the cordic solution phase is as follows:

x_i+1＝x_i-d_iy_i2^-i

y_i+1＝y_i+d_ix_i2^-i

z_i+1＝z_i-d_iθ_i

x, y represent the abscissa and ordinate of the input signal in rectangular coordinates, z represents the initial phase, z represents the phase_i+1Representing the final phase after the iteration is completed, d_iRepresenting the direction of rotation, taking +1 to represent cisAnd the hour hand, taking-1 to represent the anticlockwise, and storing the first N/3 times of iteration results x, y and z in a ROM lookup table.

Then x is put_i,y_i,z_i(i<N/3) is sent into subsequent iteration, the subsequent iteration is completed by using a probability adder and a shift register, and the design of the probability adder mainly comprises forward conversion, a calculation unit and backward conversion. Finally, the result is corrected, so as to obtain the accurate signal phase p ═ z_i+1。

And sending the phase result into a difference module for phase difference, firstly obtaining an absolute value | p | of the phase, then judging the difference phase, if the phase is greater than 90 degrees, judging the output to be 1, otherwise, judging the output to be 0, and finally obtaining the demodulated baseband signal.

In summary, the invention uses a small-capacity lookup table and a probability calculation combined manner to realize a low-delay and low-overhead DBPSK demodulator, and introduces a probability adder to help reduce overhead, but the probability adder needs a larger clock period, and meanwhile, a cordic module in demodulation needs a large amount of iterative operations to have a delay problem, so that the time has an obvious disadvantage, and the small-capacity lookup table can help solve the delay problem to a certain extent, and the effective combination of the small-capacity lookup table and the probability calculation can help the DBPSK demodulator reduce overhead and delay.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.