阅读说明：本技术 垂直存储器设备 (Vertical memory device ) 是由 韩玉辉 于 2019-08-14 设计创作，主要内容包括：本公开内容的各方面提供了半导体设备。该半导体设备包括：衬底、多个栅极层和多个绝缘层。多个栅极层和多个绝缘层交替地堆叠在衬底的第一区之上,并以阶梯台阶形式堆叠在衬底的第二区之上。半导体设备还包括：布置在第一区之上并穿过多个栅极层和多个绝缘层的沟道结构。该沟道结构和多个栅极层以串联配置方式形成晶体管的叠层,其中多个栅极层是用于晶体管的叠层的多个栅极。该半导体设备还包括：穿过阶梯台阶形式的第一阶梯区布置的第一虚设沟道结构、穿过相邻于第一阶梯区的阶梯台阶形式的第二阶梯区布置的第二虚设沟道结构,以及布置在第一阶梯区和第二阶梯区之间的边界处的第三虚设沟道结构。(Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes: the semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. A plurality of gate layers and a plurality of insulating layers are alternately stacked over a first region of a substrate and stacked in a stepped fashion over a second region of the substrate. The semiconductor device further includes: a channel structure disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration, wherein the plurality of gate layers are a plurality of gates for the stack of transistors. The semiconductor device further includes: the semiconductor device includes a first dummy channel structure arranged through a first terrace region in the form of a terrace step, a second dummy channel structure arranged through a second terrace region in the form of a terrace step adjacent to the first terrace region, and a third dummy channel structure arranged at a boundary between the first and second terrace regions.)

1. A semiconductor device, comprising:

a substrate;

a plurality of gate layers and a plurality of insulating layers alternately stacked over the first region of the substrate, the plurality of gate layers and the plurality of insulating layers being stacked in a stepped step form over the second region of the substrate;

a channel structure disposed over the first region and through the plurality of gate layers and the plurality of insulating layers, and the channel structure and the plurality of gate layers form a stack of transistors in a series configuration, wherein the plurality of gate layers are a plurality of gates for the stack of transistors;

a first dummy channel structure arranged through a first stepped region in the form of the stepped step;

a second dummy channel structure arranged through a second stair-step region of the stair-step formation adjacent to the first stair-step region; and

a third dummy channel structure disposed at a boundary between the first and second stepped regions.

2. The semiconductor device of claim 1, further comprising:

a fourth dummy channel structure arranged through the first stepped region in the form of the stepped step; and

a fifth virtually provided channel structure arranged through the second stepped region in the form of the stepped step, wherein

The first dummy channel structure and the second dummy channel structure are arranged in a first row,

the fourth dummy channel structure and the fifth dummy channel structure are arranged in a second row, and

the third dummy channel structure is disposed between the first row and the second row.

3. The semiconductor device of claim 1, further comprising:

a first contact structure disposed over the first stepped region at a distance from the third dummy channel structure that is greater than a distance between the first dummy channel structure and the first contact structure; and

a second contact structure disposed over the second stepped region at a distance from the third dummy channel structure that is greater than a distance between the second dummy channel structure and the second contact structure.

4. The semiconductor device of claim 3, wherein the first and second contact structures are conductively connected to first and second gate layers, respectively, of the plurality of gate layers.

5. The semiconductor device of claim 3, wherein the third dummy channel structure is disposed between the first contact structure and the second contact structure.

6. The semiconductor device of claim 3, wherein a minimum distance between each dummy channel structure and each contact structure is greater than or equal to a first limit.

7. The semiconductor device of claim 1, wherein a maximum distance between two adjacent dummy channel structures is less than or equal to a second limit.

8. The semiconductor device of claim 1, wherein the channel structure and the third dummy channel structure are formed of a same material.

9. The semiconductor device of claim 1, wherein the third dummy channel structure has a circular shape.

10. A method of manufacturing a semiconductor device, comprising:

alternately stacking a plurality of dummy gate layers and a plurality of insulating layers over a first region and a second region of a substrate of the semiconductor device;

forming the stacked dummy gate layer and insulating layer in a stepped-step form over the second region of the substrate; and

a channel structure formed over the first region of the substrate and a dummy channel structure over the second region of the substrate, the dummy channel structure comprising: a first dummy channel structure arranged through a first stair zone of the stair step form, a second dummy channel structure arranged through a second stair zone of the stair step form adjacent to the first stair zone, and a third dummy channel structure arranged at a boundary between the first stair zone and the second stair zone.

11. The method of claim 10, wherein the stair-step form of the stacked dummy gate layer and insulating layer over the second region is formed using a trim etch technique.

12. The method of claim 10, wherein the first and second dummy channel structures are adjacent to the boundary between the first and second step-zones.

13. The method of claim 10, further comprising:

replacing the plurality of dummy gate layers with a plurality of gate layers; and

forming a contact structure over the second region of the substrate to conductively connect the plurality of gate layers, the contact structure including a first contact structure and a second contact structure conductively connected to a first gate layer and a second gate layer, respectively, in the plurality of gate layers.

14. The method of claim 13, wherein the first contact structure is arranged over the first stepped region in the form of a stepped step at a distance from the third dummy channel structure that is greater than a distance between the first dummy channel structure and the first contact structure; and the second contact structure is arranged over the second stepped region in the form of a stepped step at a distance from the third dummy channel structure that is greater than the distance between the second dummy channel structure and the second contact structure.

15. The method of claim 13, wherein a minimum distance between each dummy channel structure and each contact structure is greater than or equal to a first limit.

16. The method of claim 10, wherein a maximum distance between two adjacent dummy channel structures is less than or equal to a second limit.

17. The method of claim 10, wherein the channel structure and the third dummy channel structure are formed of a same material.

18. The method of claim 10, wherein the third dummy channel structure has a circular shape.

19. A method for designing a layout of a semiconductor device, comprising:

arranging stacks of alternating gate layers and insulating layers in a first region and a second region of the layout, the stacks of alternating gate layers and insulating layers having a stepped step form in the second region;

arranging a first dummy channel structure through a first stair-step region in the form of the stair-step in the second region of the layout;

arranging a second dummy channel structure in the second region of the layout through a second stair-step region in the form of a stair-step adjacent to the first stair-step region; and

a third dummy channel structure disposed in the second region of the layout at a boundary between the first and second stepped regions.

20. The method of claim 19, further comprising:

arranging a channel structure through a stack of the alternating gate layers and insulating layers in the first region of the layout;

a first contact structure arranged in the first stepped region in the stepped step form and adjacent to the first dummy channel structure in the second region of the layout; and

a second contact structure arranged in the second stepped region in the stepped step form in the second region of the layout and adjacent to the second dummy channel structure.

Background

Vertical device technologies, such as three-dimensional (3D) NAND flash technology, can achieve higher data storage densities without requiring smaller memory cells. In some examples, a 3D NAND memory device includes a core region and a staircase region. The core region includes a stack of alternating gate layers and insulating layers. A stack of alternating gate layers and insulating layers is used to form a vertically stacked memory cell. The stair-step regions include respective gate layers in the form of stair-steps to facilitate forming contact structures to the respective gate layers. The contact structure is used to connect the driver circuitry to the corresponding gate layer for controlling the stacked memory cells.

SUMMARY

Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes: the semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are alternately stacked over the first region of the substrate and stacked in a stepped step form over the second region of the substrate. The semiconductor device further includes: a channel structure disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration, wherein the plurality of gate layers are a plurality of gates for the stack of transistors. The semiconductor device further includes: a first dummy channel structure arranged through a first stair-step region of the stair-step form, a second dummy channel structure arranged through a second stair-step region of the stair-step form adjacent to the first stair-step region, and a third dummy channel structure arranged at a boundary between the first stair-step region and the second stair-step region.

According to aspects of the present disclosure, the semiconductor apparatus further includes: a fourth dummy channel structure disposed through the first stepped region in the stepped step form, and a fifth dummy channel structure disposed through the second stepped region in the stepped step form. The first and second dummy channel structures are arranged in a first row, the fourth and fifth dummy channel structures are arranged in a second row, and the third dummy channel structure is arranged between the first and second rows.

According to aspects of the present disclosure, the semiconductor apparatus further includes: a first contact structure disposed over the first stepped region at a distance from the third dummy channel structure that is greater than a distance between the first dummy channel structure and the first contact structure; and a second contact structure disposed over the second stepped region at a distance from the third dummy channel structure that is greater than a distance between the second dummy channel structure and the second contact structure. The first and second contact structures are conductively connected to first and second gate layers, respectively, of the plurality of gate layers. The third dummy channel structure is disposed between the first contact structure and the second contact structure.

In some embodiments, a minimum distance between each dummy channel structure and each contact structure is greater than or equal to the first limit.

In some embodiments, the maximum distance between two adjacent dummy channel structures is less than or equal to the second limit.

In some embodiments, the channel structure and the third dummy channel structure are formed of the same material.

In some embodiments, the third dummy channel structure has a circular shape.

Aspects of the present disclosure provide methods of manufacturing semiconductor devices. The method alternately stacks a plurality of dummy gate layers and a plurality of insulating layers over a first region and a second region of a substrate of the semiconductor device, forms the stacked dummy gate layers and insulating layers in a stepped step form over the second region of the substrate, and forms a channel structure over the first region of the substrate and a dummy channel structure over the second region of the substrate. The dummy channel structure includes: a first dummy channel structure arranged through a first stair zone of the stair step form, a second dummy channel structure arranged through a second stair zone of the stair step form adjacent to the first stair zone, and a third dummy channel structure arranged at a boundary between the first stair zone and the second stair zone.

In some embodiments, the stair-step form of the stacked dummy gate layer and insulating layer over the second region is formed using a trim etch technique.

In some embodiments, the first dummy channel structure and the second dummy channel structure are adjacent to the boundary between the first stepped region and the second stepped region.

According to aspects of the present disclosure, the method further replaces the plurality of dummy gate layers with a plurality of gate layers and forms a contact structure over the second region of the substrate to conductively connect the plurality of gate layers. The contact structure includes a first contact structure and a second contact structure conductively connected to a first gate layer and a second gate layer, respectively, in the plurality of gate layers.

In some embodiments, the first contact structure is arranged over the first stepped region in the form of a stepped step at a distance from the third dummy channel structure that is greater than a distance between the first dummy channel structure and the first contact structure; and the second contact structure is arranged over the second stepped region in the form of a stepped step at a distance from the third dummy channel structure that is greater than the distance between the second dummy channel structure and the second contact structure.

In some embodiments, a minimum distance between each dummy channel structure and each contact structure is greater than or equal to the first limit.

In some embodiments, the maximum distance between two adjacent dummy channel structures is less than or equal to the second limit.

In some embodiments, the channel structure and the third dummy channel structure are formed of the same material.

In some embodiments, the third dummy channel structure has a circular shape.

Aspects of the present disclosure provide methods for designing a layout of a semiconductor device. The method arranges stacks of alternating gate layers and insulating layers in a first region and a second region of the layout. The stack of alternating gate layers and insulating layers has a stepped terrace form in the second region. The method also arranges, in the second region of the layout, a first dummy channel structure through a first stair-step region of the stair-step form, a second dummy channel structure through a second stair-step region of the stair-step form adjacent to the first stair-step region, and a third dummy channel structure at a boundary between the first stair-step region and the second stair-step region.

According to aspects of the present disclosure, the method arranges a channel structure through the stack of alternating gate layers and insulating layers in the first region of the layout. The method also arranges a first contact structure in the first stepped region of the stepped version and adjacent to the first dummy channel structure, and a second contact structure in the second stepped region of the stepped version and adjacent to the second dummy channel structure in the second region of the layout.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A and 1B illustrate horizontal and vertical cross-sectional views of a semiconductor device according to some embodiments of the present disclosure.

Fig. 2 shows a flowchart outlining an exemplary layout design process for fabricating semiconductors according to some embodiments of the present disclosure.

Fig. 3 illustrates an exemplary mask for fabricating a semiconductor device, according to some embodiments of the present disclosure.

Fig. 4 shows a flowchart outlining an exemplary manufacturing process for manufacturing a semiconductor device according to some embodiments of the present disclosure.

Fig. 5 illustrates a horizontal cross-sectional view of a semiconductor device during a manufacturing process, according to some embodiments of the present disclosure

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below … …," "below … …," "below," "above … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

According to aspects of the present disclosure, a vertical memory device (e.g., a 3D NAND memory) may include a core region over a first region of a substrate of the memory device. The core region is, for example, a stack of gate layers and insulating layers (e.g., alternating gate layers and insulating layers) over a first region of a substrate of the memory device. The stack of the gate layer and the insulating layer may extend to the second region of the substrate. The stack of the gate layer and the insulating layer over the second region of the substrate has a stair-step form and may also be referred to as a staircase-like region.

The vertical memory device further includes: a channel structure disposed over the first region. The channel structure may be one of a plurality of channel structures in the first region. The channel structure extends through the gate layer and the insulating layer to form a stack of transistors in a series configuration, wherein the gate layer is a gate of the stack of transistors. The stack of transistors forms a memory cell string of a vertical memory device. The memory cell string includes, for example, a plurality of memory cells, a string selection transistor, and a ground selection transistor arranged in series in a vertical direction with respect to a main surface of a substrate. Each memory cell may store data.

Various fabrication techniques (such as gate first fabrication techniques, gate last fabrication techniques, etc.) may be used to fabricate the vertical memory device. Gate-first fabrication techniques form the gate of a memory cell earlier than the channel structure of the memory cell. Gate-first fabrication techniques use a sacrificial layer (also referred to as a dummy gate layer) to facilitate formation of the channel structure of the memory cell and replace the sacrificial layer with the gate of the memory cell after formation of the channel structure. To replace the sacrificial layer with a gate, the sacrificial layer is removed and then a gate layer is formed. When the sacrificial layer is removed, the channel structure of the memory cells in the core region may provide support to prevent the core region from collapsing. Similar to the channel structures in the core region, the dummy channel structures in the staircase-like region may provide support to prevent the staircase-like region from collapsing when the sacrificial layer is removed, e.g., during or after removal of the sacrificial layer.

As the data storage density increases, the number of layers used in the stack of the gate layer and the insulating layer may increase, and thus the stack may be relatively thick. However, successfully forming dummy channel structures in thick film structures can be challenging. The dummy channel structures in the thick film structure may be under-etched due to etch loading effects (which is a relationship between the etch rate of the etch process and the exposed areas to be etched), and in some cases (e.g., when the dummy channel structures are in less dense areas), the dummy channel holes used to etch the dummy channel structures may not be fully open.

Aspects of the present disclosure provide a layout design of dummy channel structures in a staircase-like region. The layout design meets certain distance requirements to support the staircase-like region when the sacrificial gate is removed. In addition, the present disclosure provides techniques to increase the density of dummy channel structures in a layout design, for example, to mitigate the effects of etch loading effects when etching dummy channel holes for the dummy channel structures.

Fig. 1A illustrates a horizontal cross-sectional view and fig. 1B illustrates a vertical cross-sectional view of an exemplary semiconductor device 100, according to some embodiments of the present disclosure. The exemplary semiconductor device 100 includes a substrate 101 and circuitry formed on the substrate 101. The main surface of the substrate 101 extends in, for example, the X direction and the Y direction. The horizontal cross-section (e.g., the X-Y plane) is parallel to the major surface of the substrate 101, and the vertical cross-section (e.g., the X-Z plane) is perpendicular to the major surface of the substrate 101. FIG. 1A shows line B-B' used to produce the vertical cross-sectional view in FIG. 1B; while figure 1B shows line a-a' used to produce the horizontal cross-sectional view in figure 1A.

The exemplary semiconductor device 100 may be any suitable device, such as a memory circuit, a semiconductor chip (or die) having a memory circuit formed thereon, a semiconductor wafer having a plurality of semiconductor dies formed thereon, a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a package substrate, and so forth. The substrate 101 may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor may include Si, Ge, or SiGe. The substrate 101 may be a bulk wafer or an epitaxial layer.

In various embodiments, the exemplary semiconductor device 100 includes three-dimensional (3D) NAND memory circuitry formed on a substrate 101. The exemplary semiconductor device 100 may include other suitable circuitry (not shown), such as logic circuitry, power supply circuitry, etc., formed on the substrate 101 or other suitable substrate, and be suitably coupled with the 3D NAND memory circuitry. Typically, 3D NAND memory circuitry includes a memory array and peripheral circuitry (e.g., address decoders, drive circuits, sense amplifiers, etc.). The memory array is formed as an array of vertical strings of memory cells in core region 110. The peripheral circuitry is formed in a peripheral region (not shown). In addition to the core region 110 and the peripheral region, the exemplary semiconductor device 100 also includes a staircase-like region 120 in which contact structures to the gates of memory cells in the vertical string of memory cells are arranged. The gates of the memory cells in the vertical memory cell string correspond to the word lines of a NAND memory architecture.

In particular, in the example of fig. 1A and 1B, the core region 110 of the example semiconductor device 100 includes gate layers 105 (e.g., 105(a) -105(I)) and insulating layers 104 (e.g., 104(a) -104(I)) that are alternately stacked to form a stack of transistors. However, other orders or combinations of gate layers and insulating layers may be utilized.

In some examples, the stack of transistors includes a memory cell and a select transistor (such as a ground select transistor, a string select transistor, etc.). The gate layer 105 corresponds to a gate of a transistor. In one example, gate layer 105(a) corresponds to the gate of a ground select transistor, gate layer 105(I) corresponds to the gate of a string select transistor, and the other gate layers 105(B) -105(H) correspond to the gates of memory cells vertically stacked with the ground select transistor and the string select transistor. Gate layers 105(B) -105(H) may also be referred to as word lines in a memory architecture. Gate layer 105 may include one or more gate stack materials, such as a high dielectric constant (high-k) gate insulator layer, a Metal Gate (MG) electrode, and the like. The insulating layer 104 is made of an insulating material such as silicon nitride, silicon dioxide, or the like.

In the core region 110, a plurality of channel structures 111 (e.g., 111(a) -111(C)) are formed. In some embodiments, each channel structure 111 of the plurality of channel structures 111 has a pillar shape extending in a Z-direction perpendicular to a direction of the main surface of the substrate 101. The plurality of channel structures 111 may be arranged apart from each other along the X-direction and the Y-direction, and may be arranged in some appropriate array shape, such as a matrix array shape along the X-direction and the Y-direction, a zigzag array shape along the X-or Y-direction, a honeycomb (e.g., hexagonal) array shape, or the like. In some embodiments, each channel structure 111 of the plurality of channel structures 111 has a circular shape in the X-Y plane and a pillar shape in the X-Z plane.

In some embodiments, each channel structure 111 of the plurality of channel structures 111 is formed from a plurality of materials. For example, each channel structure 111 of the plurality of channel structures 111 includes a gate dielectric layer 112, a semiconductor layer 113, and an insulating layer 114. These materials may also have a circular shape in the X-Y plane and extend in the Z direction. The gate dielectric layer 112 is formed on sidewalls of the channel structure 111, and includes a plurality of layers, such as a tunneling insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), and a blocking insulating layer (e.g., silicon oxide) sequentially stacked from the sidewalls. In one example, the gate dielectric layer 112 has an oxide-nitride-oxide (ONO) stack structure. The semiconductor layer 113 may be any suitable semiconductor material, such as polysilicon or monocrystalline silicon, and the semiconductor material may be undoped or may include p-type or n-type dopants. The insulating layer 114 is formed of an insulating material, such as silicon oxide and/or silicon nitride, and/or may be formed as an air gap.

Channel structure 111 includes other suitable components. For example, each channel structure 111 includes a first end structure 115 and a second end structure 116. In some embodiments, the first end structure 115 and the second end structure 116 are formed of any suitable semiconductor material (such as polysilicon or monocrystalline silicon), and the semiconductor material may be undoped or may include p-type or n-type dopants. In some examples, the first terminal structure 115 is a source of a ground select transistor and the second terminal structure 116 is a drain of a string select transistor.

Further, in the example of fig. 1A and 1B, the stack of the gate layer 105 and the insulating layer 104 extends into the staircase-like region 120 of the example semiconductor device 100. Stair-step region 120 includes a plurality of stair-step regions (e.g., stair-step regions 140, 150, and 160) to facilitate forming a plurality of contact structures (e.g., contact structures 145, 155, and 165) with gate layer 105. The plurality of contact structures are used to connect drive circuitry, such as word line drive circuitry, ground select drive circuitry, string select drive circuitry, etc., in peripheral circuitry of the respective gates of the transistors in the stack.

It is noted that the stepped regions 140, 150, and 160 may include the same or different number of stacked gate and insulating layers. In an example, the stepped regions 140, 150, and 160 include the same number of stacked gate and insulating layers. In another example, the staircase regions 140 and 150 comprise the same number of stacked gate and insulating layers, but the staircase region 160 comprises a different number of stacked gate and insulating layers. In another example, the staircase regions 140 and 160 comprise the same number of stacked gate and insulating layers, but the staircase region 150 comprises a different number of stacked gate and insulating layers. In the example of fig. 1A and 1B, the ledge regions 150 and 160 include different numbers of stacked gate and insulator layers, but the ledge region 140 is not limited to including the same or different numbers of stacked gate and insulator layers.

In some examples, the top of the stack is selectively removed at different step areas of the stair-like zones 120. In the example of fig. 1A and 1B, at the step region 150, the top of the stack over the gate layer 105(D) is removed; at the step region 160, the top of the stack over the gate layer 105(C) is removed. Accordingly, the contact holes for forming the contact structures 155 and 165 may be formed through a single etching process. The etching process is configured to stop at the respective top gate layer of each of the stepped regions, for example. That is, the contact hole for the stepped region 150 stops at the gate layer 105 (D); and the contact hole for the stepped region 160 stops at the gate layer 105 (C). When the contact holes are filled with metal to form contact structures 155 and 165, the contact structures 155 are conductively connected with the gate layer 105(D), and the contact structures 165 are conductively connected with the gate layer 105 (C).

According to aspects of the present disclosure, a plurality of dummy channel structures are formed through different ones of the staircase regions 120 to support the staircase regions 120 from collapsing when the sacrificial layer is removed. Referring to fig. 1A, dummy channel structures 141 (e.g., dummy channel structures 141(a) and 141(B)) are formed around contact structure 145 through stepped region 140, dummy channel structures 151 (e.g., dummy channel structures 151(a) and 151(B)) are formed around contact structure 155 through stepped region 150, and dummy channel structures 161 (e.g., dummy channel structures 161(a) and 161(B)) are formed around contact structure 165 through stepped region 160.

In some embodiments, the layout of the dummy channel structures and the contact structures meet certain distance requirements. In an embodiment, a minimum distance between a contact structure and a dummy channel structure adjacent to the contact structure is greater than or equal to the first distance. The first distance may be predetermined to prevent overlap between the dummy channel structure and an adjacent contact structure. In the example of fig. 1A and 1B, the minimum distance between the contact structure 155 and the dummy channel structure 151(a) (or the dummy channel structure 151(B)) is greater than or equal to the distance D1.

In some related examples, to avoid underetching of the dummy channel structures 141, 151, 161, etc. in the staircase-like region 120, the hole area (e.g., corresponding to the diameter) of the dummy channel hole is enlarged. However, when the distance between the contact structure and the dummy channel structure adjacent to the contact structure is maintained at a constant distance (e.g., the allowed minimum distance D1), the enlarged dummy channel hole region of the dummy channel structure may result in a smaller contact hole region of the contact structure and, therefore, a higher contact resistance and a greater risk of breakdown. For example, the distance between the dummy channel structure 151(a) and the contact structure 155 is maintained at the allowed minimum distance D1, and thus enlarging the dummy channel hole area of the dummy channel structure 151(a) may result in a smaller contact hole area of the contact structure 155.

According to aspects of the present disclosure, in addition to dummy channel structures around the contact structures, additional dummy channel structures are disposed through the staircase-like region to support the staircase-like region and avoid underetching due to etch loading effects.

In some embodiments, an additional dummy channel structure is disposed between two adjacent stair-step regions of the stair-step regions. In an embodiment, the first and second existing dummy channel structures are arranged through first and second stair step regions, respectively, of the stair-step region, and the further dummy channel structure is arranged at a boundary between the first and second stair step regions. For example, additional dummy channel structures intersect the boundary. The second stepped region is adjacent to the first stepped region in the form of a step of a staircase-like region.

In the example of fig. 1A and 1B, a first existing dummy channel structure 151(a) is disposed through a first stair-step region 150, a second existing dummy channel structure 161(a) is disposed through a second stair-step region 160 adjacent to the first stair-step region 150, and an additional dummy channel structure 171(a) is disposed at a boundary between the first stair-step region 150 and the second stair-step region 160. Thus, by adding additional dummy channel structures, the density of dummy channel structures in the stair-step region may be increased without shrinking the contact hole area of the contact structure in the stair-step region.

However, it is noted that due to process variations, the additional dummy channel structure may not be exactly at the boundary between two different step regions. In processes with large process variations, additional dummy channel structures may be disposed closer to one of the two different step regions. In some embodiments, the additional dummy channel structure is disposed in one of the two different stair step regions, but within a predetermined distance of the boundary.

In some embodiments, additional dummy channel structures are alternately arranged in a row between the first and second rows of existing dummy channel structures in the staircase-like region with the contact structures. In an embodiment, the first and second rows of existing dummy channel structures are aligned with each other, and the alternating further rows of dummy channel structures and contact structures are arranged in an offset manner from the first and/or second rows of existing dummy channel structures.

In the example of fig. 1A and 1B, the first row of dummy channel structures is a row including existing dummy channel structures 141(a) and 151(a), and the second row of dummy channel structures is a row including existing dummy channel structures 141(B) and 151 (B). Accordingly, an additional dummy channel structure 171(B) may be disposed between the two contact structures 145 and 155. It is noted that if the stair regions 140 and 150 are in the same level of stair steps, the additional dummy channel structure 171(B) is arranged in the same level as the existing dummy channel structures 141 and 151. However, if the stepped regions 140 and 150 are different levels of stepped steps, additional dummy channel structures 171(B) may be arranged at the boundary between the stepped regions 140 and 150.

In fig. 1A, the existing dummy channel structures 141, 151, and 161 are arranged to have a symmetrical pattern with respect to the contact structures 145, 155, and 165. It is noted that the existing dummy channel structures 141, 151, and 161, etc. may be arranged to have a symmetrical pattern or an asymmetrical pattern with respect to the contact structures 145, 155, and 165. Furthermore, each contact structure has four adjacent existing dummy channel structures in fig. 1A. However, the number of adjacent channel structures for a contact structure is not limited in this disclosure as long as the maximum persistence distance requirement is met for the dummy channel structure. The maximum persistence distance requirement limits the maximum distance between two dummy channel structures to support the staircase-like region within the maximum persistence distance. In an example, the maximum persistence distance requirement requires that the maximum distance between two dummy channel structures be less than or equal to a second limit. The second limit may be predetermined to ensure adequate support without collapsing. In the example of fig. 1A and 1B, the maximum distance between two dummy channel structures is D2. Further, the shape of the dummy channel hole is not limited in the present disclosure, although the dummy channel hole in fig. 1A has a circular shape.

According to aspects of the present disclosure, a gate last process is used to form the exemplary semiconductor device 100, and dummy channel structures (e.g., dummy channel structures 151, 161, and 171) are formed in the staircase-like region 120 to support the staircase-like region 120. During the gate last process, a sacrificial layer (not shown in fig. 1B and to be shown in fig. 5) is initially used instead of the gate layer 105, so the initial stack comprises the sacrificial layer and the insulating layer 104 alternately deposited on the substrate 101 in the core region 110 and the staircase region 120. Further, the step steps are formed in the stair-step zones 120, for example, by selectively removing the tops of the stacks at the different step steps. In one example, the step-step is formed by a trim and etch process. Then, a channel structure 111 is formed in the core region 110, and dummy channel structures 151, 161, and 171 are formed in the staircase-like region 120.

In addition, the sacrificial layer is replaced with the gate layer 105 to form the gate of the transistor in the core region 110. In one example, the Gate Line Slits (GLS) are etched as trenches in the stack. An etchant to the sacrificial layer is applied via GLS to remove the sacrificial layer. In one example, the sacrificial layer is made of silicon nitride and the thermal sulfuric acid (H)₂SO₄) Applied via GLS to remove the sacrificial layer. Further, via the GLS, the gate of the transistor in the core region is formed. In one example, the gate is formed from a high-k dielectric layer, a glue layer, and a metal layer. The high-k dielectric layer may comprise any suitable material that provides a relatively large dielectric constant (such as hafnium oxide (HfO)₂) Hafnium silicon oxide (HfSiO)₄) Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al)₂O₃) Lanthanum oxide (La)₂O₃) Tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Zirconium oxide (ZrO)₂) Strontium titanium oxide (SrTiO)₃) Zirconium oxide silicon (ZrSiO)₄) Hafnium zirconium oxide (HfZrO)₄) Etc.). The glue layer may include refractory metals such as titanium (Ti), tantalum (Ta) and their nitrides such as TiN, TaN, W2N, TiSiN, TaSiN, etc. The metal layer includes a metal having high conductivity, such as tungsten (W), copper (Cu), or the like.

Note that when the sacrificial layer is removed, the channel structure 111 supports the stack of insulating layers 104 in the core region 110, and the dummy channel structures 151, 161, and 171 and the like support the stack of insulating layers 104 in the staircase-like region 120.

In an embodiment, the dummy channel structures 151, 161, and 171, etc. are formed together with the channel structure 111, and thus, the dummy channel structures 151, 161, and 171, etc. are formed of the same material as the channel structure 111. In another embodiment, the dummy channel structures 151, 161, 171, etc. are formed of a different material than the channel structure 111, e.g., using a mask layer, to distinguish the core region 110 from the staircase-like region 120.

Fig. 2 shows a flowchart outlining an exemplary process 200 according to an embodiment of the present disclosure. Process 200 is used to generate a layout design for a semiconductor device (e.g., a 3D NAND memory device) and then manufacture the semiconductor device according to the layout design. Process 200 begins and continues to S210.

At S210, the process 200 arranges a stack of alternating gate layers and insulating layers in a first region and a second region of a layout. A stack of alternating gate layers and insulating layers is arranged in a stepped formation in the second region.

In the example of fig. 1A and 1B, a stack of alternating gate layers 105 and insulating layers 104 is arranged in a first region 110 and a second region 120. The second region 120 has a stepped step form.

At S220, the process 200 arranges a channel structure through a stack of alternating gate layers and insulating layers in a first region of a layout. The channel structure and the gate layer form a stack of transistors, wherein the gate layer is a gate of the transistor. The stack of transistors may be used as a memory cell of a memory device to store data. The stack of transistors further comprises a ground select transistor, a string select transistor, etc.

In the example of fig. 1A and 1B, a channel structure 111 is arranged in the first region 110 through a stack of alternating gate layers 105 and insulating layers 104.

At S230, the process 200 arranges a first contact structure in a first stair step region in the form of a stair step in a second region of the layout to connect to the first gate layer, and arranges a second contact structure in a second stair step region in the form of a stair step to connect to the second gate layer. The second stepped region is adjacent to the first stepped region.

In the example of fig. 1A and 1B, a first contact structure 155 is arranged in the first stepped region 150 to connect to the first gate layer 105(D), and a second contact structure 165 is arranged in the second stepped region 160 to connect to the second gate layer 105 (C). The second stepped region 160 is adjacent to the first stepped region 150.

At a240, the process 200 arranges a first dummy channel structure through the first step region and adjacent to the first contact structure and a second dummy channel structure through the second step region and adjacent to the second contact structure in a second region of the layout. In an embodiment, a minimum distance between one of the dummy channel structures and one of the contact structures adjacent to the one of the dummy channel structures is greater than or equal to the first limit. Further, a maximum distance between two of the dummy channel structures is less than or equal to the second limit. The first limit and the second limit may be predetermined according to process rules.

In the example of fig. 1A and 1B, a first dummy channel structure 151(a) is disposed through the first stepped region 150 and adjacent to the first contact structure 155, and a second dummy channel structure 161(a) is disposed through the second stepped region 160 and adjacent to the second contact structure 165. The minimum distance between the first contact structure 155 and the first dummy channel structure 151(a) is D1. The maximum distance between the first contact structures 151(a) and 151(B) is D2. Both D1 and D2 are predetermined according to process rules.

At S250, the process 200 arranges a third dummy channel structure at a boundary between the first and second stepped regions in the second region of the layout.

In the example of fig. 1A and 1B, the third dummy channel structure 171(a) is arranged at a boundary between the first stepped region 150 and the second stepped region 160. As described above, it is to be noted that the third dummy channel may not be arranged exactly at the boundary due to a large process variation. Alternatively, the third dummy channel may be disposed closer to one of the two stepped regions.

At S260, the process 200 generates a layout file according to the arranged structure. The layout may have multiple layers, such as a channel layer for defining channel structures in the first region and dummy channel structures in the second region, a contact layer for defining contact structures in the second region, and so on. The process 200 then terminates.

In some embodiments, the layout file is used to manufacture a semiconductor device (such as exemplary semiconductor device 100). In one example, a set of masks is generated from the layout file. The set of masks is then used in a gate last process to fabricate the exemplary semiconductor device 100.

Fig. 3 illustrates an exemplary mask 300 according to some embodiments of the present disclosure. The mask 300 is generated according to the channel layer in the layout. Mask 300 includes a core region 310 corresponding to core region 110 and a staircase-like region 320 corresponding to staircase-like region 120. The core region 310 includes a plurality of circular shapes 311 that define the shape of the channel holes and channel structures. The stair-step regions 320 include a plurality of circular shapes 321 that define the shape of the dummy channel holes and dummy channel structures. The mask 300 is used to create channel holes in the core region 110 and dummy channel holes in the staircase-like region 120.

Fig. 4 shows a flowchart outlining an exemplary process 400 according to some embodiments of the present disclosure. Process 400 is used to fabricate a semiconductor device during a gate last process according to a set of masks. Process 400 begins and continues to S410.

At S410, the process 400 stacks a plurality of dummy gate layers and a plurality of insulating layers over a first region and a second region of a substrate of a semiconductor device. In some embodiments, the plurality of dummy gate layers and the plurality of insulating layers are alternately stacked.

At S420, the process 400 forms the stacked dummy gate layer and insulating layer into a stair step form over a second region of the substrate. In an embodiment, a trim etch technique is used to form a stepped form of the stacked dummy gate layer and insulating layer over the second region.

At S430, the process 400 forms a channel structure over a first region of the substrate and a dummy channel structure over a second region of the substrate. The dummy channel structure includes a first dummy channel structure arranged through a first stair step region in the form of a stair step, a second dummy channel structure arranged through a second stair step region in the form of a stair step adjacent to the first stair step region, and a third dummy channel structure arranged at a boundary between the first stair step region and the second stair step region. The first and second stepped regions may correspond to different levels of stepped terraces. The process 400 then terminates.

In an embodiment, the first dummy channel structure and the second dummy channel structure are disposed adjacent to a boundary between the first terrace region and the second terrace region.

In some embodiments, the process 400 replaces the plurality of dummy gate layers with a plurality of gate layers and forms a contact structure over the second region of the substrate to conductively connect the plurality of gate layers.

In an embodiment, the contact structure includes a first contact structure and a second contact structure conductively coupled to a first gate layer and a second gate layer, respectively, of the plurality of gate layers.

In an embodiment, a first contact structure is disposed over a first stepped region in the form of a stepped step and adjacent to the first dummy channel structure, and a second contact structure is disposed over a second stepped region in the form of a stepped step and adjacent to the second dummy channel structure.

In an embodiment, a minimum distance between each dummy channel structure and each contact structure is greater than or equal to the first limit.

In an embodiment, a maximum distance between two adjacent dummy channel structures is less than or equal to the second limit.

In one embodiment, the channel structure and the dummy channel structure are formed of the same material.

In an embodiment, one of the dummy channel structures is formed to have a circular shape.

Fig. 5 illustrates a horizontal cross-sectional view of an exemplary semiconductor device 100 during a gate last process after a channel etch process, in accordance with some embodiments of the present disclosure. In an example, the trench etch process generates a channel hole and a dummy channel hole according to the mask 300. The horizontal cross-sectional view is produced according to line a-a' in fig. 1B.

During the gate last process, a sacrificial layer (also referred to as a dummy gate layer) 503 (e.g., 503(a) -503(I)) is initially used in place of the gate layer 105, and thus the initial stack includes the sacrificial layer 503 and the insulating layer 104 alternately deposited on the substrate 101 in the core region 110 and the staircase region 120. Further, the step steps are formed in the stair-step zones 120, for example, by selectively removing the tops of the stacks at the different step steps. In one example, the planarization process is suitably performed to result in a relatively flat surface.

Then, photolithography techniques may be used to define a pattern in the photoresist and/or hard mask layer according to the mask 300, and etching techniques may be used to transfer the pattern into the stack of sacrificial layer 503 and insulating layer 105. Accordingly, the channel hole 311 is formed in the core region 110, and the dummy channel holes 551, 561, and 571 are formed in the staircase-like region 120.

Thereafter, a channel structure is formed in the channel hole, and a dummy channel structure is formed in the dummy channel hole. In some embodiments, the dummy channel structure may be formed with the channel structure, and thus the dummy channel structure is formed of the same material as the channel structure. In some embodiments, the dummy channel structure is formed of a different material than the channel structure.

In one example, channel structure 111 and dummy channel structures 151, 161, and 171 are formed. Channel structures 111 are formed in the core region 110, and dummy channel structures 151, 161, and 171 are formed in the staircase-like region 120. In some embodiments, dummy channel structures 151, 161, and 171 may be formed of the same material as channel structure 111. In some embodiments, dummy channel structures 151, 161, and 171 may be formed of a different material than channel structure 111.

In some embodiments, a Gate Line Slit (GLS) is used to replace the sacrificial layer 503 with the gate layer 105. In one example, the GLS is etched as a trench in the stack. An etchant to the sacrificial layer is applied via GLS to remove the sacrificial layer. The sacrificial layer is made of silicon nitride and hot sulfuric acid (H)₂SO₄) Applied via GLS to remove the sacrificial layer. Further, a gate stack of the transistor in the core region is formed via the GLS. In one exampleThe gate stack is formed from a high-k dielectric layer, a glue layer, and a metal layer. The high-k dielectric layer may comprise any suitable material that provides a relatively large dielectric constant (such as hafnium oxide (HfO)₂) Hafnium silicon oxide (HfSiO)₄) Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al)₂O₃) Lanthanum oxide (La)₂O₃) Tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Zirconium oxide (ZrO)₂) Strontium titanium oxide (SrTiO)₃) Zirconium oxide silicon (ZrSiO)₄) Hafnium zirconium oxide (HfZrO)₄) Etc.). The glue layer may include refractory metals such as titanium (Ti), tantalum (Ta) and their nitrides such as TiN, TaN, W2N, TiSiN, TaSiN, etc. The metal layer includes a metal having high conductivity such as tungsten (W), copper (Cu), or the like.

The gate last process continues to fill the GLS, for example with a spacer material (e.g., silicon oxide) and a common source material (e.g., tungsten) to form contact structures 145, 155, and 165, etc., and to form metal traces, etc.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.