阅读说明：本技术 通过时间交错而无需归零的高频数模转换 (High frequency digital to analog conversion without return to zero by time interleaving ) 是由 Y·阿曾科特 N·G·贾亚玛兰 于 2018-06-06 设计创作，主要内容包括：交错式DAC利用一组正子DAC和一组负子DAC并行转换数字输入,而无需归零。对于每个数字输入,正子DAC执行转换,并且驱动其模拟输出达N/f<Sub>s</Sub>的持续时间；而负子DAC执行转换,并且以1/f<Sub>s</Sub>的延迟驱动其模拟输出达(N-1)/f<Sub>s</Sub>的持续时间。通过组合来自两组子DAC的输出,当在组合输出处不再需要来自正子DAC的输出时,可以将其有效地去除。结果,组合模拟信号使每个数据点仅有效达T的持续时间,从而达到期望的数据转换速度f<Sub>s</Sub>。(The interleaved DAC converts the digital input in parallel using a set of positive sub-DACs and a set of negative sub-DACs without return-to-zero. For each digital input, the positive sub-DAC performs the conversion and drives its analog output to N/f s The duration of (d); while the negative sub-DAC performs the conversion and at 1/f s Is driven by the delay of (N-1)/f s The duration of (c). By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC can be effectively removed when it is no longer needed at the combined output. As a result, the combined analog signals cause each data point to be valid only for a duration of T, thereby achieving the desired data conversion speed f s 。)

1. A method of digital to analog signal conversion, the method comprising:

converting a plurality of digital inputs in parallel into a first analog output by using a set of first clock signals of a first frequency, respectively;

in parallel with the converting to the first analog output, converting the plurality of digital inputs in parallel to a second analog output by using a set of second clock signals respectively at a second frequency different from the first frequency,

wherein the converting comprises: converting respective digital inputs to a first analog output and a second analog output, the second analog output being an opposite value of the first analog output; and

subtracting the second analog output from the first analog output to sequentially output the first analog output as a composite analog signal.

2. The method of claim 1, wherein first clock signals for converting each two consecutive ones of the plurality of digital inputs to a corresponding first analog output are shifted from each other by a first phase, wherein second clock signals for converting each two consecutive ones of the plurality of digital inputs to a corresponding second analog output are shifted from each other by the first phase.

3. The method of claim 2, wherein a first clock signal and a second clock signal are used to convert the respective digital inputs to the first analog output and the second analog output, respectively, and wherein additionally the first clock signal and the second clock signal are shifted from each other by the first phase.

4. The method of claim 1, a ratio of the first frequency to the second frequency is (N-1)/N, where N is an integer greater than 1.

5. According to the claimsThe method of claim 2, wherein the first frequency is equal to f_s/N, wherein the second frequency is equal to f_sV (N-1), wherein f_sEqual to the effective frequency of the composite analog signal into which the plurality of digital inputs are sequentially converted, wherein the first phase is equal to 1/f_sAnd wherein additionally N is an integer greater than 1.

6. The method of claim 5, wherein each of the first analog outputs remains for N/f_sAnd wherein additionally each of the second analog outputs remains for (N-1)/f_sThe duration of (c).

7. The method of claim 6, wherein the converting the plurality of digital inputs to the first analog output comprises: converting N digital inputs in parallel; and wherein said converting said plurality of digital inputs to said second analog output comprises: n-1 digital inputs are converted in parallel.

8. The method of claim 1, further comprising:

demultiplexing the digital signal into a further plurality of digital inputs; and

adding respective delays to the further plurality of digital inputs to generate the plurality of digital inputs.

9. A digital-to-analog converter (DAC), comprising:

a set of first sub-DACs operable to be coupled to a set of first clock signals of a first frequency and configured to convert a plurality of digital inputs into a first analog output, wherein the first clock signals are shifted from each other by a first phase, the first clock signals for converting each two consecutive digital inputs of the plurality of digital inputs into a corresponding first analog output;

a set of second sub-DACs operable to be coupled to a set of second clock signals at a second frequency and configured to convert the plurality of digital inputs to a second analog output in parallel with the plurality of digital outputs being converted to the first analog output, wherein the second frequency is different from the first frequency, and wherein additionally second clock signals for converting each two consecutive ones of the plurality of digital inputs to a corresponding second analog output are shifted from each other by the first phase; and

a combined output configured to: combining the first analog output and the second analog output; and outputs a synthesized analog signal.

10. The DAC of claim 9, wherein a first sub-DAC of the set of first sub-DACs is configured to convert a respective digital input of the plurality of digital inputs to a first analog output, wherein a second sub-DAC of the set of second sub-DACs is configured to convert the respective digital input to a second analog output, and wherein further, a first clock signal coupled to the first sub-DAC and a second clock signal coupled to the second sub-DAC are configured to be shifted from each other by the first phase.

11. The DAC of claim 10, wherein the first and second analog outputs have the same magnitude and opposite sign, and wherein the combined output is configured to sum the first and second analog outputs.

12. The DAC of claim 9, the ratio of the first frequency to the second frequency is (N-1)/N, where N is an integer greater than 1.

13. The DAC of claim 9, wherein the first frequency is equal to f_s/N, wherein the second frequency is equal to f_sV (N-1), wherein f_sEqual to an effective frequency of the DAC sequentially converting the plurality of digital inputs to the composite analog signal, wherein the first phase is equal to 1/f_sAnd wherein in addition N is an integer greater than 1。

14. The DAC of claim 13, wherein each of the first analog outputs is held at the combined output for N/f_sAnd wherein additionally each of the second analog outputs is held at the combined output for (N-1)/f_sThe duration of (c).

15. The DAC of claim 12, wherein the set of first sub-DACs includes N sub-DACs, and wherein further the set of second sub-DACs includes N-1 sub-DACs.

16. The DAC of claim 9, further comprising:

a demultiplexer configured to demultiplex the digital signal into a further plurality of digital inputs; and

a delay unit configured to add respective delays to the further plurality of digital inputs to generate the plurality of digital inputs for provision to the first sub-DAC and the second sub-DAC.

17. A communication system, comprising:

an interface configured to receive a digital signal; and

an interleaved digital-to-analog converter (DAC) coupled to the interface and configured to operate at an effective frequency f_sConverting the digital signal to a synthesized analog signal, wherein the interleaved DAC comprises:

a set of first sub-DACs operable to be coupled to a sub-DAC equal to f_sA set of first clock signals at a first frequency of/N, wherein the set of first sub-DACs is configured to convert a plurality of digital inputs to first analog outputs, respectively, wherein N is an integer greater than 1;

a set of second sub-DACs operable to be coupled to a signal equal to f_sA set of second clock signals at a second frequency of (N-1), wherein the set of second sub-DACs is configured to: separately and in parallel with the multiplexing of the plurality by the set of first sub-DACsConverting the plurality of digital inputs to a second analog output in parallel with converting the digital output to the first analog output; and

a combined output configured to combine the analog outputs of the set of first sub-DACs and the second set of second sub-DACs to generate the composite analog signal.

18. The communication system of claim 17, wherein each first sub-DAC of the set of first sub-DACs is configured to drive conversion of a digital input to a first analog output by N/f_sAnd wherein each second sub-DAC of the set of second sub-DACs is configured to drive conversion of a digital input to a second analog output by (N-1)/f_sThe duration of (c).

19. The communication system of claim 17, wherein first clock signals for converting each two consecutive ones of the plurality of digital inputs to a corresponding first analog output are shifted from each other by a first phase, and wherein second clock signals for converting each two consecutive ones of the plurality of digital inputs to a corresponding second analog output are shifted from each other by the first phase, and wherein further the first phase is equal to 1/f_s。

20. The communication system of claim 17, wherein in response to the same digital input, a first sub-DAC of the set of first sub-DACs and a second sub-DAC of the set of second sub-DACs are configured to generate a first analog output and a second analog output, respectively, having the same magnitude and opposite sign, wherein the first analog output is present at the combined output for N/f_sWherein the second analog output is present at the combined output for a duration of (N-1)/f_sAnd is 1/f delayed from the first analog output_s。

21. The communication system of claim 20, wherein a first clock signal coupled to the first sub-DAC and a second clock signal coupled to the second sub-DAC are shifted from each other by the first phase.

22. The communication system of claim 21, wherein the interleaved DAC further comprises:

a demultiplexer configured to demultiplex the digital signal into a further plurality of digital inputs; and

a delay unit configured to add respective delays to the further plurality of digital inputs to generate the plurality of digital inputs for provision to the first sub-DAC and the second sub-DAC.