阅读说明：本技术 一种采用镜像结构的栅压自举采样开关电路 (Grid voltage bootstrap sampling switch circuit adopting mirror image structure ) 是由 周前能 高唱 李红娟 于 2019-09-06 设计创作，主要内容包括：本发明请求保护一种采用镜像结构的栅压自举采样开关电路,通过采用“镜像”结构使得自举电容增大为传统电路的2倍,提高采样开关线性度；采用钟控虚拟MOS管吸收相关MOS管产生的沟道电荷的技术,抑制沟道电荷注入；采用钟控反相器输出端驱动NMOS管M10与NMOS管M12的结构,减小采样开关管M11栅极节点的寄生电容,抑制电路电荷共享,在采样开始阶段,NMOS管M10和NMOS管M12分别与PMOS管MOS管M5和PMOS管M13同时导通,加快采样开关的导通速度,在采样到保持转换瞬间,PMOS管M8与NMOS管M9组成电路以及PMOS管M16与NMOS管M17组成电路有一段时间同时保持导通,加快采样开关的关断速度。本电路有效地提高了栅压自举采样开关电路的线性度及开关速度,从而有效地改善了栅压采样开关电路整体性能。(The invention requests to protect a grid voltage bootstrap sampling switch circuit adopting a mirror image structure, and the linearity of a sampling switch is improved by adopting the mirror image structure to increase a bootstrap capacitor to 2 times that of a traditional circuit; the technology that a clock-controlled virtual MOS tube absorbs channel charges generated by a related MOS tube is adopted to inhibit channel charge injection; the structure that the output end of a clock-controlled inverter is adopted to drive an NMOS tube M10 and an NMOS tube M12 is adopted, the parasitic capacitance of a grid node of a sampling switch tube M11 is reduced, the charge sharing of a circuit is inhibited, in the sampling starting stage, the NMOS tube M10 and the NMOS tube M12 are respectively and simultaneously conducted with a PMOS tube MOS tube M5 and a PMOS tube M13, the conduction speed of the sampling switch is accelerated, at the moment of sampling to holding conversion, a circuit formed by the PMOS tube M8 and the NMOS tube M9 and a circuit formed by the PMOS tube M16 and the NMOS tube M17 are kept conducted for a period of time at the same time, and the turn-off speed of the sampling switch is. The circuit effectively improves the linearity and the switching speed of the grid voltage bootstrap sampling switch circuit, thereby effectively improving the overall performance of the grid voltage sampling switch circuit.)

1. A gate voltage bootstrapping sampling switch circuit adopting a mirror structure is characterized by comprising: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, NMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, PMOS tube M13, PMOS tube M14, NMOS tube M15, PMOS tube M16, NMOS tube M17, NMOS tube M18, NMOS tube M19, NMOS tube M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, PMOS tube M24, PMOS tube M25, PMOS tube M26, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 and capacitor C6;

the drain electrode of the NMOS tube M is connected with the drain electrode of the NMOS tube M, the source electrode of the PMOS tube M, the grid electrode of the NMOS tube M, the source electrode of the PMOS tube M, the drain electrode of the NMOS tube M and the external power supply VDD, the source electrode of the NMOS tube M is connected with the grid electrode of the NMOS tube M, the grid electrode of the NMOS tube M and one end of a capacitor C, the other end of the capacitor C is connected with the grid electrode of the NMOS tube M, the grid electrode of the PMOS tube M, the grid electrode of the NMOS tube M and an external clock CK, the source electrode of the NMOS tube M is connected with the grid electrode of the NMOS tube M and one end of a capacitor C, the other end of the capacitor C is connected with the grid electrode of the PMOS tube M, the grid electrode of the NMOS tube M and the external clock CK, the source electrode of the NMOS tube M is connected with the source electrode of the PMOS tube M, the drain electrode of the PMOS tube M and one, A source of the NMOS transistor M7 and a source of the NMOS transistor M10 are connected, a source of the NMOS transistor M4 is connected to a source of the NMOS transistor M9, and an external ground GND, a gate of the PMOS transistor M9 is connected to the external clock CK 9, a drain of the PMOS transistor M9 is connected to a gate of the NMOS transistor M9 and a drain of the NMOS transistor M9, a drain of the NMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a gate of the NMOS transistor M9, a drain of the NMOS transistor M9 is connected to the signal input Vin, a drain of the NMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a drain of the NMOS transistor M9, a drain of the PMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a drain of the NMOS transistor M9, and a drain of the PMOS transistor M9 are connected to a drain of the NMOS transistor M9, and a drain of the PMOS transistor M9, a drain of, the gate of the NMOS tube M12 is connected to the drain of the PMOS tube M16 and the drain of the NMOS tube M17, the gate of the PMOS tube M26 is connected to the external clock CK1, the source of the NMOS tube M18 is connected to the source of the PMOS tube M13, the drain of the PNMOS tube M13, the source of the PMOS tube M13, and one end of the capacitor C13, the other end of the capacitor C13 is connected to the source of the NMOS tube M13, and the drain of the NMOS tube M13, the source of the NMOS tube M13 is connected to the gate of the NMOS tube M13 and one end of the capacitor C13, the other end of the capacitor C13 is connected to the gate of the PMOS tube M13, the gate of the NMOS tube M13, and the external clock 13, the source of the NMOS tube M13 is connected to the gate of the NMOS tube M13, the gate of the NMOS tube CK 13, and the gate of the external clock 13.

2. The gate voltage bootstrap sampling switch circuit adopting the mirror image structure of claim 1, wherein the circuit composed of the NMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, the NMOS transistor M15, the PMOS transistor M16, the NMOS transistor M17, the NMOS transistor M18, the NMOS transistor M19, the NMOS transistor M20, the NMOS transistor M21, the PMOS transistor M26, the capacitor C4, the capacitor C5, and the capacitor C6 is a "mirror image" structure of a circuit composed of the NMOS transistor M1, the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, the NMOS transistor M7, the PMOS transistor M8, the NMOS transistor M9, the NMOS transistor M10, the PMOS transistor M25, the capacitor C1, the capacitor C2, and the capacitor C3, and the gate voltage of the "mirror image" sampling switch circuit is increased by twice the gate voltage sampling switch circuit adopting the "mirror image" structure.

3. The gate voltage bootstrapped sampling switch circuit of claim 1 or 2, wherein the PMOS transistor M8 and the NMOS transistor M9 form an inverter, such that the gate of the NMOS transistor M10 is disconnected from the gate of the NMOS transistor M11 of the sampling switch during the sampling period, the PMOS transistor M16 and the NMOS transistor M17 form an inverter, such that the gate of the NMOS transistor M12 is disconnected from the gate of the NMOS transistor M11 of the sampling switch during the sampling period, thereby reducing the parasitic capacitance of the gate node of the NMOS transistor M11, and therefore, the sampling switch NMOS transistor M11 operates the linear region channel resistor r_on11Is composed of

4. The gate voltage bootstrapped sampling switch circuit of claim 1 or 2, wherein the gate of the NMOS transistor M10 is controlled by the output of the inverter comprising the PMOS transistor M8 and the NMOS transistor M9, the gate of the NMOS transistor M12 is controlled by the output of the inverter comprising the PMOS transistor M16 and the NMOS transistor M17, at the beginning of sampling, the NMOS transistor M10 and the NMOS transistor M12 can be respectively connected to the PMOS transistor M5 and the PMOS transistor M13 at the same time, so as to increase the turn-on speed of the sampling switch, during the sample-hold conversion process, the gates of the PMOS transistor M5 and the PMOS transistor M13 are controlled by the output signal of an inverter from the external clock CK1, and at the instant of sample-hold conversion, the circuits comprising the PMOS transistor M8 and the NMOS transistor M9 and the circuits comprising the PMOS transistor M16 and the NMOS transistor M17 can be kept connected at the same time, so as to increase the turn-off speed of the sampling switch; the virtual PMOS transistor M25 and the virtual PMOS transistor M26 controlled by the external clock CK1 absorb channel charges generated by the PMOS transistor M8 and the PMOS transistor M16 respectively, so that the problem of channel charge injection is suppressed.

5. The gate voltage bootstrapped sampling switch circuit of claim 4, wherein during the sample-and-hold period, the external clock CK1 is at a low level, and the external clock CK2 is at a high level; the NMOS transistor M3, the NMOS transistor M4, the NMOS transistor M18 and the NMOS transistor M19 are all conducted, an external power supply VDD charges C3 and C4, and the voltage difference of upper and lower electrode plates of the NMOS transistor M19 is V_DDIn which V is_DDFor the voltage of an external power supply VDD, an NMOS tube M22 and an NMOS tube M23 are both conducted to turn off an NMOS tube M11, an NMOS tube M9 and an NMOS tube M17 are both conducted to turn off an NMOS tube M10 and an NMOS tube M12, a PMOS tube M6 and a PMOS tube M14 are both conducted to turn off a PMOS tube M5 and a PMOS tube M13, and therefore the NMOS tube M11 is disconnected from a capacitor C3 and a capacitor C4 in the holding stage;

in the sampling stage, the external clock CK1 is at a high potential, and the external clock CK2 is at a low potential; the NMOS transistor M3, the NMOS transistor M4, the NMOS transistor M18 and the NMOS transistor M19 are all turned off, and the voltage difference between the upper electrode plate and the lower electrode plate of the capacitor C3 and the capacitor C4 is V_DD(ii) a The NMOS tube M22 and the NMOS tube M23 are both turned off, so that the sampling switch circuit has no discharge path, the NMOS tube M7 and the NMOS tube M15 are both turned on, so that the PMOS tube M5 and the PMOS tube M13 are both turned on, the NMOS tube M9 and the NMOS tube M17 are both turned off, and the PMOS tube MOS tube M8 and the PMOS tube M16 are both turned on, so that the NMOS tube M10 and the NMOS tube M12 are both turned on, so that the NMOS tube M11 is connected with the capacitor C3 and the capacitor C4; at this time, the signal of the input Vin passes through the NMOS transistor M10, the capacitor C3 and the PMOS transistorM5 making the gate voltage of NMOS transistor M11 be V_in+V_DDWhile outputting a voltage V_outThe gate voltage of the NMOS transistor M11 is V through the NMOS transistor M12, the capacitor C4 and the PMOS transistor M13_out+V_DDAnd in the sampling phase V_in＝V_outTherefore, the gate voltage of the NMOS transistor M11 is still bootstrapped to V_in+V_DDIn which V is_inIs the voltage of input terminal Vin, V_outIs the voltage at the output.

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a grid voltage bootstrap sampling switch circuit.

Background

As integrated circuits develop, Analog-to-digital converters (ADCs) are developing as one of the main modules of mixed signal application systems, and are moving toward high speed and high precision. The sample/hold circuit is a core circuit of the ADC, and the sample switch is an important component of the sample/hold circuit, so that the performance characteristic of the sample switch largely determines the performance characteristic of the sample/hold circuit and further determines the performance characteristic of the ADC. Thus, the sampling switch is undoubtedly one of the important circuits of the ADC.

Fig. 1 is a conventional gate voltage bootstrap sampling switch, in which a MOS transistor M10 is a switching transistor, and the rest of bootstrap circuits. The basic principle is as follows:

(1) in the hold phase, the external clock CK1 is at a low potential and the external clock CK2 is at a high potential. At this stage, the MOS transistor M3 and the MOS transistor M4 are both turned on, and the bootstrap capacitor C3 is charged by the power supply, so that the voltage difference between the upper and lower plates is the power voltage V_DD(ii) a The MOS tube M11 and the MOS tube M12 are both conducted, the grid electrode of the MOS sampling switch tube M10 is at a low potential, and the MOS tube M9 and the MOS tube M10 are both turned off; the MOS tube M5 is switched on, so that the grid electrode of the MOS tube M7 is at a high potential, the MOS tube M7 is switched off, and the MOS sampling switch tube M10 is disconnected from the bootstrap capacitor C3 in a holding stage;

(2) in the sampling phase, the external clock CK1 is at a high level, and the external clock CK2 is at a low level. At this stage, MOS transistor M3 and MOS transistor M4 are both turned off, and the voltage difference between the upper and lower plates of bootstrap capacitor C3 is V_DD(ii) a The MOS transistor M11 and the MOS transistor M12 are both turned off, the MOS transistor M5 is turned off, and the MOS transistor M6 is turned on, so that the grid of the MOS transistor M7 is at a low potential and is turned on, and further, charges stored in the bootstrap capacitor C3 enable the MOS transistor M9 and the MOS transistor M10 to be both turned on; at this time, the input signal Vin passes through the MOS transistor M9, so that the voltage of the upper plate of the bootstrap capacitor C3 is V_in+V_DDIt makes the MOS sampling switch tube M10 grid voltage bootstrap to V through MOS tube M7_in+V_DDIn which V is_inIs the input signal voltage.

During the hold phase, although the voltage difference between the upper plate and the lower plate of the bootstrap capacitor C3 is charged to V_DDHowever, in the sampling phase, the parasitic capacitance of the gate node of the sampling switch tube M10 causes charge sharing, so that the gate-source voltage V of the sampling switch tube M10_GS10Less than V_DDAnd is a

Wherein, C₃Is the capacitance value of the capacitor C3, C_PThe total parasitic capacitance is the sum of the parasitic capacitances contributed by the MOS transistor M7, the MOS transistor M8, the MOS transistor M9, the MOS transistor M11 and the MOS transistor M12. In the sampling stage, the MOS transistor M10 works in the deep linear region, and the on-resistance r thereof_on10Is composed ofWherein, mu_nFor electron mobility, C_oxIs unit area gate oxide capacitance (W/L)₁₀Is the channel width length ratio, V, of the MOS sampling switch tube M10_TH10The threshold voltage of the switching tube M10 is sampled for MOS. Thus, charge sharing affects the linearity of the MOS sampling switch on-resistance. Meanwhile, in the initial sampling stage, after the MOS transistor M7 is turned on for a certain time, the MOS transistor M9 is turned on, so that the speed of the conventional gate voltage bootstrapped sampling switch is reduced.

Disclosure of Invention

The present invention is directed to solving the above problems of the prior art. A high-linearity and fast grid voltage bootstrap sampling switch circuit adopting a mirror image structure is provided. The technical scheme of the invention is as follows:

a gate voltage bootstrapped sampling switch circuit adopting a mirror structure comprises: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, NMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, PMOS tube M13, PMOS tube M14, NMOS tube M15, PMOS tube M16, NMOS tube M17, NMOS tube M18, NMOS tube M19, NMOS tube M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, PMOS tube M24, PMOS tube M25, PMOS tube M26, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 and capacitor C6;

the drain electrode of the NMOS tube M is connected with the drain electrode of the NMOS tube M, the source electrode of the PMOS tube M, the grid electrode of the NMOS tube M, the source electrode of the PMOS tube M, the drain electrode of the NMOS tube M and the external power supply VDD, the source electrode of the NMOS tube M is connected with the grid electrode of the NMOS tube M, the grid electrode of the NMOS tube M and one end of a capacitor C, the other end of the capacitor C is connected with the grid electrode of the NMOS tube M, the grid electrode of the PMOS tube M, the grid electrode of the NMOS tube M and an external clock CK, the source electrode of the NMOS tube M is connected with the grid electrode of the NMOS tube M and one end of a capacitor C, the other end of the capacitor C is connected with the grid electrode of the PMOS tube M, the grid electrode of the NMOS tube M and the external clock CK, the source electrode of the NMOS tube M is connected with the source electrode of the PMOS tube M, the drain electrode of the PMOS tube M and one, A source of the NMOS transistor M7 and a source of the NMOS transistor M10 are connected, a source of the NMOS transistor M4 is connected to a source of the NMOS transistor M9, and an external ground GND, a gate of the PMOS transistor M9 is connected to the external clock CK 9, a drain of the PMOS transistor M9 is connected to a gate of the NMOS transistor M9 and a drain of the NMOS transistor M9, a drain of the NMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a gate of the NMOS transistor M9, a drain of the NMOS transistor M9 is connected to the signal input Vin, a drain of the NMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a drain of the NMOS transistor M9, a drain of the PMOS transistor M9 is connected to a drain of the NMOS transistor M9 and a drain of the NMOS transistor M9, and a drain of the PMOS transistor M9 are connected to a drain of the NMOS transistor M9, and a drain of the PMOS transistor M9, a drain of, the gate of the NMOS tube M12 is connected to the drain of the PMOS tube M16 and the drain of the NMOS tube M17, the gate of the PMOS tube M26 is connected to the external clock CK1, the source of the NMOS tube M18 is connected to the source of the PMOS tube M13, the drain of the PNMOS tube M13, the source of the PMOS tube M13, and one end of the capacitor C13, the other end of the capacitor C13 is connected to the source of the NMOS tube M13, and the drain of the NMOS tube M13, the source of the NMOS tube M13 is connected to the gate of the NMOS tube M13 and one end of the capacitor C13, the other end of the capacitor C13 is connected to the gate of the PMOS tube M13, the gate of the NMOS tube M13, and the external clock 13, the source of the NMOS tube M13 is connected to the gate of the NMOS tube M13, the gate of the NMOS tube CK 13, and the gate of the external clock 13.

Further, the NMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, the NMOS transistor M15, the PMOS transistor M16, the NMOS transistor M17, the NMOS transistor M18, the NMOS transistor M19, the NMOS transistor M20, the NMOS transistor M21, the PMOS transistor M26, the capacitor C4, the capacitor C5, and the capacitor C6 form a "mirror image" structure of a circuit formed by the NMOS transistor M1, the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, the NMOS transistor M7, the PMOS transistor M8, the NMOS transistor M9, the NMOS transistor M10, the PMOS transistor M25, the capacitor C1, the capacitor C2, and the capacitor C3, and the capacitance of the gate voltage bootstrap sampling switch circuit adopting the "mirror image" structure is increased to twice the capacitance of the traditional gate voltage sampling switch circuit.

Furthermore, the PMOS transistor M8 and the NMOS transistor M9 form an inverter, so that the grid of the NMOS transistor M10 is disconnected with the grid of the sampling switch NMOS transistor M11 in the sampling stage, the PMOS transistor M16 and the NMOS transistor M17 form an inverter, so that the grid of the NMOS transistor M12 is disconnected with the grid of the sampling switch NMOS transistor M11 in the sampling stage, and therefore the grid node parasitic capacitance of the NMOS transistor M11 is reduced, and therefore the sampling switch NMOS transistor M11 works in a linear region to form a channel resistor r_on11Is composed of

Wherein mu_nFor electron mobility, C_oxIs unit area gate oxide capacitance (W/L)₁₁Is the channel width-to-length ratio of NMOS transistor M11, W is the channel width, L is the channel length, V_TH11Is the threshold voltage, C, of the NMOS transistor M11_PAIs the sum of parasitic capacitances C of PMOS transistor M5, PMOS transistor M13 and NMOS transistor M22 at signal path node₃Is the capacitance value of the capacitor C3, C₄Is the capacitance value of the capacitor C4, V_DDIs the voltage of the external power supply VDD.

Furthermore, the gate of the NMOS transistor M10 is controlled by the output end of an inverter composed of a PMOS transistor M8 and an NMOS transistor M9, the gate of the NMOS transistor M12 is controlled by the output end of an inverter composed of a PMOS transistor M16 and an NMOS transistor M17, at the beginning of sampling, the gates of the NMOS transistor M10 and the NMOS transistor M12 can be simultaneously turned on with the PMOS transistor MOS transistor M5 and the PMOS transistor M13, respectively, so as to increase the turn-on speed of the sampling switch, during the conversion from sampling to holding, the gates of the PMOS transistor M5 and the PMOS transistor M13 are controlled by an external clock CK1 via the output signal of the inverter, at the moment of conversion from sampling to holding, the circuit composed of the PMOS transistor M8 and the NMOS transistor M9 and the circuit composed of the PMOS transistor M16 and the NMOS transistor M17 can be simultaneously turned on for a while being kept on, so as to increase the turn-off; the virtual PMOS transistor M25 and the virtual PMOS transistor M26 controlled by the external clock CK1 absorb channel charges generated by the PMOS transistor M8 and the PMOS transistor M16 respectively, so that the problem of channel charge injection is suppressed.

Further, in the sample-and-hold stage, the external clock CK1 is at a low potential, and the external clock CK2 is at a high potential; the NMOS transistor M3, the NMOS transistor M4, the NMOS transistor M18 and the NMOS transistor M19 are all conducted, an external power supply VDD charges C3 and C4, and the voltage difference of upper and lower electrode plates of the NMOS transistor M19 is V_DDIn which V is_DDFor the voltage of an external power supply VDD, an NMOS tube M22 and an NMOS tube M23 are both conducted to turn off an NMOS tube M11, an NMOS tube M9 and an NMOS tube M17 are both conducted to turn off an NMOS tube M10 and an NMOS tube M12, a PMOS tube M6 and a PMOS tube M14 are both conducted to turn off a PMOS tube M5 and a PMOS tube M13, and therefore the NMOS tube M11 is disconnected from a capacitor C3 and a capacitor C4 in the holding stage;

in the sampling stage, the external clock CK1 is at a high potential, and the external clock CK2 is at a low potential; the NMOS transistor M3, the NMOS transistor M4, the NMOS transistor M18 and the NMOS transistor M19 are all turned off, and the voltage difference between the upper electrode plate and the lower electrode plate of the capacitor C3 and the capacitor C4 is V_DD(ii) a The NMOS tube M22 and the NMOS tube M23 are both turned off, so that the sampling switch circuit has no discharge path, the NMOS tube M7 and the NMOS tube M15 are both turned on, so that the PMOS tube M5 and the PMOS tube M13 are both turned on, the NMOS tube M9 and the NMOS tube M17 are both turned off, and the PMOS tube MOS tube M8 and the PMOS tube M16 are both turned on, so that the NMOS tube M10 and the NMOS tube M12 are both turned on, so that the NMOS tube M11 is connected with the capacitor C3 and the capacitor C4; at this time, the signal of the input terminal Vin passes through the NMOS transistor M10, the capacitor C3 and the PMOS transistor M5, so that the gate voltage of the NMOS transistor M11 is V_in+V_DDWhile outputting a voltage V_outThe gate voltage of the NMOS transistor M11 is V through the NMOS transistor M12, the capacitor C4 and the PMOS transistor M13_out+V_DDAnd in the sampling phase V_in＝V_outTherefore, the gate voltage of the NMOS transistor M11 is still bootstrapped to V_in+V_DDIn which V is_inIs the power of input terminal VinPressure, V_outIs the voltage at the output.

The invention has the following advantages and beneficial effects:

the invention provides a novel grid voltage bootstrap sampling switch circuit, which adopts an NMOS tube M12, a PMOS tube M12, an NMOS tube M12, a PMOS tube M12, a capacitor C12, and a capacitor C12 to form a circuit, wherein the circuit is an NMOS tube M12, a PMOS tube M12, an NMOS tube M12, a bootstrap tube M12, a PMOS tube M12, a capacitor C12, and a capacitor C12 to form a 'mirror image' structure of the circuit, so that the capacitance value of the novel grid voltage sampling switch circuit is increased to double that of a traditional grid voltage bootstrap sampling switch, the grid voltage sampling switch circuit is adopted, the NMOS tube M12 and the NMOS switch circuit are respectively controlled by the NMOS switch structure of the NMOS tube M12 and the NMOS switch 12 at the grid voltage sampling switch circuit is disconnected at the grid voltage sampling switch circuit stage, the parasitic capacitance of the grid node of the NMOS tube M11 is reduced, the influence of charge sharing is reduced, and the grid source voltage V of the NMOS tube M11 of the sampling switch is enabled to be V_GS11Closer to the supply voltage V_DDImproving the linearity of the sampling switch;

the virtual PMOS tube M25 and the virtual PMOS tube M26 controlled by an external clock CK1 absorb channel charges generated by the PMOS tube M8 and the PMOS tube M16 respectively to inhibit the problem of channel charge injection, the NMOS tube M10 and the NMOS tube M12 are controlled by the output end of a clock control inverter respectively, at the beginning stage of sampling, the NMOS tube M10 and the NMOS tube M12 can be conducted with the PMOS tube MOS tube M5 and the PMOS tube M13 respectively at the same time to accelerate the conduction speed of the sampling switch, and at the moment of conversion from sampling to holding, a circuit formed by the PMOS tube M8 and the NMOS tube M9 and a circuit formed by the PMOS tube M16 and the NMOS tube M17 can be kept on for a period of time at the same time to accelerate the turn-off speed of the sampling switch, so that the overall performance characteristic of the grid voltage sampling switch is improved effectively.

Drawings

FIG. 1 is a circuit diagram of a conventional gate voltage bootstrapped sampling switch;

FIG. 2 is a circuit diagram of a novel gate voltage bootstrapped sampling switch according to a preferred embodiment of the present invention;

fig. 3 is a simulation diagram of the gate voltage of the sampling switch tube of the novel gate voltage bootstrap sampling switch circuit and the conventional gate voltage bootstrap sampling switch circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.

The technical scheme for solving the technical problems is as follows:

the embodiment of the application provides a mirror image grid voltage bootstrap sampling switch circuit, and the linearity and the turn-off speed of the sampling switch circuit are effectively improved by adopting the technologies that a mirror image structure is adopted to increase a bootstrap capacitor, a clocked inverter is adopted to reduce a parasitic capacitor, an external clock CK1 controls a virtual MOS tube to absorb channel charges, and the like.

In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and specific embodiments.