阅读说明：本技术 具有半级联的电流镜布置 (Current mirror arrangement with half-cascade ) 是由 D·阿克司因 O·弗罗迪 于 2021-04-29 设计创作，主要内容包括：本公开涉及具有半级联的电流镜布置。示例电流镜布置包括电流镜电路,被配置为在输入晶体管Q1处接收输入电流信号并在输出晶体管Q2处输出镜像信号。该布置还包括半级联电路,该半级联电路包括晶体管Q3、Q4和两端无源网络。晶体管Q3耦合到输出晶体管Q2并与其级联。晶体管Q4耦合到晶体管Q3。晶体管Q3的基极/栅极耦合到偏置电压Vref,并且晶体管Q4的基极/栅极通过两端无源网络耦合到偏置电压Vref1。通过选择适当的无源网络阻抗并选择适当的偏置电压Vref和Vref1,可以减少这种电流镜布置的输出电流的非线性。(The present disclosure relates to a current mirror arrangement with a half-cascade. An example current mirror arrangement includes a current mirror circuit configured to receive an input current signal at an input transistor Q1 and output a mirror signal at an output transistor Q2. The arrangement also includes a semi-cascode circuit comprising transistors Q3, Q4 and a two-terminal passive network. A transistor Q3 is coupled to and cascaded with the output transistor Q2. Transistor Q4 is coupled to transistor Q3. The base/gate of transistor Q3 is coupled to a bias voltage Vref, and the base/gate of transistor Q4 is coupled to a bias voltage Vref1 through a two terminal passive network. The non-linearity of the output current of such a current mirror arrangement can be reduced by selecting the appropriate passive network impedance and selecting the appropriate bias voltages Vref and Vref 1.)

1. A current mirror arrangement comprising:

a current mirror circuit comprising a transistor Q1 at an input of the current mirror circuit and a transistor Q2 at an output of the current mirror circuit;

a transistor Q3;

a transistor Q4; and

the passive networks PN at both ends,

wherein:

each of the transistors Q1, Q2, Q3, and Q4 having a first terminal, a second terminal, and a third terminal,

a first terminal of the transistor Q1 is coupled to a first terminal of the transistor Q2 and a second terminal of the transistor Q1,

a second terminal of the transistor Q2 is coupled to a third terminal of the transistor Q3,

a second terminal of the transistor Q3 is coupled to a third terminal of the transistor Q4,

a first terminal of the transistor Q3 is coupled to a bias voltage Vref, an

A first terminal of the transistor Q4 is coupled to a first terminal of the two-terminal passive network PN, and a second terminal of the two-terminal passive network PN is coupled to a bias voltage Vref 1.

2. The current mirror arrangement of claim 1, wherein the bias voltage Vref and the bias voltage Vref1 are such that a quiescent voltage between first and second terminals of the transistor Q3 is substantially equal to a quiescent voltage between first and second terminals of the transistor Q4.

3. The current mirror arrangement according to claim 1, wherein the impedance of the two-terminal passive network PN is such that the voltage swing at the first terminal of the transistor Q4 is substantially equal to half the voltage swing at the output of the current mirror arrangement.

4. The current mirror arrangement of claim 1, wherein the current mirror arrangement comprises M stages, wherein:

m is an integer greater than 1 and M is a hydrogen atom,

each stage i of said M stages comprising a respective group of transistors and a two-terminal passive network, wherein i is an integer between 1 and M,

for i-1, the transistor of stage i is transistor Q4, and the two-terminal passive network of stage i is the two-terminal passive network PN, and

for i >1:

a first terminal of the transistor of stage i is coupled to a first terminal of the two-terminal passive network of stage i,

the second terminal of the two-terminal passive network of stage i is coupled to Vrefi, which is the bias voltage of stage i, and

the third terminal of the transistor of stage i is coupled to the second terminal of the transistor of stage i-1.

5. The current mirror arrangement of claim 4, wherein:

for i < M, the second terminal of the transistor of stage i is coupled to the third terminal of the transistor of stage i +1, an

A second terminal of the transistor of stage M is coupled to an output of the current mirror arrangement.

6. The current mirror arrangement according to claim 4, wherein for any i between 1 and M, the impedance of the two-terminal passive network of stage i is such that the voltage swing at the first terminal of the transistor of stage i is substantially equal to i x VO/(M +1), where VO is the voltage swing at the output of the current mirror arrangement.

7. The current mirror arrangement of claim 1, wherein for each transistor Q1, Q2, Q3, and Q4, the first terminal is a base terminal, the second terminal is a collector terminal, and the third terminal is an emitter terminal.

8. The current mirror arrangement of claim 7, wherein the emitter area of each transistor Q2, Q3, and Q4 is K times the emitter area of the transistor Q1, wherein K is a positive number.

9. The current mirror arrangement of claim 1, wherein for each transistor Q1, Q2, Q3, and Q4, the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

10. The current mirror arrangement of claim 9, wherein the aspect ratio of each transistor Q2, Q3, and Q4 is K times the aspect ratio of the transistor Q1, where K is a positive number.

11. The current mirror arrangement of claim 1, wherein:

a second terminal of the transistor Q1 is coupled to an input of the current mirror circuit, an

A second terminal of the transistor Q2 is coupled to an output of the current mirror circuit.

12. A current mirror arrangement comprising:

a current mirror circuit comprising a transistor Q1 at an input of the current mirror circuit and a transistor Q2 at an output of the current mirror circuit;

a transistor Q3;

a transistor Q4; and

a passive network is arranged at the two ends,

wherein:

the transistor Q2 is in a common emitter configuration,

the transistor Q3 and the transistor Q4 are each in a common base configuration,

the output of the transistor Q2 is coupled to the input of the transistor Q3,

the output of the transistor Q3 is coupled to the input of the transistor Q4,

the output of the transistor Q4 is coupled to the output of the current mirror arrangement,

the base terminal of the transistor Q3 is coupled to a bias voltage Vref,

a base terminal of the transistor Q4 is coupled to a first terminal of the two-terminal passive network, an

A second terminal of the two-terminal passive network is coupled to a bias voltage Vref 1.

13. The current mirror arrangement of claim 12, wherein the bias voltage Vref and the bias voltage Vref1 are such that a quiescent voltage between a base terminal and an output of the transistor Q3 is substantially equal to a quiescent voltage between a base terminal and an output of the transistor Q4.

14. The current mirror arrangement of claim 12, wherein the two-terminal passive network comprises one or more resistors, capacitors, and inductors.

15. The current mirror arrangement of claim 12, wherein the impedance of the two-terminal passive network is such that the voltage swing at the base terminal of the transistor Q4 is substantially equal to half the voltage swing at the output of the current mirror arrangement.

16. A current mirror arrangement comprising:

a current mirror circuit comprising a transistor Q1 at an input of the current mirror circuit and a transistor Q2 at an output of the current mirror circuit;

a transistor Q3; and

the transistors of the transistors Q4 are,

wherein:

each of the transistors Q1, Q2, Q3, and Q4 having a first terminal, a second terminal, and a third terminal,

the input of the transistor Q3 is coupled to the output of the current mirror circuit,

the input of the transistor Q4 is coupled to the output of the transistor Q3,

the output of the transistor Q4 is coupled to the output of the current mirror arrangement, an

The transistors Q3 and Q4 are configured such that the voltage at the first terminal of the transistor Q4 and the voltage at the second terminal of the transistor Q3 vary accordingly as the voltage at the output of the current mirror arrangement varies.

17. The current mirror arrangement of claim 16, wherein the transistor Q3 is cascaded with the transistor Q2.

18. The current mirror arrangement of claim 16, wherein the transistor Q4 is cascaded with the transistor Q3.

19. The current mirror arrangement of claim 16, further comprising a two-terminal passive network, wherein a first terminal of the two-terminal passive network is coupled to the transistor Q4 and a second terminal of the two-terminal passive network is coupled to a bias voltage Vref 1.

20. The current mirror arrangement of claim 19, wherein:

the transistor Q3 is coupled to a second bias voltage Vref, an

The bias voltage Vref and the bias voltage Vref1 are such that the quiescent voltage between the terminal of transistor Q3 coupled to the bias voltage Vref and the output of the transistor Q3 is substantially equal to the quiescent voltage between the terminal of transistor Q4 coupled to the bias voltage Vref1 and the output of the transistor Q4.

Technical Field

The present disclosure relates generally to electronic devices and, more particularly, to current mirror circuits.

Background

A current mirror is one of the few components necessary for a typical circuit design. In particular, the broadband linear current mirror is one of the main basic modules of the open-loop broadband linear amplifier, and is widely used in the markets of communication, military, automobiles, industry and the like.

Designing a current mirror can mirror its input current to its output with a constant current gain in a constant manner over a wide operating bandwidth, and this is not a trivial matter with ever increasing fundamental input signal frequency. At a given operating frequency, the linearity and signal bandwidth of the current mirror ultimately set an upper limit on the dynamic range of the amplifier or any other circuit in which the current mirror is used. Traditionally, linearity has required tradeoffs with bandwidth and power. Therefore, having a current mirror with both high linearity and wide signal bandwidth would provide a significant competitive advantage in a given market of differentiated products.

Drawings

To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

FIG. 1 provides a circuit diagram of an NPN implementation of a conventional current mirror with a current gain K;

FIG. 2 provides a circuit diagram of an NPN embodiment of the current mirror of FIG. 1, additionally showing the associated parasitic elements at high operating frequencies;

FIG. 3 provides a circuit diagram of an NPN implementation of cascaded current mirrors;

FIG. 4 provides a circuit diagram of an NPN implementation with a single-stage half-cascaded current mirror arrangement according to some embodiments of the present disclosure;

fig. 5 provides a circuit diagram of a PNP implementation with a single-stage half-cascaded current mirror arrangement according to some embodiments of the present disclosure;

fig. 6 provides a circuit diagram of an NPN implementation of a current mirror arrangement having a plurality of half-cascaded stages, according to some embodiments of the present disclosure;

fig. 7 provides a circuit diagram of a PNP implementation of a current mirror arrangement having a plurality of half-cascaded stages, according to some embodiments of the present disclosure;

fig. 8 provides a schematic diagram of a system in which a current mirror arrangement with half-cascades may be implemented, according to some embodiments of the present disclosure.

Detailed Description

Overview

The systems, methods, and devices of the present disclosure each have several innovative aspects, none of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

In one aspect of the disclosure, a current mirror arrangement with a half-cascade is described. The precise design of the current mirror arrangement with the half-cascade can be achieved in many different ways, all of which are within the scope of the present disclosure. In one example of a design variation according to various embodiments of the present disclosure, a selection may be made separately for each transistor having a semi-cascaded current mirror arrangement to employ a bipolar transistor (e.g., where the various transistors may be NPN or PNP transistors), a Field Effect Transistor (FET), such as a Metal Oxide Semiconductor (MOS) technology transistor (e.g., where the various transistors may be N-type MOS (nmos) or P-type MOS (pmos) transistors), or a combination of one or more FETs and one or more bipolar transistors. In view of this, in the following description, the transistors are described with reference to the first, second, and third terminals of the transistors. If the transistor is a bipolar transistor, the "first terminal" of the transistor is used to refer to the base terminal; if the transistor is a FET, the "first terminal" of the transistor is used to refer to the gate terminal; the "second terminal" of the transistor refers to the collector terminal if the transistor is a bipolar transistor, and to the drain terminal if the transistor is an FET; the "third terminal" of the transistor refers to the emitter terminal if the transistor is a bipolar transistor, and to the source terminal if the transistor is a FET. These terms remain the same whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor if the transistor is a bipolar transistor; an NMOS transistor if the transistor is a FET) or a P-type transistor (e.g., a PNP transistor if the transistor is a bipolar transistor; a PMOS transistor if the transistor is a FET).

In another example of a design variation according to various embodiments of the present disclosure, a selection may be made separately for each transistor having a semi-cascaded current mirror arrangement, which transistors are implemented as N-type transistors (e.g., NMOS transistors for transistors implemented as FETs, or NPN transistors for transistors implemented as bipolar transistors), and which transistors are implemented as P-type transistors (e.g., PMOS transistors for transistors implemented as FETs, or PNP transistors for transistors implemented as bipolar transistors). In other examples, in various embodiments, which type of transistor architecture is employed may be selected. For example, any transistor implemented as a FET with a semi-cascaded current mirror arrangement as described herein may be a planar transistor or a non-planar transistor, such as a FinFET, nanowire transistor, or nanoribbon transistor. Some exemplary embodiments of current mirror arrangements with half cascades are shown in fig. 4-7. However, any implementation with a semi-cascaded current mirror arrangement consistent with the description provided herein is within the scope of the present disclosure.

Example arrangements may include current mirror circuits and circuits referred to herein as "semi-cascaded" circuits. The current mirror circuit may include an input transistor Q1 and an output transistor Q2, and may be configured to receive an input signal (e.g., an input current signal I) at an input_IN) And outputs an image signal (e.g., an image current signal IM) at the output, where IM K I_INWhere K is the current gain, which is a positive number greater than 0 (the value may, but need not, be an integer). For a bipolar embodiment, the value of K may indicate (e.g., be equal to or based on) the ratio of the area of the emitter of the output transistor Q2 to the area of the emitter of the input transistor Q1. For a FET implementation embodiment, the value of K may indicate the ratio of the aspect ratio of the output transistor Q2 to the aspect ratio of the input transistor Q1, where the aspect ratio of a FET transistor may be defined as the channel width of that transistor divided by its channel length. In embodiments where K is greater than 0 but less than 1, multiplying by K means attenuating the current. In embodiments where K is greater than 1, multiplying by K means increasing or obtaining the current. The semi-cascode circuit may include transistors Q3 and Q4, and a two-terminal passive network (e.g., a resistor). Each of the transistors Q3 and Q4 may be in a common base configuration if the transistors Q3 and Q4 are bipolar transistors, or in a common gate configuration if the transistors Q3 and Q4 are FETs. CrystalThe tube Q3 may be coupled to the output transistor Q2 and form a cascade with the output transistor Q2. Transistor Q4 may be coupled to transistor Q3. The base/gate of transistor Q3 may be coupled to a bias voltage Vref, and the base/gate of transistor Q4 may be coupled to the bias voltage Vref1 through a two-terminal passive network. The non-linearity of the output current from such a current mirror arrangement can be reduced by selecting the appropriate impedance of the two-terminal passive network and selecting the appropriate bias voltages Vref and Vref1 for transistors Q3 and Q4. For example, the impedance of the two-terminal passive network may be selected such that the voltage swing of the base/gate terminal of transistor Q4 is substantially half the output swing at the frequency of interest. On the other hand, the bias voltages Vref and Vref1 may be selected such that the quiescent voltage between the bias/gate terminal and the output of transistor Q3 is substantially equal to the quiescent voltage between the bias/gate terminal and the output of transistor Q4.

The term "semi-cascode" is a term chosen for use in this disclosure to reflect that the circuit of transistors Q3, Q4, as well as the two-terminal passive network (particularly the portion of the circuit that includes transistor Q4, with the transistor Q4 coupled to the bias voltage Vref1 through the two-terminal passive network) can be considered to be between having cascode devices and not having any cascode devices. Typically, to implement a cascode device having two transistors, one of which is a cascode transistor and the other of which is a cascode transistor, a voltage source is applied directly to the base/gate terminals of the cascode transistors (i.e., the base/gate voltages of the cascode transistors are constant). In this way, the emitter/source terminal voltage of the cascode transistor, and thus the collector/drain terminal voltage of the cascode transistor, can be kept constant. In contrast, the base/gate voltage of transistor Q4 described herein is allowed to move up and down based on (i.e., vary according to variations) the signal at the output of the current mirror arrangement. Subsequently, the emitter/source voltage of the cascode transistor also varies with the output signal. The proposed arrangement is therefore intermediate between having a cascode device (i.e. a constant base/gate voltage across the cascode transistor) and not having any cascode device (i.e. a base/gate voltage, hence the emitter/source voltage of the cascode transistor moves with the output signal). Consistent with this, transistor Q4 having a serial two-terminal passive network coupled to its base/gate terminal may be referred to as a "half-cascade stage" in this disclosure. In a further embodiment, the current mirror arrangement may comprise a plurality of such semi-cascaded stages, for example as shown in fig. 6 and 7.

As will be appreciated by those skilled in the art, aspects of the present disclosure, particularly aspects having a semi-cascaded current mirror arrangement, as described herein, may be embodied in various ways, for example, as a method or system. The following detailed description presents various descriptions of specific certain embodiments. The innovations described herein may, however, be embodied in many different forms, for example, as defined and encompassed by the claims or selected examples. For example, while some description herein is provided with respect to bipolar (e.g., NPN or PNP implementations) or field effect (e.g., NMOS or PMOS implementations) transistors, other embodiments of the current mirror arrangements described herein may include any bipolar transistor and FET combination.

In the following description, reference is made to the accompanying drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements shown in the figures are not necessarily drawn to scale. Further, it will be understood that certain embodiments may include more elements than are shown in the figures and/or subsets of the elements shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures.

With the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electronic components. However, this is done for clarity and example purposes only. It should be understood that the devices and systems described herein may be combined in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the invention may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of flows with reference to only a limited number of electrical elements. It will be appreciated that the circuitry of the present figure and its teachings is readily scalable and can accommodate a large number of components, as well as more complex or sophisticated arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of electronic circuits that could potentially be applied to a myriad of other architectures.

The description may use the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connect" refers to a direct electrical connection between the things that are connected, without any intervening devices/components, while the term "couple" refers to a direct electrical connection between the things that are connected, or an indirect electrical connection through one or more passive or active intervening devices/components. In another example, the term "circuitry" refers to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms "substantially," "about," "approximately," and the like, if used, may be used to generally refer to being within +/-20% of a target value, e.g., +/-10% of the target value, based on the context of the particular values described herein or known in the art. For the purposes of this disclosure, the phrase "a and/or B" or the symbol "a/B" means (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The term "between" when used with reference to a measurement range includes the ends of the measurement range. As used herein, the symbol "A/B/C" refers to (A, B and/or C).

Basis of current mirror

For the purpose of illustrating the current mirror arrangement with semi-cascades presented herein, it may be useful to first understand the phenomena that may work when currents are mirrored. The following basic information may be considered as a basis on which the present disclosure may be appropriately explained. This information is provided for explanatory purposes only and, therefore, should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

Fig. 1 provides a circuit diagram of a simple single-ended NPN bipolar transistor implementation with a current mirror 100 having a current gain K, as is known in the art. As shown in fig. 1, the current mirror 100 may include a first transistor Q1 (which may be referred to as an "input transistor") and a second transistor Q2 (which may be referred to as an "output transistor"). Input current 102 (I)_IN) May be provided by the input current source 104 (i.e., the current to be mirrored at the output of the current mirror 100 to generate the output current 108). The current mirror 100 may first generate the control voltage (voltage VN1) on node 106 (node N1) by placing transistor Q1 in feedback to force the current on the collector terminal 110 (or simply "collector" 110) of transistor Q1 to equal the input current 102. The emitter terminal 112 (or simply "emitter" 112) of transistor Q1 may be connected to ground, as shown in fig. 1. The base terminal 114 of transistor Q1 (or simply base 114) may be coupled to the base 124 of transistor Q2. The voltage VN1 carrying input current information may be utilized to drive the base 124 of the output transistor Q2 to produce the output current 108. Fig. 1 also indicates a collector 120 of transistor Q2 and an emitter 122 of transistor Q2, where emitter 122 may be grounded and output current 108 is the current at collector 120 as shown in fig. 1. When the emitter area of transistor Q2 is K times the emitter area of transistor Q1, current 108 (I) is output_O) Possibly equal to K.I_IN。

A simplified model of the bipolar transistor collector current is given by:

wherein I_C、A、I_S、V_BEAnd V_tRespectively a collector current,Emitter area, saturation current per unit area, base-emitter voltage, and thermal voltage. Despite the collector current (I)_C) And base-emitter voltage (V)_BE) The relationship between (i.e. equivalent input current I)_INAnd VN1) is strongly non-linear, but the input-output current mirroring is linear, i.e. I_O＝K·I_IN。

The basic analysis given above has a number of disadvantages in understanding the degradation of current mirrors at high operating frequencies. Fig. 2 provides a circuit diagram of an NPN embodiment of current mirror 200. The current mirror 200 is substantially identical to the current mirror circuit 100 of fig. 1, except that it additionally shows the associated parasitic elements for high operating frequencies. In other words, fig. 2 shows important parasitic devices that may reduce the bandwidth and linearity of the circuit 100. It should be understood that the parasitic elements shown in the figures and discussed herein refer to elements that are not intentionally fabricated in a circuit, but rather are indicative of an unintentional effect or behavior that may be exhibited by the circuit.

Elements in fig. 2 having reference numerals shown in fig. 1 are intended to show the same or similar elements as those described with respect to fig. 1, and thus, the description thereof will not be repeated for the sake of brevity. This applies to other figures of the disclosure-elements with reference to a figure described with reference to one figure may be the same or similar to elements with the same reference number shown in another figure, so the description provided for one figure applies to another figure without repetition.

The current mirror 200 may be affected by one or more of a parasitic capacitance 216, a parasitic capacitance 218, a parasitic capacitance 220, a parasitic capacitance 228, and a resistance 224 (which may be used to convert the output current of the current mirror to a voltage), each of which is coupled as shown in fig. 2.

Parasitic capacitance 216 may represent all routing parasitic capacitances associated with node 106, parasitic capacitance of 104 input current source load node 106, and collector-substrate capacitances and extrinsic base terminal parasitic capacitors of transistors Q1 and Q2. Note that bipolar transistor collector-substrate capacitors based on modern SOI technology are relatively small and can be considered linear. Parasitic capacitance 218 may represent the intrinsic base-emitter forward bias capacitance of transistor Q1. The parasitic capacitance 220 may represent the intrinsic base-emitter forward bias capacitance of the transistor Q2 (which may be K times greater than the parasitic capacitance 218 if the emitter area of the transistor Q2 is K times greater than the emitter area of the transistor Q1). The parasitic capacitance 228 may represent the intrinsic base-collector junction parasitic capacitance of the transistor Q2. Resistor 224 may represent the output Resistance (RO) of current mirror 100/200.

The inventors of the present disclosure have recognized that from an analysis of the circuit in fig. 2, three different mechanisms of reducing the bandwidth and/or linearity of the current mirror can be identified for a bipolar transistor implementation. One is the bandwidth reduction due to parasitic capacitors. Another is the degradation of linearity due to the non-linearity of the intrinsic base-collector junction parasitic capacitance (e.g., parasitic capacitance 228 shown in fig. 2). The third is the decrease in linearity due to the linear parasitic capacitance 216.

Similarly, many linear droop mechanisms can be identified for FET implementations of the current mirror circuit. One degradation mechanism for FET implementations is bandwidth degradation due to parasitic capacitors, similar to bipolar implementations. The other is the decrease in linearity due to the linear capacitive load on node 106. The third is due to the gate-drain capacitance C_GDThe resulting linearity is reduced.

The inventors of the present disclosure have further recognized that improvements in at least some of these degradation mechanisms may provide improvements in designing linear broadband current mirrors.

Current mirror arrangement cascade device

In general, different techniques may be implemented to ameliorate one or more of the above problems, where some compromise must be made, for example, in transaction performance with complexity. As described above, embodiments of the present disclosure aim to address non-linearities associated with the base-collector junction parasitic capacitance of the output transistor Q2. Due to the large quiescent current at the current mirror output, the parasitic capacitance of the nonlinear base-collector junction can be large, which is common in wideband designs. The parasitic capacitance of the base-collector junction may convert the output signal swing to a non-linear current at the output node and load the diode side of the current mirror, thereby reducing overall linearity and reducing current mirror bandwidth due to the miller effect. Embodiments of the present disclosure are based on the following recognition: implementing a half-cascade with one or more half-cascade stages may provide improvements with respect to reducing non-linearities associated with base-collector junction parasitic capacitance.

For high frequency applications, the cascade technique is mainly used to isolate the input side of the circuit from signal interference caused by large swings at its output. The technique can effectively eliminate the miller effect of loading the node 106, thereby reducing the bandwidth of the mirror and its linearity. An example of a cascade technique is shown in fig. 3, which provides a circuit diagram of an NPN implementation of a current mirror arrangement 300, which current mirror arrangement 300 may be referred to as a "cascade current mirror 300". Fig. 3 shows a current mirror formed by transistors Q1 and Q2, similar to that shown in fig. 1. Fig. 3 also shows the intrinsic base-collector junction parasitic capacitance 228 associated with transistor Q2, and the resistance 224, similar to fig. 2. The other parasitic capacitances in fig. 2 are not shown in fig. 3, since the focus is now on the base-collector junction parasitic capacitance.

As shown in fig. 3, the cascode current mirror 300 includes a transistor Q3 in addition to the current mirror formed by transistors Q1 and Q2. Similar to transistors Q1 and Q2, transistor Q3 may be an NPN transistor having a collector 330, an emitter 332, and a base 334. The emitter 332 of the transistor Q3 may be coupled to the collector 120 of the transistor Q2. The collector 330 of transistor Q3 may be coupled to the output resistor 224 or the output current 108. The base 334 of transistor Q3 may be coupled to a reference voltage Vref. Transistor Q3 may be used to keep the collector node voltage of transistor Q2 substantially constant, or with different wording to make the equivalent impedance seen from the collector terminal of transistor Q2 equal to 1/gm₃Rather than the equivalent impedance of the output resistor 224. Fig. 3 further illustrates parasitic capacitance 328 associated with transistor Q3, which is an intrinsic base-collector junction capacitance similar to capacitance 228. Thus, the cascode current mirror 300 may include two inherent base-collector junction capacitances, one for each of the base-collector junction capacitances shown in FIG. 3Transistors Q2 and Q3 are associated. In the cascaded current mirror 300, the non-linear current through the intrinsic base-collector junction capacitance of transistor Q1 is not shown because the signal swing on the intrinsic base-collector junction capacitance of this transistor is substantially equal to zero.

Although the cascode current mirror 300 may provide improvement in mitigating the miller effect, it does not improve the non-linear current injected into the output current by the non-linear reverse bias capacitor 328 of the transistor Q3. Such non-linear currents may limit the achievable linearity, especially in applications where high frequency signals may need to be generated (e.g., as drive signals for analog-to-digital converters (ADCs)) when the capacitors 228 and 328 and output swing are large.

Exemplary bulk semi-cascaded Current mirror arrangement

To reduce the non-linear current at the output due to the intrinsic base-collector junction capacitances 228 and 328 associated with transistors Q2 and Q3, embodiments of the present disclosure propose adding one or more half-cascaded stages to the arrangement shown in fig. 3. In particular, the semi-cascaded arrangement described herein is intended to reduce the non-linear current of the base-collector junction capacitance by effectively reducing the signal swing across these capacitors (e.g., by effectively reducing the signal swing between the base and collector terminals of transistors Q3 and Q4 shown in fig. 4). Since the swing on the output node of the current mirror arrangement is set by the module specification, the only feasible way to reduce the signal swing on the base-collector junction capacitance (e.g., 428 and 328 in fig. 4) is to let the corresponding base terminal swing with the swing on the output node. A first example of which is shown in fig. 4, which provides a circuit diagram of an NPN implementation with a single-stage, half-cascaded current mirror arrangement 400, according to some embodiments of the present disclosure.

The current mirror arrangement 400 includes all of the elements shown in fig. 3, and for the sake of brevity, the description thereof will not be repeated here (fig. 4 further identifies the positive supply of the circuit with reference numeral 480 and the negative supply of the circuit, e.g., ground potential, with reference numeral 482). In addition, the current mirror arrangement 400 further includes a transistor Q4, the emitter terminal 442 of which transistor Q4 is coupled to the collector terminal 330 of the transistor Q3, and the base terminal 444 of which is coupled to the bias voltage Vref1 via a resistor 450 (e.g., the base terminal 444 may be coupled to a first terminal of the resistor 450, and the bias voltage Vref1 may be coupled to a second terminal of the resistor 450).

Resistor 450 is an exemplary representation that may generally be any other two-terminal passive network. Thus, although a resistor 450 is shown in fig. 4, in general, the current mirror arrangement 400 may include any other two-terminal passive network 450, which may include one or more passive components, such as resistors, capacitors, and inductors. In some embodiments, it may be advantageous to use resistors as the two-terminal passive network 450 in terms of reduced complexity. In other embodiments, the two-terminal passive network 450 may include a complex impedance at the base terminal 444 of the transistor Q4 instead of a simple resistor to further extend the linear operating band of the current mirror arrangement 400.

Fig. 4 further illustrates that a collector terminal 440 of a transistor Q4 may be coupled to the output 108 of the current mirror arrangement 400, and also illustrates a parasitic base-collector junction capacitance 428 that may be associated with the transistor Q4.

Together, the transistors Q3, Q4 and the two-terminal passive network 450 may be considered a "half-cascade arrangement" in which the transistor Q4 and the two-terminal passive network 450 are single stages of the half-cascade arrangement. The current mirror arrangement 400 with the semi-cascaded arrangement may operate as follows.

The current mirror arrangement 400 reduces non-linear current due to base-collector junction parasitic capacitance by effectively reducing the signal swing on the parasitic capacitor 428 by swinging the voltage on the base terminal 444 with the voltage at the output of the current mirror arrangement 400 (e.g., the voltage on resistor 224).

In the arrangement shown in fig. 4, transistor Q2 is a cascode transistor, and transistor Q3 is a cascode transistor, thus forming a cascode. By having transistor Q2 in a common emitter configuration and transistor Q3 in a common base configuration, with a bias voltage Vref coupled to the bias terminal 334 of transistor Q3, transistor Q3 may maintain the voltage at the collector terminal 120 of transistor Q2 substantially constant, thereby providing an improvement in reducing or eliminating the miller effect described above.

The bias voltages Vref and Vref1 may be selected such that the quiescent base-collector voltages of transistors Q3 and Q4 are substantially equal. Providing such bias voltages Vref and Vref1 may help ensure that the base-collector capacitances 328 and 428 of transistors Q3 and Q4 are substantially equal.

The impedance of the two-terminal passive network 450 may be selected such that the base terminal voltage swing of transistor Q4 is substantially equal to one-half of the output swing at the frequency of interest. Since the voltage at the emitter terminal 442 of the transistor Q4 will follow its base voltage, the same signal (i.e., approximately half of the output swing) appears at the collector terminal 330 of the transistor Q3.

In such a configuration, the signal swing across base-collector capacitors 428 and 328 is half that in the cascaded current mirror 300 shown in fig. 3. Thus, the corresponding third order nonlinear current is reduced by a factor of 8. The amount of non-linear base-collector junction capacitance in the current mirror arrangement 400 of fig. 4 is doubled compared to the cascaded current mirror 300 shown in fig. 3 (since now transistor Q4 contributes base-collector junction capacitance 428 in addition to base-collector junction capacitance 328 of transistor Q3). Thus, overall third order non-linear current due to the base-collector parasitic capacitors in the current mirror arrangement 400 of fig. 4 may be reduced by only a factor of 4 compared to the cascaded current mirror 300 shown in fig. 3. However, a factor of 4 still provides a significant improvement in linearity.

The explanation provided above assumes that the base-collector junction parasitic capacitances of transistors Q3 and Q4 are equal. However, even if the two base-collector capacitors are not equal, the semi-cascade described herein is still effective, for example, due to considerations of headroom, and the overall third order nonlinear current is reduced due to the base-collector junction parasitic capacitance at the output. In this case, the impedance of the two-terminal passive network 450 may change accordingly, but is still selected such that the resulting base voltage swing of transistor Q4 substantially eliminates output nonlinear distortion at the frequency of interest.

To summarize the current mirror arrangement 400, the arrangement comprises a current mirror circuit formed by an input transistor Q1 at the input of the current mirror circuit and an output transistor Q2 at the output of the current mirror circuit. The arrangement 400 further comprises: a semi-cascaded arrangement including transistors Q3 and Q4; and a two-terminal passive network 450. The transistor Q2 is in a common emitter configuration, while the transistor Q3 and the transistor Q4 are each in a common base configuration. The output of the transistor Q2 is coupled to the input of the transistor Q3, the output of the transistor Q3 is coupled to the input of the transistor Q4, and the output of the transistor Q4 is coupled to the output of the current mirror arrangement. Additionally, a base terminal of the transistor Q3 is coupled to a bias voltage Vref, a base terminal of the transistor Q4 is coupled to a first terminal of the two-terminal passive network, and a second terminal of the two-terminal passive network is coupled to the bias voltage Vref 1. The bias voltage Vref and the bias voltage Vref1 may be selected such that the quiescent voltage between the base terminal and the output of transistor Q3 is substantially equal to the quiescent voltage between the base terminal and the output of transistor Q4. For an input signal provided at the input of the current mirror arrangement 400 at a given frequency of interest, the impedance of the two-terminal passive network 450 may be such that the voltage swing at the base terminal of the transistor Q4 (where the output of the current mirror arrangement 400 may be, for example, the collector terminal of the transistor Q4) is substantially equal to half the voltage swing at the output of the current mirror arrangement 400 (where the input of the current mirror arrangement 400 may be, for example, the collector terminal of the transistor Q1). In this way, the transistors Q3 and Q4 are configured such that, at a given frequency of interest, the voltage at the base terminal of transistor Q4 and the voltage at the collector terminal of transistor Q3 vary accordingly as the voltage at the output of the current mirror arrangement 400 varies.

Although the description provided above with a single-stage, half-cascaded current mirror configuration refers to an NPN implementation of the transistors Q1-Q4 (i.e., all of the transistors Q1-Q4 are implemented as NPN transistors), in other embodiments, the transistors Q1-Q4 of the current mirror arrangement 400 may be implemented as PNP transistors. Fig. 5 provides a circuit diagram of a PNP implementation with a single-stage half-cascaded current mirror arrangement 500 according to some embodiments of the present disclosure. The current mirror arrangement 500 is substantially similar to the current mirror arrangement 400 except that each NPN transistor in the current mirror arrangement 400 is replaced by a PNP transistor in the current mirror arrangement 500 and the positive and negative power supplies 480, 482 are exchanged. In such a configuration, the description provided with reference to fig. 4 applies to the current mirror arrangement 500, except that NPN and PNP transistors are swapped and the power supply and current directions are reversed. The names such as "first/base terminal", "second/collector terminal", and "third/emitter terminal" remain the same. For the sake of brevity, a detailed description of FIG. 5 is not provided, as it is substantially similar to the description of FIG. 4, except for the modifications noted above.

The above-described half-cascade method can be generalized to M cascades to further reduce the total third-order nonlinear current at the output by M²And (4) doubling.

Fig. 6 provides a circuit diagram of an NPN implementation of a current mirror arrangement 600 having a plurality of half-cascaded stages according to some embodiments of the present disclosure.

The current mirror arrangement 600 includes all of the elements shown in fig. 4, and for the sake of brevity, the description thereof will not be repeated here. In contrast to the arrangement of fig. 4, which includes only a single half-cascaded stage of transistor Q4 and two-terminal passive network 450, current mirror arrangement 600 includes M such half-cascaded stages, where M may be any integer greater than 1. The first cascaded half-stage of the current mirror arrangement 600 includes a transistor Q4 and a two-terminal passive network 450. Fig. 6 then shows two columns, 3 dots each, showing that additional semi-cascaded stages may be included therein, each semi-cascaded stage being substantially identical to the first semi-cascaded stage. Fig. 6 further shows the last mth half-cascaded stage, which includes transistor QM +3 and two-terminal passive network 650. The symbol "M + 3" in the transistors of the mth semi-cascaded stage indicates that, for example, if the current mirror arrangement 600 includes 2 semi-cascaded stages, i.e., M2, the transistor of the last stage will be the transistor Q5 (i.e., M + 32 + 3-5) or, for example, if the current mirror arrangement 600 includes 3 semi-cascaded stages, i.e., M3, the transistor of the last stage will be the transistor Q6 (i.e., M + 3-3 + 3-6), and so on. The transistor Q in each of the M half-cascaded stages may be substantially identical to the transistor Q3 in the first half-cascaded stage, and the two-terminal passive network in each of the M half-cascaded stages may be substantially identical to the two-terminal passive network 450 of the first half-cascaded stage, except for the differences described below.

Consider that i is a variable that identifies a given half-cascaded stage of the current mirror arrangement 600, i.e., i is an integer equal to or greater than 1 and equal to or less than M. Then for i-1 (i.e., for the first half-cascaded stage of the current mirror arrangement 600), the transistor of stage i (i.e., stage 1) is transistor Q4 and the two-terminal passive network of stage i (i.e., stage 1) is the two-terminal passive network 450. For i >1, the base terminal of the transistor Qi of stage i is coupled to a first terminal of the two-terminal passive network of stage i, the second terminal of the two-terminal passive network of stage i is coupled to the respective bias voltage Vrefi of stage i, the emitter terminal of the transistor Qi of stage i is coupled to the collector terminal of the transistor Qi-1 of stage i-1. Further, for i < M, the collector terminal of transistor Qi of stage i is coupled to the emitter terminal of transistor Qi +1 of stage i +1, and the collector terminal of transistor QM +3 of stage M is coupled to the output of current mirror arrangement 600. In such an arrangement, for any i between 1 and M (including i-1 and i-M), the impedance of the two-terminal passive network of stage i is such that the voltage swing at the base terminal of the transistor Qi of stage i is substantially equal to i × VO/(M +1), where VO is the voltage swing at the output of the current mirror arrangement 600 at a given frequency of interest for providing the input signal at the input of the current mirror arrangement. In some embodiments, the respective bias voltages of different cascaded stages may be such that the static base-collector voltages of the transistors of the different stages are equal.

Although the description of the current mirror arrangement with multiple half-cascaded stages provided above refers to NPN implementations of the transistors of the current mirror circuit and the transistors of the half-cascaded arrangement (i.e., all transistors Q1-QM +3 are implemented as NPN transistors), in other embodiments, the current mirror arrangement 600 may be implemented as PNP transistors. Fig. 7 provides a circuit diagram of a PNP implementation of a current mirror arrangement 700 having a plurality of half-cascaded stages, according to some embodiments of the present disclosure. The current mirror arrangement 700 is substantially similar to the current mirror arrangement 600 except that each NPN transistor in the current mirror arrangement 600 is replaced by a PNP transistor in the current mirror arrangement 700 and the positive and negative power supplies 480, 482 are swapped. In such a configuration, the description provided with reference to fig. 6 applies to the current mirror arrangement 700, except that the NPN and PNP transistors are swapped and the power supply and current directions are reversed. The names such as "first/base terminal", "second/collector terminal", and "third/emitter terminal" remain the same. For the sake of brevity, a detailed description of FIG. 7 is not provided, as it is substantially similar to FIG. 6, except for the modifications noted above.

Variants and implementations

Although the description provided above refers to a bipolar implementation of transistors, in other embodiments, any current mirror arrangement having a half-cascade as described herein may include FETs. In particular, in a further embodiment as described herein with any current mirror arrangement in half-cascade, each NPN transistor may be replaced by an NMOS transistor and each PNP transistor may be replaced by a PMOS transistor. In such embodiments, the description provided above with reference to the drawings with a bipolar transistor applies, except that the "first terminal" or "base terminal" of the bipolar transistor becomes the "gate terminal" of the FET, the "second terminal" or "collector terminal" of the bipolar transistor becomes the "drain terminal" of the FET, and the "third terminal" or "emitter" of the bipolar transistor becomes the "source terminal" of the FET.

In an example embodiment, any number of the circuits of the present figures may be implemented on a board of an associated electronic device. The board may be a universal circuit board that may house various components of the internal electronics system of the electronic device, and may also provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system may electrically communicate. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc. may be suitably coupled to the board based on particular configuration needs, processing needs, computer design, etc. Other components, such as external memory, additional sensors, controls for audio/video display and peripherals, may be connected to the board as plug-in cards via cables, or may be integrated into the board.

In another example embodiment, the circuitry of the present figure may be implemented as a standalone module (e.g., a device with associated components and circuitry configured to perform particular applications or functions) or as a plug-in module in dedicated hardware of an electronic device. Note that certain embodiments of the present disclosure relating to partially semi-cascaded current mirror arrangements may be readily included, partially or wholly, in a system-on-a-chip (SOC) package. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal and often radio frequency functions: all of these functions may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package. In various other embodiments, the functionality of the particular semi-cascaded current mirror arrangement presented herein may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips. .

Example System with semi-cascaded Current mirror arrangement

The various embodiments described above with a semi-cascaded current mirror arrangement may be implemented in any kind of system in which current mirrors may be used. Such a current mirror arrangement is particularly useful in systems requiring a current mirror having both high linearity and a wide signal bandwidth. One example of such a system is shown in fig. 8, which provides a schematic diagram of a system 800 implementing a current mirror arrangement 812, according to some embodiments of the present disclosure. As shown in fig. 8, system 800 may include an ADC driver 810 and an ADC 820. The ADC driver 810 may be used to provide a drive signal to drive the ADC 820 so that the ADC 820 may convert the analog electrical signal to digital form, for example for data processing purposes. In particular, the ADC driver 810 may comprise a current mirror arrangement 812, which current mirror arrangement 812 may be implemented according to any implementation of the specific semi-cascaded current mirror arrangement described above. For example, as described above, the current mirror arrangement 812 may be implemented as the current mirror arrangement 400, 500, 600, or 700, or as any other embodiment of these current mirror arrangements. The ADC driver 810 may then generate a drive signal based on the output signal generated by the current mirror arrangement 812. In various embodiments, the drive signal generated by the ADC driver 810 may be used to drive a single or double differential input of the ADC 820.

In various embodiments, the drive signals generated by the ADC driver 810 may implement/realize functions such as buffering, amplitude scaling, single-ended to differential and differential to single-ended conversion, common-mode offset adjustment, and filtering. In other words, ADC driver 810 may act as a signal conditioning element in the data conversion stage and may be a key factor in enabling ADC 820 to achieve its desired performance. ADC 820 may be any type of ADC, such as, but not limited to, a Successive Approximation Register (SAR) converter, a pipeline converter, a flash memory converter, or a sigma-delta converter.

The system 800 shown in fig. 8 provides only one non-limiting example in which a current mirror arrangement as described herein may be used, and the various teachings relating to a current mirror arrangement having a half cascade as described herein are applicable to a variety of other systems. In some cases, various embodiments as described herein having a semi-cascaded current mirror arrangement may be used in automotive systems, safety critical industrial applications, medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be very accurate), and various digital processing based systems. In other cases, various embodiments having semi-cascaded current mirror arrangements as described herein may be used in an industrial market that includes process control systems that help to improve productivity, energy efficiency, and reliability. In further scenarios, various embodiments having semi-cascaded current mirror arrangements may be used in consumer applications.

Selection example

The following paragraphs provide examples of the various embodiments disclosed herein.

Example 1 provides a current mirror arrangement comprising a current mirror circuit and a circuit referred to herein as a "semi-cascaded arrangement". The current mirror circuit includes a transistor Q1 at an input of the current mirror circuit and a transistor Q2 at an output of the current mirror circuit. The semi-cascaded arrangement includes a transistor Q3, a transistor Q4, and a two-terminal passive network PN, including one or more resistors, capacitors, and inductors. Each of the transistors Q1, Q2, Q3, and Q4 has a first terminal, a second terminal, and a third terminal. A first terminal of the transistor Q1 is coupled to a first terminal of the transistor Q2 and to a second terminal of the transistor Q1. A second terminal of the transistor Q2 is coupled to a third terminal of the transistor Q3. A second terminal of the transistor Q3 is coupled to a third terminal of the transistor Q4. A first terminal of the transistor Q3 is coupled to a bias voltage Vref. A first terminal of the transistor Q4 is coupled to a first terminal of the two-terminal passive network PN, and a second terminal of the two-terminal passive network PN is coupled to a bias voltage Vref 1.

Example 2 provides the current mirror arrangement according to example 1, wherein the bias voltage Vref and the bias voltage Vref1 are such that the quiescent voltage between the first and second terminals of transistor Q3 (i.e., the voltage when no input signal is applied, e.g., the voltage when no input signal is applied to the input of the current mirror) is substantially equal to the quiescent voltage between the first and second terminals of transistor Q4.

Example 3 provides a current mirror arrangement according to example 1 or 2, wherein the impedance of the two-terminal passive network PN is such that the voltage swing at the first terminal of the transistor Q4 is substantially equal to half the voltage swing at the output of the current mirror arrangement for an input signal provided at the input of the current mirror arrangement at a given frequency of interest.

Example 4 provides a current mirror arrangement according to example 1 or 2, wherein the current mirror arrangement includes M stages, where M is an integer greater than 1, each stage i of the M stages includes a respective set of transistors and a two-terminal passive network (i.e., other examples of a), where i is an integer between 1 and M (i.e., stage 1, …, etc., up to each of stages M), and the transistors of each stage i have a first terminal, a second terminal, and a third terminal. For i-1, the transistor of stage i (i.e., stage 1) is transistor Q4 and the two-terminal passive network of stage i (i.e., stage 1) is the two-terminal passive network PN. For i >1, a first terminal of the transistor of stage i is coupled to a first terminal of the two-terminal passive network of stage i, a second terminal of the two-terminal passive network of stage i is coupled to the respective bias voltage Vrefi of stage i, and a third terminal of the transistor of stage i is coupled to a second terminal of the transistor of stage i-1.

Example 5 provides the current mirror arrangement of example 4, wherein for i < M, a second terminal of the transistor of stage i is coupled to a third terminal of the transistor of stage i +1, and a second terminal of the transistor of stage M is coupled to an output of the current mirror arrangement.

Example 6 provides a current mirror arrangement according to example 4 or 5, wherein for any i between 1 and M, the impedance of the two-terminal passive network of stage i is such that the voltage swing at the first terminal of the transistor of stage i is substantially equal to i x VO/(M +1), where VO is the voltage swing at the output of the current mirror arrangement for the input signal provided at the input of the current mirror arrangement at the given frequency of interest.

Example 7 provides the current mirror arrangement of any of examples 1-6, wherein for each transistor Q1, Q2, Q3, and Q4, the first terminal is a base terminal, the second terminal is a collector terminal, and the third terminal is an emitter terminal.

Example 8 provides a current mirror arrangement according to example 7, wherein the emitter area of each transistor Q2, Q3, and Q4 is K times the emitter area of the transistor Q1, where K is a positive number (any number greater than 0). Therefore, K is the current gain of the current mirror circuit.

Example 9 provides the current mirror arrangement of any of examples 1-6, wherein for each transistor Q1, Q2, Q3, and Q4, the first terminal is a gate terminal, the second terminal is a drain terminal, and the third terminal is a source terminal.

Example 10 provides a current mirror arrangement according to example 9, wherein the aspect ratio of each transistor Q2, Q3, and Q4 is K times the aspect ratio of the transistor Q1, where K is a positive number.

Example 11 provides the current mirror arrangement according to any of the preceding examples, wherein the second terminal of the transistor Q1 is coupled to an input of the current mirror circuit, and the second terminal of the transistor Q2 is coupled to an output of the current mirror circuit.

Example 12 provides a current mirror arrangement comprising a current mirror circuit and a semi-cascaded arrangement. The current mirror circuit includes a transistor Q1 at an input of the current mirror circuit and a transistor Q2 at an output of the current mirror circuit. The semi-cascaded arrangement includes a transistor Q3, a transistor Q4, and a two-terminal passive network. In this current mirror arrangement, the transistor Q2 is in a common emitter configuration, the transistor Q3 and the transistor Q4 are each in a common base configuration, the output of the transistor Q2 is coupled to the input of the transistor Q3, the output of the transistor Q3 is coupled to the input of the transistor Q4, the output of the transistor Q4 is coupled to the output of the current mirror arrangement, the base terminal of the transistor Q3 is coupled to a bias voltage Vref, the base terminal of the transistor Q4 is coupled to a first terminal of the two-terminal passive network, and the second terminal of the two-terminal passive network is coupled to the bias voltage Vref 1.

Example 13 provides the current mirror arrangement of example 12, wherein the bias voltage Vref and the bias voltage Vref1 are such that a quiescent voltage between the base terminal and the output of the transistor Q3 is substantially equal to a quiescent voltage between the base terminal and the output of the transistor Q4.

Example 14 provides the current mirror arrangement of example 12 or 13, wherein the two-terminal passive network includes one or more resistors, capacitors, and inductors.

Example 15 provides the current mirror arrangement of any of examples 12-14, wherein the impedance of the two-terminal passive network is such that, for an input signal provided at the input of the current mirror arrangement, at a given frequency of interest, the voltage swing at the base terminal of the transistor Q4 is substantially equal to half the voltage swing at the output of the current mirror arrangement.

Example 16 provides a current mirror arrangement comprising a current mirror circuit having a transistor Q1 at an input of the current mirror circuit and a transistor Q2, a transistor Q3, and a transistor Q4 at an output of the current mirror circuit. In this current mirror arrangement, each of the transistors Q1, Q2, Q3 and Q4 has a first terminal, a second terminal and a third terminal, the input of the transistor Q3 is coupled to the output of the current mirror circuit, the input of the transistor Q4 is coupled to the output of the transistor Q3, the output of the transistor Q4 is coupled to the output of the current mirror arrangement, and the transistors Q3 and Q4 are configured such that, at a given frequency of interest, the voltage at the first terminal of the transistor Q4 and the voltage at the second terminal of the transistor Q3 vary accordingly with variations in the voltage at the output of the current mirror arrangement.

Example 17 provides the current mirror arrangement of example 16, wherein the transistor Q3 is cascaded with the transistor Q2.

Example 18 provides the current mirror arrangement of example 16 or 17, wherein the transistor Q4 is cascaded with the transistor Q3.

Example 19 provides the current mirror arrangement of any of examples 16-18, further comprising a two-terminal passive network, wherein a first terminal of the two-terminal passive network is coupled to the transistor Q4 and a second terminal of the two-terminal passive network is coupled to a bias voltage Vref 1.

Example 20 provides the current mirror arrangement of example 19, wherein the transistor Q3 is coupled to a second bias voltage Vref, and the bias voltage Vref1 are such that a quiescent voltage between a terminal of the transistor Q3 coupled to the bias voltage Vref and the output of the transistor Q3 is substantially equal to a quiescent voltage between a terminal of the transistor Q4 coupled to the bias voltage Vref1 and the output of the transistor Q4.

Example 21 provides an electronic device comprising an ADC configured to perform analog-to-digital conversion; further comprising an ADC driver configured to provide a drive signal to the ADC to enable the ADC to perform an analog-to-digital conversion, the ADC driver comprising a current mirror arrangement according to any of the preceding examples.

Example 22 provides the electronic device of example 21, wherein the electronic device is or is included in an automatic test equipment, a military radar/LIDAR, a civilian radar/LIDAR, an automotive radar/LIDAR, an industrial radar/LIDAR, a cellular base station, a high-speed wired or wireless communication transceiver, or a high-speed digital control system.

Example 23 provides an ADC system, including an ADC configured to perform analog-to-digital conversion; an ADC driver configured to provide a drive signal to the ADC to enable the ADC to perform analogue to digital conversion, the ADC driver comprising a current mirror arrangement according to any of the preceding examples.

In other embodiments, the current mirror arrangement according to any of the preceding examples may be incorporated in other kinds of components of the electronic device than being comprised in the ADC driver. Examples of other components that may be combined with the current mirror arrangement according to any of the preceding examples include amplifiers, mixers and filters, e.g. high speed amplifiers, high speed mixers and high speed filters. Such components, in turn, may be included in devices such as automatic test equipment, military radar/LIDAR, civilian radar/LIDAR, automotive radar/LIDAR, industrial radar/LIDAR, cellular base stations, high-speed wired or wireless communication transceivers, or high-speed digital control systems.