阅读说明：本技术 一种栅极及其制作方法 (Grid and manufacturing method thereof ) 是由 罗清威 李赟 周俊 于 2019-09-29 设计创作，主要内容包括：本发明提供了一种栅极及其制作方法,对N型区域内的所述栅极多晶硅层进行N型掺杂之后,对所述N型区域与P型区域内的所述栅极多晶硅层进行离子掺杂,使所述栅极多晶硅层非晶化,使得所述N型区域与所述P型区域内的所述栅极多晶硅层在刻蚀之前的表面晶体结构一致,从而改善所述N型区域与所述P型区域内的所述栅极多晶硅层在刻蚀过程中的形貌差异,以此改善多晶硅蚀刻负载效应,提高器件性能。(The invention provides a grid and a manufacturing method thereof, wherein after the grid polycrystalline silicon layer in an N-type region is subjected to N-type doping, the grid polycrystalline silicon layer in the N-type region and a P-type region is subjected to ion doping, so that the grid polycrystalline silicon layer is amorphized, the surface crystal structures of the grid polycrystalline silicon layer in the N-type region and the grid polycrystalline silicon layer in the P-type region before etching are consistent, the appearance difference of the grid polycrystalline silicon layer in the N-type region and the grid polycrystalline silicon layer in the P-type region in the etching process is improved, the polycrystalline silicon etching load effect is improved, and the device performance is improved.)

1. A method for manufacturing a gate electrode is characterized by comprising the following steps:

providing a substrate, sequentially forming a gate oxide layer and a grid polycrystalline silicon layer on the substrate, wherein the grid polycrystalline silicon layer comprises an N-type region and a P-type region, and carrying out N-type doping on the grid polycrystalline silicon layer in the N-type region;

carrying out ion doping on the grid polycrystalline silicon layer in the N-type region and the P-type region to make the grid polycrystalline silicon layer amorphous;

and etching the grid polysilicon layer to form an N-type polysilicon grid and a P-type polysilicon grid.

2. The method of claim 1, wherein the gate polysilicon layer in the N-type region and the P-type region is doped with germanium ions, silicon ions or argon ions.

3. The method of claim 2, wherein the germanium ion is doped at a dose of 1E14/cm²～1E16/cm²In the meantime.

4. The method of claim 1, wherein the step of etching the gate polysilicon layer to form an N-type polysilicon gate and a P-type polysilicon gate comprises:

forming a photoresist layer on the grid polycrystalline silicon layer, and patterning the photoresist layer to define an N-type polycrystalline silicon grid pattern and a P-type polycrystalline silicon grid pattern;

etching the grid polysilicon layer by taking the graphical photoresist layer as a mask to form an N-type polysilicon grid and a P-type polysilicon grid;

and removing the patterned photoresist layer.

5. The method of claim 1, wherein after etching the gate polysilicon layer to form an N-type polysilicon gate and a P-type polysilicon gate, further comprising: and performing high-temperature annealing to activate N-type doping in the N-type polysilicon gate, so that doping ions are uniformly distributed in the N-type polysilicon gate.

6. The method of claim 1, wherein the N-type dopant is a boron ion dopant.

7. The method of claim 1 wherein the gate oxide layer is silicon oxide or silicon oxynitride or a mixture of silicon oxide and silicon oxynitride.

8. The method of claim 1, wherein the substrate comprises an N-type active region and a P-type active region, and the N-type polysilicon gate and the P-type polysilicon gate are formed over the N-type active region and the P-type active region, respectively.

9. A gate electrode, comprising:

a substrate;

the grid electrode oxide layer is positioned on the substrate, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are positioned on the grid electrode oxide layer, wherein N-type doping is distributed in the N-type polycrystalline silicon grid electrode, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are both in an amorphous state.

10. The gate of claim 9, wherein the N-type and P-type polysilicon gates are doped with germanium ions, silicon ions, or argon ions.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a grid and a manufacturing method thereof.

Background

With the continuous reduction of the device size, the gate size is smaller and smaller, and in order to match the reduction of the gate size, the photolithography process and the etching process need to be continuously optimized and upgraded.

The existing polysilicon gate forming process is to perform one-step doping after forming a polysilicon layer, for example, N-type doping is performed, so that an N-type polysilicon region and a P-type polysilicon region have different doping, and the surface of the N-type polysilicon region is changed from a crystalline state to an amorphous state due to the higher concentration of the N-type doping, while the P-type polysilicon region is still in a crystalline state, i.e., the doping can cause the crystalline states of the surfaces of the N-type and P-type polysilicon layers to be different, so that the difference of etching appearances can be caused when the N-type and P-type polysilicon gates are formed by etching, and the polysilicon etching load effect is caused.

Therefore, it is desirable to provide a gate and a method for fabricating the same to solve the above-mentioned problems.

Disclosure of Invention

Based on the above problems, an object of the present invention is to provide a gate and a method for fabricating the same, which can improve the polysilicon etching loading effect and improve the device performance.

In order to achieve the above object, the present invention provides a method for manufacturing a gate, including:

providing a substrate, sequentially forming a gate oxide layer and a grid polycrystalline silicon layer on the substrate, wherein the grid polycrystalline silicon layer comprises an N-type region and a P-type region, and carrying out N-type doping on the grid polycrystalline silicon layer in the N-type region;

carrying out ion doping on the grid polycrystalline silicon layer in the N-type region and the P-type region to make the grid polycrystalline silicon layer amorphous;

and etching the grid polysilicon layer to form an N-type polysilicon grid and a P-type polysilicon grid.

Optionally, in the method for manufacturing the gate, germanium ions, silicon ions, or argon ions are doped into the gate polysilicon layer in the N-type region and the P-type region.

Optionally, in the method for manufacturing the gate, the dopant amount of the germanium ions is between 1E14/cm²～1E16/cm²In the meantime.

Optionally, in the method for manufacturing the gate, the step of etching the gate polysilicon layer to form the N-type polysilicon gate and the P-type polysilicon gate includes:

forming a photoresist layer on the grid polycrystalline silicon layer, and patterning the photoresist layer to define an N-type polycrystalline silicon grid pattern and a P-type polycrystalline silicon grid pattern;

etching the grid polysilicon layer by taking the graphical photoresist layer as a mask to form an N-type polysilicon grid and a P-type polysilicon grid;

and removing the patterned photoresist layer.

Optionally, in the method for manufacturing the gate, after the gate polysilicon layer is etched to form an N-type polysilicon gate and a P-type polysilicon gate, the method further includes: and performing high-temperature annealing to activate N-type doping in the N-type polysilicon gate, so that doping ions are uniformly distributed in the N-type polysilicon gate.

Optionally, in the method for manufacturing the gate, the N-type doping is boron ion doping.

Optionally, in the manufacturing method of the gate electrode, the gate oxide layer is silicon oxide or silicon oxynitride or a mixture of silicon oxide and silicon oxynitride.

Optionally, in the gate manufacturing method, the substrate includes an N-type active region and a P-type active region, and the N-type polysilicon gate and the P-type polysilicon gate are formed above the N-type active region and the P-type active region, respectively.

Correspondingly, the invention also provides a gate comprising:

a substrate;

the grid electrode oxide layer is positioned on the substrate, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are positioned on the grid electrode oxide layer, wherein N-type doping is distributed in the N-type polycrystalline silicon grid electrode, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are both in an amorphous state.

Optionally, in the gate, germanium ions, silicon ions or argon ions are doped in the N-type polysilicon gate and the P-type polysilicon gate.

Compared with the prior art, in the grid and the manufacturing method thereof provided by the invention, after the grid polycrystalline silicon layer in the N-type region is subjected to N-type doping, the grid polycrystalline silicon layer in the N-type region and the grid polycrystalline silicon layer in the P-type region are subjected to ion doping, so that the surface of the grid polycrystalline silicon layer is amorphized, the surface crystal structures of the grid polycrystalline silicon layer in the N-type region and the grid polycrystalline silicon layer in the P-type region before etching are consistent, the shape difference of the grid polycrystalline silicon layer in the N-type region and the grid polycrystalline silicon layer in the P-type region in the etching process is improved, the polycrystalline silicon etching load effect is improved, and the device performance is improved.

Drawings

FIGS. 1-4 are schematic structural diagrams of steps of a gate fabrication method.

Fig. 5 is a flowchart of a method for manufacturing a gate according to an embodiment of the invention.

Fig. 6 to 10 are schematic structural diagrams of steps of a method for manufacturing a gate according to an embodiment of the invention.

Detailed Description

FIGS. 1-4 are schematic structural diagrams of steps of a gate fabrication method. Referring to fig. 1 to 4, the gate fabrication method is as follows.

First, referring to fig. 1, a substrate 10 is provided, a gate oxide layer 11 and a gate polysilicon layer 12 are sequentially formed on the substrate 10, the gate polysilicon layer 12 includes an N-type region 12B and a P-type region 12A, and then the gate polysilicon layer 12 in the N-type region 12B is N-doped, for example, boron ion doped.

Next, referring to fig. 2, a photoresist layer is formed on the gate polysilicon layer 12, and the photoresist layer covers the N-type region 12B and the P-type region 12A. Then, the photoresist layer is patterned, i.e., exposed and developed, to form a patterned photoresist layer 13. The patterned photoresist layer 13 defines an N-type polysilicon gate pattern and a P-type polysilicon gate pattern.

Next, referring to fig. 2 and 3, the patterned photoresist layer 13 is used as a mask to etch the gate polysilicon layer 12 to form an N-type polysilicon gate 15 and a P-type polysilicon gate 14, and then the patterned photoresist layer 13 is removed.

Finally, referring to fig. 4, a high temperature anneal is performed to activate the N-type doping in the N-type polysilicon gate 15, so that the doped ions are uniformly distributed in the N-type polysilicon gate 15.

In the above etching step, since the gate polysilicon layer 12 in the N-type region 12B is N-doped, the surface of the gate polysilicon layer 12 in the N-type region 12B becomes amorphous, and the gate polysilicon layer 12 in the P-type region 12A is not doped, and the surface thereof is in a crystalline state, so that the crystalline states of the surfaces of the gate polysilicon layer 12 in the N-type region 12B and the P-type region 12A are different, thereby causing a difference in etching profile and a polysilicon etching loading effect.

Based on the above problems, the present invention provides a method for manufacturing a gate, including: providing a substrate, sequentially forming a gate oxide layer and a grid polycrystalline silicon layer on the substrate, wherein the grid polycrystalline silicon layer comprises an N-type region and a P-type region, and carrying out N-type doping on the grid polycrystalline silicon layer in the N-type region; carrying out ion doping on the grid polycrystalline silicon layer in the N-type region and the P-type region to make the grid polycrystalline silicon layer amorphous; and etching the grid polysilicon layer to form an N-type polysilicon grid and a P-type polysilicon grid.

Correspondingly, the invention also provides a gate comprising: a substrate; the grid electrode oxide layer is positioned on the substrate, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are positioned on the grid electrode oxide layer, wherein N-type doping is distributed in the N-type polycrystalline silicon grid electrode, and the N-type polycrystalline silicon grid electrode and the P-type polycrystalline silicon grid electrode are both in an amorphous state.

In the grid and the manufacturing method thereof provided by the invention, after the grid polycrystalline silicon layer in the N-type area is subjected to N-type doping, the grid polycrystalline silicon layer in the N-type area and the grid polycrystalline silicon layer in the P-type area are subjected to ion doping, so that the surface of the grid polycrystalline silicon layer is amorphized, the surface crystal structures of the grid polycrystalline silicon layer in the N-type area and the grid polycrystalline silicon layer in the P-type area before etching are consistent, the shape difference of the grid polycrystalline silicon layer in the N-type area and the grid polycrystalline silicon layer in the P-type area in the etching process is improved, the polycrystalline silicon etching load effect is improved, and the device performance is improved.

In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.

It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.

Fig. 5 is a flowchart of a method for manufacturing a gate according to an embodiment of the invention. Fig. 6 to 10 are schematic structural diagrams of steps of a method for manufacturing a gate according to an embodiment of the invention. The following describes each step of the method for manufacturing a gate in this embodiment in detail with reference to fig. 5 and fig. 6 to 10.

In step S100, please refer to fig. 5 and 6, a substrate 100 is provided, a gate oxide layer 110 and a gate polysilicon layer 120 are sequentially formed on the substrate 100, the gate polysilicon layer 120 includes an N-type region 120B and a P-type region 120A, and the gate polysilicon layer 120 in the N-type region 120B is N-doped.

The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In the present embodiment, the material of the substrate 100 is preferably single crystal silicon (Si).

First, a gate oxide layer 110 is formed on the substrate 100, and the gate oxide layer 110 is made of silicon oxide or silicon oxynitride or a mixture of silicon oxide and silicon oxynitride, and may be formed by a thermal oxidation method (only silicon oxide) or a chemical vapor deposition method. Next, a gate polysilicon layer 120 is formed on the gate oxide layer 110, the gate polysilicon layer 120 is made of polysilicon, and the gate polysilicon layer 120 may be formed by using methods such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. The gate polysilicon layer 120 includes an N-type region 120B and a P-type region 120A, the P-type region 120A is used for forming a P-type polysilicon gate, and the N-type region 120B is used for forming an N-type polysilicon gate.

The gate polysilicon layer 120 in the N-type region 120B is then N-doped. In this embodiment, boron ion doping is preferable. The doping operation is performed by an ion implantation process, which may be any conventional method, and is not limited in this respect.

In step S200, please refer to fig. 5 and 7, the gate polysilicon layer 120 in the N-type region 120B and the P-type region 120A is ion-doped 130, so that the gate polysilicon layer 120 is amorphized. The ion doping 130 may be germanium ion, silicon ion, or argon ion doping.

In the embodiment of the present invention, germanium ions are doped into the gate polysilicon layer 120 in the N-type region 120B and the P-type region 120A, and the doping dose of the germanium ions is between 1E14/cm²～1E16/cm²In between, for example, the germanium ion is doped at a dose of 1E14/cm²、1E15/cm²Or 1E16/cm²。

After germanium ion doping, the gate polysilicon layer 120 in the N-type region 120B and the P-type region 120A are amorphized, so that the difference caused by the fact that the gate polysilicon layer 120 in the N-type region 120B is N-doped and the gate polysilicon layer 120 in the P-type region 120A is not doped is eliminated, the surface crystal structures of the gate polysilicon layer 120 in the N-type region 120B and the gate polysilicon layer 120 in the P-type region 120A before etching are consistent and are in an amorphous state, and the morphology difference caused in the subsequent etching process can be avoided.

In step S300, please refer to fig. 5 and 9, the gate polysilicon layer 120 is etched to form the N-type polysilicon gate 160 and the P-type polysilicon gate 150.

First, referring to fig. 8, a photoresist layer (not shown) is formed on the gate polysilicon layer 120, wherein the photoresist layer covers the N-type region 120B and the P-type region 120A. Then, the photoresist layer is patterned, that is, the photoresist layer is exposed and developed to form a patterned photoresist layer 140, and the patterned photoresist layer 140 defines an N-type polysilicon gate pattern and a P-type polysilicon gate pattern. Then, the patterned photoresist layer is used as a mask to etch the gate polysilicon layer 120 to form an N-type polysilicon gate 160 and a P-type polysilicon gate 150, and finally, an ashing process is used to remove the patterned photoresist layer 140, so as to form the structure shown in fig. 9.

The surface crystal structures of the gate polysilicon layer 120 in the N-type region 120B and the P-type region 120A are the same, and the etching in this step can avoid the morphology difference between the N-type polysilicon gate 160 and the P-type polysilicon gate 150, thereby improving the polysilicon etching load effect and improving the device performance.

In the embodiment of the present invention, the method further includes: a high temperature anneal is performed to activate the N-type doping in the N-type polysilicon gate 160, so that the doped ions are uniformly distributed in the N-type polysilicon gate, i.e., the boron ions doped in step S100 are uniformly distributed in the N-type polysilicon gate 160. Meanwhile, due to the high temperature annealing, the ions (germanium ions in the present embodiment) doped in step S200 are uniformly distributed in the N-type polysilicon gate 160 and the P-type polysilicon gate 150, as shown in fig. 10.

It is understood that the substrate 100 includes an N-type active region (not shown) and a P-type active region (not shown), and the N-type polysilicon gate 160 and the P-type polysilicon gate 150 are formed over the N-type active region and the P-type active region, respectively.

Of course, the following steps include P-type doping of the P-type polysilicon gate, formation of a source/drain, a side wall, and the like, which are not described in detail herein.

In the method for manufacturing the gate provided by the invention, after the gate polysilicon layer 120 in the N-type region 120B is subjected to N-type doping, the gate polysilicon layer 120 in the N-type region 120B and the P-type region 120A is subjected to ion doping, so that the surface of the gate polysilicon layer 120 is amorphized, the surface crystal structures of the gate polysilicon layer 120 in the N-type region 120B and the gate polysilicon layer 120 in the P-type region 120A before etching are consistent, and the morphology difference between the gate polysilicon layer 120 in the N-type region 120B and the gate polysilicon layer 120 in the P-type region 120A during etching is improved, thereby improving the polysilicon etching load effect and improving the device performance.

Correspondingly, the invention also provides a grid which can be manufactured by adopting the manufacturing method of the grid. Referring to fig. 10, the gate includes:

a substrate 100;

the gate structure includes a gate oxide layer 110 on the substrate 100, and an N-type polysilicon gate 160 and a P-type polysilicon gate 150 on the gate oxide layer 110, wherein N-type dopants are distributed in the N-type polysilicon gate 160, and the N-type polysilicon gate 160 and the P-type polysilicon gate 140 are both amorphous.

Preferably, the N-type polysilicon gate 160 and the P-type polysilicon gate 150 are doped with germanium ions, silicon ions or argon ions, so that the N-type polysilicon gate 160 and the P-type polysilicon gate 150 are in an amorphous state.

N-type doping, preferably boron ion doping, is distributed in the N-type polysilicon gate 160.

In summary, in the gate and the method for manufacturing the same provided by the present invention, after the gate polysilicon layer in the N-type region is N-doped, the gate polysilicon layer in the N-type region and the P-type region is ion-doped, so that the surface of the gate polysilicon layer is amorphized, and the surface crystal structures of the gate polysilicon layer in the N-type region and the P-type region before etching are consistent, thereby improving the morphology difference between the gate polysilicon layer in the N-type region and the P-type region during the etching process, so as to improve the polysilicon etching load effect and improve the device performance.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.