Semiconductor structure and forming method thereof
阅读说明:本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 周飞 于 2018-06-26 设计创作,主要内容包括:一种半导体结构及其形成方法,其中方法包括:提供基底,所述基底表面具有鳍部和隔离结构,所述隔离结构的顶部低于鳍部的顶部,且覆盖鳍部的部分侧壁;在所述隔离结构的顶部表面形成保护层;形成所述保护层之后,在所述鳍部底部掺入掺杂离子。所述方法形成的器件性能较好。(A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part; forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed. The device formed by the method has better performance.)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part;
forming a protective layer on the top surface of the isolation structure;
and doping ions at the bottom of the fin part after the protective layer is formed.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises: SiO 22SiOCN, SiBCN or SiOBCN.
3. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of: 50 to 200 angstroms.
4. The method of claim 1, wherein the substrate has a well region therein, the well region having trap ions therein, the trap ions being of opposite conductivity type to the dopant ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
5. The method of claim 1, wherein the gate structure crosses the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; the forming method of the protective layer comprises the following steps: forming protective films on the top surface of the isolation structure, the side wall and the top surface of the fin part and the side wall and the top surface of the grid structure; forming a first dielectric layer on the surface of the protective film, wherein the top surface of the first dielectric layer is lower than the top surface of the fin portion; and removing the protective film on the top of the fin part and the grid structure by taking the first dielectric layer as a mask to form the protective layer.
6. The method of forming a semiconductor structure of claim 5, wherein a material of the first dielectric layer comprises: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
7. The method of claim 5, wherein the first dielectric layer has a thickness of 200 to 500 angstroms.
8. The method of forming a semiconductor structure of claim 5, further comprising: and forming source and drain doped regions in the fin parts on two sides of the grid structure respectively, wherein source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions.
9. The method for forming a semiconductor structure according to claim 8, wherein after the protective layer is formed and before the source-drain doped region is formed, doping ions are doped at the bottom of the fin portion; or doping ions into the fin part at the bottom of the source-drain doped region after the protective layer and the source-drain doped region are formed.
10. The method for forming the semiconductor structure according to claim 8, wherein the dimension from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
11. The method for forming a semiconductor structure according to claim 8, wherein the doping concentration of the source and drain ions is: 1.0E 21-5.0E 21 atomic number/cubic centimeter.
12. The method for forming a semiconductor structure of claim 8, wherein after forming the source-drain doped regions and doping dopant ions at the bottom of the fin, the method further comprises: forming a second dielectric layer on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; forming a contact hole exposing the top surface of the source drain doped region in the second dielectric layer; and forming a plug in the contact hole.
13. A semiconductor structure, comprising:
the surface of the substrate is provided with a fin part and an isolation structure, and the top of the isolation structure is lower than the top of the fin part and covers part of the side wall of the fin part;
a protective layer on a top surface of the isolation structure;
dopant ions located within the bottom fin portion.
14. The semiconductor structure of claim 13, wherein a material of the protective layer comprises: SiO 22SiOCN, SiBCN or SiOBCN.
15. The semiconductor structure of claim 13, wherein the protective layer has a thickness of: 50 to 200 angstroms.
16. The semiconductor structure of claim 13, wherein said substrate has a well region therein, said well region having therein trap ions, said trap ions being of opposite conductivity type to the dopant ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
17. The semiconductor structure of claim 13, wherein the gate structure crosses the fin; the protective layer also covers the fin part and the side wall of the grid structure; source and drain doped regions are respectively arranged in the fin parts at two sides of the grid structure and the protective layer, source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions; the semiconductor structure further includes: the first dielectric layer is positioned on the surface of the protective layer, and the top surface of the first dielectric layer is lower than the top surface of the fin portion; the second dielectric layer is positioned on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; the contact hole is positioned in the second medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region; a plug located within the contact hole.
18. The semiconductor structure of claim 17, wherein a material of the first dielectric layer comprises: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
19. The semiconductor structure of claim 17, wherein the first dielectric layer has a thickness of 200 to 500 angstroms.
20. The semiconductor structure of claim 17, wherein the dimension from the top of the source drain doped region to the bottom of the source drain doped region is: 300 to 800 angstroms.
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
When the channel length is less than 100nm, in the conventional MOSFET, the source and drain regions interact with each other due to the semiconductor material of the semiconductor substrate surrounding the active region, the distance between the drain and the source is also shortened, and a short channel effect is generated, so that the control capability of the gate on the channel is deteriorated, the difficulty of pinch-off of the gate voltage on the channel is increased, and the Sub-threshold leakage (Sub-threshold leakage) phenomenon is more likely to occur.
A Fin Field effect transistor (FinFET) is a new type of metal oxide semiconductor Field effect transistor, and its structure is usually formed on a silicon-on-insulator (SOI) substrate, and includes narrow and isolated silicon strips (i.e., vertical channel structures, also called fins) with gate structures on both sides of the Fin. The FinFET structure makes the device smaller and has higher performance.
However, as the integration of semiconductor devices is further improved, the performance of finfet devices is expected to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a fin field effect transistor.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part; forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed.
Optionally, the material of the protective layer includes: SiO 22SiOCN, SiBCN or SiOBCN.
Optionally, the thickness of the protective layer is: 50 to 200 angstroms.
Optionally, the substrate has a well region therein, and the well region has trap ions therein, wherein the trap ions have a conductivity type opposite to that of the doped ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
Optionally, a gate structure crossing the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; the forming method of the protective layer comprises the following steps: forming protective films on the top surface of the isolation structure, the side wall and the top surface of the fin part and the side wall and the top surface of the grid structure; forming a first dielectric layer on the surface of the protective film, wherein the top surface of the first dielectric layer is lower than the top surface of the fin portion; and removing the protective film on the top of the fin part and the grid structure by taking the first dielectric layer as a mask to form the protective layer.
Optionally, the material of the first dielectric layer includes: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
Optionally, the thickness of the first dielectric layer is 200 angstroms to 500 angstroms.
Optionally, the forming method further includes: and forming source and drain doped regions in the fin parts on two sides of the grid structure respectively, wherein source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions.
Optionally, after the protective layer is formed and before the source-drain doped region is formed, doping ions are doped at the bottom of the fin portion; or doping ions into the fin part at the bottom of the source-drain doped region after the protective layer and the source-drain doped region are formed.
Optionally, the size from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
Optionally, the doping concentration of the source and drain ions is: 1.0E 21-5.0E 21 atomic number/cubic centimeter.
Optionally, after the source-drain doped region is formed and the dopant ions are doped at the bottom of the fin portion, the forming method further includes: forming a second dielectric layer on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; forming a contact hole exposing the top surface of the source drain doped region in the second dielectric layer; and forming a plug in the contact hole.
The present invention also provides a semiconductor structure comprising: the surface of the substrate is provided with a fin part and an isolation structure, and the top of the isolation structure is lower than the top of the fin part and covers part of the side wall of the fin part; a protective layer on a top surface of the isolation structure; dopant ions located within the bottom fin portion.
Optionally, the material of the protective layer includes:SiO2SiOCN, SiBCN or SiOBCN.
Optionally, the thickness of the protective layer is: 50 to 200 angstroms.
Optionally, the substrate has a well region therein, and the well region has trap ions therein, wherein the trap ions have a conductivity type opposite to that of the doped ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
Optionally, a gate structure crossing the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; source and drain doped regions are respectively arranged in the fin parts at two sides of the grid structure and the protective layer, source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions; the semiconductor structure further includes: the first dielectric layer is positioned on the surface of the protective layer, and the top surface of the first dielectric layer is lower than the top surface of the fin portion; the second dielectric layer is positioned on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; the contact hole is positioned in the second medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region; a plug located within the contact hole.
Optionally, the material of the first dielectric layer includes: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
Optionally, the thickness of the first dielectric layer is 200 angstroms to 500 angstroms.
Optionally, the size from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the substrate is internally provided with a well region, and the well region is used for realizing electrical isolation among different devices. Form the protective layer at isolation structure top for the basement top not only covers isolation structure, still covers the protective layer, then follow-up when doping ion in fin portion bottom, protective layer and isolation structure are great to the protection dynamics of basement, make in the well region be difficult for being doped with doping ion, then the isolation performance of well region is not influenced, promptly: the well region has better performance for isolating different devices, and the performance of the semiconductor device is better.
Further, the method for forming the protective layer includes: and forming protective films on the surfaces of the isolation structures, the side walls and the top surfaces of the fin parts. And forming a first dielectric layer on the surface of the protective film after the protective film is formed. And forming the protective layer by taking the first dielectric layer as a mask. And when doping ions are doped at the bottoms of the fin portions subsequently, the first dielectric layer can further protect the well region in the substrate, doping ions in the well region are prevented, and the performance of different devices of the semiconductor isolated by the well region is further ensured.
Furthermore, the grid electrode structures are arranged across the fin parts, after the first dielectric layers are formed, the depth-to-width ratio of the grooves between the adjacent grid electrode structures is favorably reduced, the difficulty of forming the second dielectric layers in the grooves between the adjacent grid electrode structures is low subsequently, the compactness of the formed second dielectric layers is good, the isolation performance of the second dielectric layers is good, and the performance of the semiconductor device is favorably improved.
Drawings
Fig. 1-3 are schematic structural diagrams of steps in a method of forming an N-type finfet transistor;
fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, finfet performance is poor.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming an N-type finfet.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view taken along line a-a1 in fig. 1, fig. 1 is a cross-sectional view taken along line B-B1 in fig. 2, providing a
Referring to fig. 3, doped ions are doped into the
In the above method, the method for forming the source/drain doped
In order to reduce the contact resistance between the source and drain doped
However, the energy of the doped ions at the bottom of the source/drain doped
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed. The device formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a cross-sectional view taken along line C-C1 in fig. 4, and fig. 4 is a cross-sectional view taken along line D-D1 in fig. 5, providing a
The method for forming the
In this embodiment, the initial substrate is made of silicon, and correspondingly, the
The material of the first mask layer comprises: silicon nitride or titanium nitride. The first mask layer is used as a mask for forming the
The process for etching the initial substrate by taking the first mask layer as a mask comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
Also within the
The method for forming the
The material of the isolation structure film comprises: silicon oxide, silicon oxynitride, or low K material (K less than 3.9), and accordingly, the material of the
The forming process of the isolation structure film comprises the following steps: a fluid chemical vapor deposition process.
The
A protective layer is subsequently formed on the surface of the
Referring to fig. 6, a
The cross-sectional direction of fig. 6 coincides with the cross-sectional direction of fig. 5.
The
The forming method of the
The gate dielectric film is made of the following materials: and silicon oxide, and correspondingly, the material of the gate dielectric layer comprises silicon oxide. The forming process of the gate dielectric film comprises the following steps: an in-situ steam generation process or a chemical oxidation process.
The material of the gate film comprises silicon, and correspondingly, the material of the gate layer comprises silicon. The forming process of the gate electrode film comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
The
Referring to fig. 7, a
The method for forming the
The first side wall film is made of materials including: silicon nitride or silicon oxynitride, respectively, the material of the first side comprising: silicon nitride or silicon oxynitride.
The forming process of the first side wall film comprises the following steps: an atomic layer deposition process or a chemical vapor deposition process.
The process for removing the first sidewall film on the top of the
The
The formation process of the lightly doped
In other embodiments, the transistor is a PMOS transistor, and thus, the lightly doped ions are P-type ions, such as: boron ion or BF2 +Ions.
Referring to fig. 8 and 9, after the doped
Fig. 8 and 7 are in the same cross-sectional direction, and fig. 9 and 4 are in the same cross-sectional direction.
In this embodiment, the material of the
In the present embodiment, the
In this embodiment, the forming process of the
In this embodiment, the
The thickness of the
Referring to fig. 10, a first
The forming method of the
The first dielectric film comprises the following materials: silicon oxide, silicon oxynitride or low K material (K less than 3.9), and correspondingly, the material of the
The forming process of the first dielectric film comprises a chemical vapor deposition process or a physical vapor deposition process.
The process for removing part of the first dielectric film comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The functions of the
The thickness of the
Referring to fig. 11, the
In the present embodiment, silicon nitride is used as the material of the
The
The forming process of the source-
The depth of the
Referring to fig. 12, an epitaxial layer (not shown) is formed in the source-drain opening 208 (see fig. 11); and doping source and drain ions into the
The forming process of the epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
The material of the epitaxial layer and the conductivity type of the source and drain ions are related to the type of the transistor.
In this embodiment, the transistor is an NMOS transistor, and therefore, the material of the epitaxial layer includes silicon and phosphorus, and the source and drain ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the transistor is a PMOS transistor, and thus, the epitaxial layer comprises silicon germanium, and the source and drain ions are P-type ionsAnd (c) as follows: boron ion or BF2 +Ions.
The doping concentration of the source and drain ions is as follows: 1.0E 21-5.0E 21 atomic number/cubic centimeter. The source and drain ions have a higher doping concentration, which is beneficial to reducing the contact resistance between the source and drain
The dimension from the top of the source-drain doped
Referring to fig. 13, doped ions are doped into the
In this embodiment, after the
In other embodiments, after the protective layer is formed and before the source/drain doped region is formed, doped ions are doped at the bottom of the fin portion.
The doped ions are used for reducing the resistance of the
Since the dimension from the top of the source drain doped
After doping ions into the
Before the second dielectric layer is formed, the
Accordingly, the present invention further provides a semiconductor structure, please refer to fig. 13, which includes: the semiconductor device comprises a
The material of the
The
The semiconductor device comprises a
The material of the
The thickness of the
The dimension from the top of the source drain doped
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:用于改进层间介电层形貌的方法