阅读说明：本技术 外延结构和低开启电压晶体管 (Epitaxial structure and low turn-on voltage transistor ) 是由 颜志泓 蔡文必 魏鸿基 于 2019-09-30 设计创作，主要内容包括：本申请提供了一种外延结构和低开启电压晶体管,涉及半导体领域。外延结构包含复合基电极层和复合发射极层。复合基电极层包含第一基电极层和制备在第一基电极层上的第二基电极层。第一基电极层的材料包含In<Sub>x</Sub>Ga<Sub>1－x</Sub>As<Sub>1－y</Sub>N<Sub>y</Sub>或In<Sub>x</Sub>Ga<Sub>1－x</Sub>As,第二基电极的材料包含In<Sub>m</Sub>Ga<Sub>1－</Sub><Sub>m</Sub>As。In<Sub>x</Sub>Ga<Sub>1－x</Sub>As<Sub>1－y</Sub>N<Sub>y</Sub>具有低能隙的特点,能够减少晶体管的开启电压,减少功耗。在靠近复合发射极层的方向上,第一基电极层中In含量不变,第二基电极层中In含量逐渐增大。In含量逐渐增大能够提高电子的载子迁移率,减少器件的基电极层的电阻,能够保证晶体管的频率特性良好。(The application provides an epitaxial structure and a low-turn-on voltage transistor, and relates to the field of semiconductors. The epitaxial structure comprises a composite base electrode layer and a composite emitter electrode layer. The composite base electrode layer includes a first base electrode layer and a second base electrode layer prepared on the first base electrode layer. The material of the first base electrode layer contains In x Ga 1－x As 1－y N y Or In x Ga 1－x As, the material of the second base electrode contains In m Ga 1－ m As。In x Ga 1－x As 1－y N y The transistor has the characteristic of low energy gap, can reduce the starting voltage of the transistor and reduce the power consumption. In the direction close to the composite emitter layer, the In content In the first base electrode layer is unchanged, and the In content In the second base electrode layer is gradually increased. The gradual increase of the In content can improve electronsThe carrier mobility of (2) reduces the resistance of the base electrode layer of the device, and can ensure good frequency characteristics of the transistor.)

1. An epitaxial structure, comprising:

a composite base electrode layer (10) comprising a first base electrode layer (101) and a second base electrode layer (102) prepared on the first base electrode layer (101), the material of the first base electrode layer (101) comprising In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs, a material of the second base electrode contains In_mGa_1-mAs；

A composite emitter layer (20) prepared on the basis of the second base electrode layer (102);

wherein the In content In the first base electrode layer (101) is constant and the In content In the second base electrode layer (102) is gradually increased In a direction approaching the composite emitter layer (20).

2. The epitaxial structure of claim 1, wherein the In_xGa_1-xAs_1-yN_yIn this case, x is 0.03 and x is 3 y.

3. Epitaxial structure according to claim 2, characterized In that the composition range of In the material of the first base electrode layer (101) is: 3 to 20 percent.

4. Epitaxial structure according to claim 3, characterized In that the first base electrode layer (101) In_xGa_1-xIn the As material, the In composition range is As follows: 7 to 102 percent.

5. The epitaxial structure of claim 1, wherein the In_mGa_1-mIn As, the value of m gradually increases from 0.05 to 0.15 in the direction close to the composite emitter layer (20).

6. The epitaxial structure of claim 1, wherein the In_mGa_1-mIn As, the value of x gradually increases from 0.03 to 0.2 in the direction close to the composite emitter layer (20).

7. Epitaxial structure according to claim 1, characterized in that the thickness of the second base electrode layer (102) ranges from: the thickness of the monoatomic layer is up to 30 nm.

8. Epitaxial structure according to claim 1, characterized in that the material of the composite emitter layer (20) comprises Ga_nIn_1-nP, the composite emitter layer (20) comprising:

a first emitter layer (201);

a second emitter layer (202) prepared on the basis of the first emitter layer (201);

a third emitter layer (203) prepared on the basis of the second emitter layer (202);

in the direction far away from the composite base electrode layer (10), the value of n in the first emitter layer (201) is gradually increased, the value of n in the second emitter layer (202) is unchanged, and the value of n in the third emitter layer (203) is gradually increased.

9. Epitaxial structure according to claim 8, characterized in that the value of n in the first emitter layer (201) is gradually increased from 0.3 to 0.7.

10. Epitaxial structure according to claim 8, characterized in that n in the second emitter layer (202) has a value of 0.3.

11. Epitaxial structure according to claim 8, characterized in that the value of n in the third emitter layer (203) is gradually increased from 0.3 to 0.51.

12. Epitaxial structure according to claim 8, characterized in that the composition range of Ga in the material of the composite emitter layer (20) is: 30 to 70 percent.

13. Epitaxial structure according to claim 8, characterized in that the thickness of the first emitter layer (201) ranges from: 1nm to 5nm, the thickness range of the second emitter layer (202) is as follows: 15nm to 25nm, the thickness range of the third emitter layer (203) is as follows: 5nm to 10 nm.

14. A low turn-on voltage transistor comprising the epitaxial structure of any one of claims 1 to 13.

Technical Field

The application relates to the field of semiconductors, in particular to an epitaxial structure and a low-turn-on voltage transistor.

Background

The existing heterojunction indium gallium phosphide transistor device (InGaP HBT) has high device reliability and good application prospect, but the starting voltage is high, so that the power consumption of the device is high. Therefore, it is desirable to design a transistor that can be applied to a low turn-on voltage, reduce power consumption, and does not cause other drawbacks.

Disclosure of Invention

The application provides an epitaxial structure and low-starting-voltage transistor, can be applicable to low-starting-voltage, reduce the consumption, and can not bring other defects.

An embodiment of the present application provides an epitaxial structure, including:

a composite base electrode layer comprising a first base electrode layer and a second base electrode layer prepared on the first base electrode layer, the material of the first base electrode layer containing In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs, the material of the second base electrode contains In_mGa_1-mAs；

A composite emitter layer prepared based on the second base electrode layer;

in the direction close to the composite emitter layer, the In content In the first base electrode layer is unchanged, and the In content In the second base electrode layer is gradually increased.

Further, In_xGa_1-xAs_1-yN_yIn this case, x is 0.03 and x is 3 y.

Further, In the material of the first base electrode layer, the composition range of In is: 3 to 20 percent.

Further, In the material of the first base electrode layer, the composition range of In is: 7 to 102 percent.

Further, In_xGa_1-xIn As, the value of x gradually increases from 0.05 to 0.15 in the direction close to the composite emitter layer.

Further, In_xGa_1-xIn As, the value of x gradually increases from 0.03 to 0.2 in the direction close to the composite emitter layer.

Further, the thickness range of the second base electrode layer is: the thickness of the monoatomic layer is up to 30 nm.

Further, the material of the composite emitter layerComprising Ga_xIn_1-xP, the composite emitter layer comprising:

a first emitter layer;

a second emitter layer prepared on the basis of the first emitter layer;

a third emitter layer prepared on the basis of the second emitter layer;

in the direction far away from the composite base electrode layer, the value of x in the first emitter layer is gradually increased, the value of x in the second emitter layer is unchanged, and the value of x in the third emitter layer is gradually increased.

Further, the value of x in the first emitter layer gradually increases from 0.3 to 0.7.

Further, the value of x in the second emitter is 0.3.

Further, the value of x in the third emitter layer gradually increases from 0.3 to 0.51.

Further, in the material of the composite emitter layer, the composition range of Ga is: 30 to 70 percent.

Further, the thickness range of the first emitter layer is: 1 nm-5 nm, and the thickness range of the second emitter layer is as follows: 15 nm-25 nm, and the thickness range of the third emitter layer is as follows: 5nm to 10 nm.

The embodiment of the application also provides a low-turn-on voltage transistor which comprises the epitaxial structure.

The epitaxial structure and the low-turn-on voltage transistor provided by the embodiment of the application have the beneficial effects that:

1. designing a composite base electrode layer to comprise a first base electrode layer and a second base electrode layer, wherein the material of the first base electrode layer comprises In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs, the material of the second base electrode layer contains In_mGa_1-mAs，In_xGa_1-xAs_1-yN_yThe material has the characteristic of low energy gap, can reduce the starting voltage of a transistor, and reduce the power consumption;

2. in as described above_xGa_1-xAs_1-yN_yThe material has the problem of low electron carrier mobility, and the direct application of the materialResulting in an excessively high resistance value and limiting the frequency characteristics of the transistor. In this regard, the following is designed: in the direction close to the composite emitter layer, the In content In the first base electrode layer is unchanged, the In content In the second base electrode layer is gradually increased, the carrier mobility of electrons can be improved due to the gradual increase of the In content, the resistance of the base electrode layer of the device is reduced, and the good frequency characteristic of the transistor is ensured. Meanwhile, the conduction band spike effect between the second base electrode layer and the composite emitter electrode layer is reduced along with the gradual increase of the In content, and the starting voltage of the transistor is further reduced;

3. in the preparation process, no additional working procedure is needed, and no additional preparation cost is increased.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic view of an epitaxial structure according to a first embodiment of the present application.

FIG. 2 is a flow chart for the preparation of the epitaxial structure of FIG. 1.

Fig. 3 is a schematic diagram of an epitaxial structure applied to an HBT according to a second embodiment of the present application.

Fig. 4 is a schematic view of an epitaxial structure according to a third embodiment of the present application.

Fig. 5 is a flow chart of the preparation of the epitaxial structure of fig. 4.

Fig. 6 is a schematic diagram of an epitaxial structure applied to an HBT according to a fourth embodiment of the present application.

Icon: 1-an epitaxial structure; 10-a composite base electrode layer; 101-a first base electrode layer; 102-a second base electrode layer; 20-a composite emitter layer; 201-first emitter layer; 202-a second emitter layer; 203-a third emitter layer; 30-a substrate; a 40-sub-collector layer; 50-a collector layer; 60-a cap layer; 70-collector metal contact layer; 80-emitter metal contact layer; a 90-base electrode metal contact layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it is to be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like are used in an orientation or positional relationship as indicated in the drawings, or as would be ordinarily understood by those skilled in the art, simply for convenience in describing and simplifying the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be in any way limiting of the present application.

Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

For a heterojunction indium gallium phosphide transistor device (InGaP HBT), the conduction band spike effect between an Emitter electrode layer (Emitter) and a Base electrode layer (Base) is reduced, and the turn-on voltage (Vbe, on) value of the heterojunction indium gallium phosphide transistor device can be reduced. The energy gap of the material of the Base electrode layer is reduced, and the purpose of improving the conduction band spike effect between the Emitter layer (Emitter) and the Base electrode layer (Base) can be achieved.

In a gallium arsenide-based heterojunction transistor device,using In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs is used for preparing the Base electrode layer, the energy gap of the material of the Base electrode layer can be reduced, and therefore the purpose of reducing the conduction band spike effect between the Emitter layer (Emitter) and the Base electrode layer (Base) is achieved. However, In_xGa_1-xAs_1-yN_yThe problem of low electron carrier mobility is solved, and direct application causes the resistance of the base electrode layer to be too high, thereby limiting the frequency characteristics of the transistor.

Therefore, the embodiment of the application provides an epitaxial structure and a low-turn-on voltage transistor, which can be suitable for low-turn-on voltage, reduce power consumption, improve the carrier mobility of electrons, reduce the resistance of a base electrode layer of a device, and can ensure good frequency characteristics of the transistor when applied to the transistor.

First embodiment

Referring to fig. 1, the present embodiment provides an epitaxial structure 1, which includes a composite base electrode layer 10 and a composite emitter layer 20.

The composite base electrode layer 10 is a two-layer material structure, the composite base electrode layer 10 includes a first base electrode layer 101 and a second base electrode layer 102, and the second base electrode layer 102 is formed on the first base electrode layer 101. The material of the first base electrode layer 101 contains In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs, the material of the second base electrode contains In_mGa_1-mAs。In_xGa_1-xAs_1-yN_yThe material has the characteristic of low energy gap, improves the conduction band spike effect between the base electrode layer and the emitter electrode layer, and can reduce the starting voltage of the transistor and reduce the power consumption.

In a direction close to the composite emitter layer 20, equivalently, In a direction from bottom to top In fig. 1, the In content In the first base electrode layer 101 is constant, and the In content In the second base electrode layer 102 gradually increases.

In the second base electrode layer 102, the In content gradually increases with the increase of the height, and the increasing speed may keep a linear relationship with the height, and the size relationship may also be flexibly designed according to the performance requirement, so long as the In content tends to increase with the increase of the height, which shall fall within the scope of the claimed application.

The gradual increase of the In content can improve the carrier mobility of electrons, reduce the resistance of the base electrode layer and ensure good frequency characteristics of the transistor. Meanwhile, the conduction band spike effect between the second base electrode layer 102 and the composite emitter layer 20 is reduced as the In content gradually increases, thereby further reducing the turn-on voltage of the transistor.

The composite emitter layer 20 is a single-layer material structure. The material of the composite emitter layer 20 comprises Ga_nIn_1-nAnd P. The In content In the composite emitter layer 20 is uniformly distributed and remains equal.

Referring to fig. 2, the present embodiment further provides a method for manufacturing the epitaxial structure 1, including the following steps:

s1: preparing the first base electrode layer 101

In may be used as the material of the first base electrode layer 101_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs。

In is formed by_xGa_1-xAs_1-yN_yFor example, x is 0.03 and x is 3y, and the In composition In the material of the first base electrode layer 101 may be any fixed value from 3% to 20%. The layer is grown with a suitable mole fraction (mole ratio) depending on the material growth requirements.

In is formed by_xGa_1-xAs is, x may be set to 0.03, and the In composition In the material of the first base electrode layer 101 may be any fixed value from 7% to 102%. Thus, the first base electrode layer 101 is gradually formed by adjusting the mole fraction (mole ratio) of In, the mole fraction (mole ratio) of Ga, and the mole fraction (mole ratio) of N In proportion, and the In content distribution is kept uniform and equal from bottom to top.

S2: preparing the second base electrode layer 102

In may be used as the material of the second base electrode layer 102_mGa_1-mAs. In the direction close to the composite emitter layer 20, that is, the direction from bottom to top, the value of m gradually increases from 0.05 to 0.15. At itIn other embodiments, the value of m may be gradually increased from 0.03 to 0.2.

The mole fraction (mole ratio) of In and the mole fraction (mole ratio) of Ga are adjusted In proportion, and the second base electrode layer 102 is gradually deposited and formed on the first base electrode layer 101, with the In content being kept gradually increasing from bottom to top. The In content is gradually increased and increased by In_mGa_1-mWhen the As forms the base electrode layer, the carrier mobility of electrons is reduced, and the conduction band spike effect between the second base electrode layer 102 and the composite emitter layer 20 is reduced, so that the turn-on voltage of the device is reduced, and the energy consumption is reduced.

S2 may control the thickness of the second base electrode layer 102 to be in the range of: the thickness of the monoatomic layer is up to 30 nm.

S3: preparing the composite emitter layer 20

The composite emitter layer 20 is designed to be a single-layer material structure, and Ga can be used as the material of the composite emitter layer 20_nIn_{1- n}P, the composition range of Ga in the material of the composite emitter layer 20 is 30% to 70%.

The composite emitter layer 20 is gradually formed on the second base electrode layer 102 by adjusting the mole fraction (mole ratio) of In and the mole fraction (mole ratio) of Ga In proportion.

The epitaxial structure 1 and the preparation method thereof provided by the embodiment have the following beneficial effects:

1. the starting voltage of the transistor can be reduced and the power consumption can be reduced by using the low energy gap material;

2. the carrier mobility of electrons can be improved, the resistance value of the base electrode layer is kept at a lower level, and the good frequency characteristic of the transistor can be ensured;

3. the preparation method only needs to correspondingly adjust the mole ratio of the raw materials, does not need to add extra working procedures, and does not cause extra cost.

Second embodiment

The present embodiment provides an epitaxial structure 1, which is further designed to be applied to an epitaxial structure 1 of an HBT (heterojunction bipolar transistor) on the basis of the epitaxial structure 1 provided in the first embodiment.

Referring to fig. 3, the epitaxial structure 1 includes a substrate 30, a sub-collector layer 40, a collector layer 50, a composite base electrode layer 10, a composite emitter layer 20, and a cap layer 60, which are sequentially grown from bottom to top. Among them, the composite base electrode layer 10 and the composite emitter layer 20 use the structure in the first embodiment.

In addition, an emitter metal contact layer 80 is disposed above the composite emitter layer 20, the emitter metal contact layer 80 forms ohmic contact with the cap layer 60, a base electrode metal contact layer 90 is disposed on the composite base electrode layer 10, and the base electrode metal contact layer 90 forms ohmic contact with the composite base electrode layer 10. A collector metal contact layer 70 is provided on the sub-collector layer 40, and the collector metal contact layer 70 forms ohmic contact with the sub-collector layer 40.

Among them, GaAs may be used as the material of substrate 30, sub-collector layer 40, collector layer 50, and cap layer 60.

Third embodiment

The present embodiment provides an epitaxial structure 1 which is different from the epitaxial structure 1 in the first embodiment in that the structure of the composite emitter layer 20 is different.

Referring to fig. 4, the epitaxial structure 1 includes a composite base electrode layer 10 and a composite emitter layer 20. Here, the composite base electrode layer 10 uses the structure in the first embodiment.

The composite emitter layer 20 is a three-layer material structure. The material of the composite emitter layer 20 comprises Ga_nIn_1-nP, the composite emitter layer 20 includes a first emitter layer 201, a second emitter layer 202, and a third emitter layer 203, which are sequentially grown from bottom to top. In a direction away from the composite base electrode layer 10, that is, in a direction from bottom to top, a value of n in the first emitter layer 201 gradually increases, a value of n in the second emitter layer 202 does not change, and a value of n in the third emitter layer 203 gradually increases.

In the first emitter layer 201 and the third emitter layer 203, the value of n is gradually increased, so that the conduction band peak between the composite base electrode layer 10 and the composite emitter layer 20 can be further improved, the turn-on voltage of the device is reduced, and the power consumption is reduced.

In the first emitter layer 201 and the third emitter layer 203, the Ga content gradually increases with the increase of the height, and the increasing speed can keep a linear relation with the height, and the size relation can also be flexibly designed according to the performance requirement, so long as the Ga content tends to increase with the increase of the height, which shall fall within the protection scope of the present application.

Referring to fig. 5, the present embodiment further provides a method for manufacturing the epitaxial structure 1, including the following steps:

s10: preparing the first base electrode layer 101

S10 is the same as S1 in the first embodiment, and is not described here again.

S20: preparing the second base electrode layer 102

S20 is the same as S2 in the first embodiment, and is not described here again.

S30: preparing the first emitter layer 201

The material of the first emitter layer 201 is Ga_nIn_1-nP, wherein the value of n gradually increases from 0.3 to 0.7 in the direction away from the composite base electrode layer 10, i.e., in the direction from bottom to top.

The mole fraction of In and the mole fraction of Ga are adjusted In proportion, the first emitter layer 201 is gradually deposited and formed on the second base electrode layer 102, and the Ga content is kept gradually increasing from bottom to top.

The thickness range of the first emitter layer 201 is: 1nm to 5 nm.

S40: preparing the second emitter layer 202

The material of the second emitter layer 202 is Ga_nIn_1-nP, wherein the value of n is kept constant in the direction away from the composite base electrode layer 10, that is, in the direction from bottom to top, which is equivalent to that the Ga in the second emitter layer 202 is uniformly distributed and the content of Ga is kept constant. In this embodiment, the value of n in the second emitter is 0.3.

The mole fraction of In and the mole fraction of Ga are proportionally adjusted, and the second emitter layer 202 is gradually stacked on the first emitter layer 201, and the Ga content is kept unchanged from bottom to top.

The thickness range of the second emitter layer 202 is: 15nm to 25 nm.

S50: preparing the third emitter layer 203

The material of the third emitter layer 203 is Ga_nIn_1-nP, wherein the value of n gradually increases from 0.3 to 0.51 in a direction away from the composite base electrode layer 10, i.e., in a direction from bottom to top.

The mole fraction of In and the mole fraction of Ga are proportionally adjusted, and the third emitter layer 203 is gradually stacked on the second emitter layer 202, and the Ga content is kept gradually increasing from bottom to top.

The thickness range of the third emitter layer 203 is: 5nm to 10 nm.

Fourth embodiment

The present embodiment provides an epitaxial structure 1, which is further designed to be applied to an epitaxial structure 1 of an HBT (heterojunction bipolar transistor) on the basis of the epitaxial structure 1 provided in the third embodiment.

Referring to fig. 6, the epitaxial structure 1 includes a substrate 30, a sub-collector layer 40, a collector layer 50, a composite base electrode layer 10, a composite emitter layer 20, and a cap layer 60, which are sequentially grown from bottom to top. Among them, the composite base electrode layer 10 and the composite emitter layer 20 use the structure in the third embodiment. In addition, an emitter metal contact layer 80 is disposed above the cap layer 60 and is in ohmic contact with the composite emitter layer 20. The composite base electrode layer 10 is provided with a base electrode metal contact layer 90, and the base electrode metal contact layer 90 is in ohmic contact with the composite base electrode layer 10. A collector metal contact layer 70 is disposed on the sub-collector layer 40, and the collector metal contact layer 70 is in ohmic contact with the sub-collector layer 40.

The epitaxial structure 1 provided in this embodiment is similar to the epitaxial structure 1 provided in the second embodiment, except that the structure of the composite emitter layer 20 is different, and the structures of other layers are correspondingly the same, and are not described herein again.

It should be emphasized that the epitaxial structure 1 described in the present application has a wide application range, such as various transistors, and further, can be applied to a power amplifier or other electrical appliances, and the composite base electrode layer 10 provided in the present application should be applied to the scope of protection claimed in the present application.

In the present application, the composite base electrode layer 10 is a double-layer material structure, and the composite emitter layer 20 is a single-layer material structure or a three-layer material structure, according to the principle of the present application, the composite base electrode layer 10 can also be designed into a layer structure with more number, and the composite emitter layer 20 can also be designed into a double-layer material structure or a layer structure with more number, so, in other embodiments, the number of the layer structures may not be limited.

The epitaxial structure 1 and the low-turn-on voltage transistor provided by the embodiment of the application have the beneficial effects that:

1. the composite base electrode layer 10 is designed such that the composite base electrode layer 10 includes a first base electrode layer 101 and a second base electrode layer 102, and the material of the first base electrode layer 101 includes In_xGa_1-xAs_1-yN_yOr In_xGa_1-xAs, the material of the second base electrode layer 102 contains In_mGa_1-mAs，In_xGa_1-xAs_1-yN_yThe material has the characteristic of low energy gap, can reduce the starting voltage of a transistor, and reduce the power consumption;

2. in as described above_xGa_1-xAs_1-yN_yThe material has the problem of low electron carrier mobility, and direct application of the material can cause over-high resistance and limit the frequency characteristics of the transistor. In this regard, the following is designed: in the direction close to the composite emitter layer 20, the In content In the first base electrode layer 101 is unchanged, the In content In the second base electrode layer 102 is gradually increased, and the gradual increase of the In content can improve the carrier mobility of electrons, reduce the resistance of the base electrode layer of the device, and ensure that the frequency characteristics of the transistor are good. Meanwhile, the conduction band spike effect between the second base electrode layer 102 and the composite emitter layer 20 is reduced along with the gradual increase of the In content, so that the turn-on voltage of the transistor is further reduced;

3. in the preparation process, no additional working procedure is needed, and no additional preparation cost is increased.

The above technical solutions are only exemplary descriptions made by the applicant around the technical core, and cannot be described as the only technical solutions in the present application, and a person skilled in the art can make some conceivable modifications on the core of the present application to obtain other technical solutions, and these other technical solutions should fall within the protection scope of the present application.