阅读说明：本技术 芯片设计中基于综合网表提取时钟树的方法及应用 (Method for extracting clock tree based on comprehensive netlist in chip design and application ) 是由 吴帅帅 郑立青 杨睿 孙一 于 2021-07-29 设计创作，主要内容包括：本发明公开了芯片设计中基于综合网表提取时钟树的方法及应用,涉及集成电路设计技术领域。所述方法包括步骤：在逻辑综合步骤,获取芯片顶层和子模块的逻辑综合网表信息,以及芯片切分的模块信息和时钟约束文件信息；根据获取的信息拼接全芯片的时钟结构,从时钟约束文件中获取时钟源；基于全芯片的时钟结构信息,从时钟源开始采用递归算法逐级往后循迹以形成全芯片时钟树网络；在循迹过程中,根据时钟树循迹路径确定顶层时钟树和子模块时钟树的起点和终点；循迹结束,对顶层和子模块的时钟结构进行归类以形成时钟树实现指导文件。本发明缩短了时钟树验证周期,提高了时钟树实现工作的效率和正确性。(The invention discloses a method for extracting a clock tree based on a comprehensive netlist in chip design and application thereof, and relates to the technical field of integrated circuit design. The method comprises the following steps: in the logic synthesis step, logic synthesis netlist information of a top layer and sub-modules of a chip, module information of chip segmentation and clock constraint file information are obtained; splicing the clock structure of the whole chip according to the acquired information, and acquiring a clock source from a clock constraint file; based on the clock structure information of the whole chip, tracking from a clock source to a clock tree network of the whole chip by adopting a recursive algorithm step by step; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree; and after tracking is finished, classifying the clock structures of the top layer and the sub-modules to form a clock tree implementation guide file. The invention shortens the clock tree verification period and improves the efficiency and the correctness of clock tree realization work.)

1. A method for extracting clock tree based on synthesized netlist in chip design is characterized by comprising the following steps:

in the logic synthesis step, logic synthesis netlist information of a chip top layer and sub-modules, module information of chip segmentation and clock constraint file information are obtained;

splicing the clock structure of the whole chip according to the acquired information, and acquiring a point defined by a clock from a clock constraint file as an initial clock source;

based on the clock structure information of the whole chip, tracking from an initial clock source to the back step by adopting a recursive algorithm to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree;

and after tracking is finished, classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file.

2. The method of claim 1, wherein: the steps of tracking backwards step by step using a recursive algorithm starting from an initial clock source are as follows,

s310, using the initial clock source as a top-level clock source;

s320, acquiring a top-level clock source, and judging whether a clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule; if yes, go to step S331; otherwise, go to step S332;

s331, executing step S3311 when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the clock source, and executing step S3312 when determining that the clock is connected to the clock terminal of the flip-flop inside one of the submodules from the clock source;

s3311, configuring the segment of clock as a top-level clock tree, configuring the clock source as a start point of the segment of clock tree, configuring the analog IP port or the chip output port as an end point of the segment of clock tree, and performing step S340;

s3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; configuring the flip-flop from the input end of the sub-module to the inside as a sub-module clock tree, configuring the input end of the sub-module as the starting point of the segment clock tree, configuring the flip-flop inside the sub-module as the end point of the segment clock tree, and executing step S340;

s332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule, if so, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source as the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree; configuring the output end of the submodule as a top-level next-level clock source, and returning to the step S320 for next-level backward tracking;

s340, ending the tracking.

3. The method of claim 1, wherein: the clock tree realization guide file comprises a top-level clock tree realization guide file and sub-module clock tree realization guide files, the top-level clock tree realization guide file comprises the starting point and the end point information of the top-level clock tree, and the sub-module clock tree realization guide file comprises the starting point and the end point information of each sub-module clock tree.

4. The method of claim 3, wherein: and obtaining communication account information of clock tree implementing personnel, and sending the top-level clock tree implementing guide file and the sub-module clock tree implementing guide file to the clock tree implementing personnel according to the communication account information.

5. The method of claim 1, wherein: and after analyzing the logic synthesis netlist and the clock constraint file information of the top layer of the chip and each submodule of the chip by a time sequence analysis tool, splicing the clock structure of the whole chip.

6. The method of claim 1, wherein: the module information is a sub-module list.

7. A chip design method at least comprises a clock design step, a logic synthesis step, a layout step, a clock tree realization step and a wiring step, and is characterized in that:

in the logic synthesis step, a clock tree implementation guide file is acquired by the method of any one of claims 1 to 5 as guide information of the clock tree implementation step at the later stage.

8. A chip design system at least comprises a clock design unit, a logic synthesis unit, a layout unit, a clock tree realization unit and a wiring unit, and is characterized in that:

the logic synthesis unit includes a clock analysis module configured to: acquiring a clock tree implementation guide file by the method of any one of claims 1-5 and sending the clock tree implementation guide file to the clock tree implementation unit.

9. A device for extracting clock tree based on synthesized netlist in chip design is characterized by comprising the following structures:

the information acquisition module is used for acquiring logic synthesis netlist information of a top layer and sub-modules of the chip, module information of chip segmentation and clock constraint file information in the logic synthesis step;

the initialization module is used for splicing the clock structure of the whole chip according to the acquired information and acquiring a point defined by a clock from a clock constraint file as an initial clock source;

the clock tree tracking module is used for tracking the clock structure information of the whole chip from the initial clock source by adopting a recursive algorithm step by step to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree;

and the result processing module is used for classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file after the tracking is finished.

10. The method of claim 9, wherein: the clock tree tracking module is configured to perform the steps of:

s310, using the initial clock source as a top-level clock source;

s320, acquiring a top-level clock source, and judging whether a clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule; if yes, go to step S331; otherwise, go to step S332;

s331, executing step S3311 when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the clock source, and executing step S3312 when determining that the clock is connected to the clock terminal of the flip-flop inside one of the submodules from the clock source;

s3311, configuring the segment of clock as a top-level clock tree, configuring the clock source as a start point of the segment of clock tree, configuring the analog IP port or the chip output port as an end point of the segment of clock tree, and performing step S340;

s3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; configuring the flip-flop from the input end of the sub-module to the inside as a sub-module clock tree, configuring the input end of the sub-module as the starting point of the segment clock tree, configuring the flip-flop inside the sub-module as the end point of the segment clock tree, and executing step S340;

s332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule, if so, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source as the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree; configuring the output end of the submodule as a top-level next-level clock source, and returning to the step S320 for next-level backward tracking;

s340, ending the tracking.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a method for extracting a clock tree in chip design.

Background

With the gradual maturity of 5G and artificial intelligence technologies, the demand for chip functions in the development process is increasing, the chip scale is also increasing, but the expected chip design cycle is shorter and shorter, and how to optimize the chip design flow to improve the design efficiency in the chip design process and reduce the waste of design resources is one of the current main research directions. The main flow of a typical chip design generally includes the following steps: specification formulation, architecture design, clock design, code compiling, simulation verification, logic synthesis, form verification, testability design, layout planning (or called layout), clock tree realization (or called clock tree synthesis), wiring planning (or called wiring), form verification, parasitic parameter extraction, timing verification and physical layout verification. In the logic synthesis step, a logic synthesis tool (such as design component of synopsys) is used to convert the register transfer level hardware description language code into a logic gate level netlist for a specific process according to information such as a set process library, design constraints and the like. The design constraints include timing constraints of the integrated circuit. The logic gate-level netlist records the connection relationship between the logic modules. In the layout planning step, each logic module is physically laid out according to constraints such as time sequence, utilization rate, congestion degree, power consumption and the like. In the clock tree implementation step, a path from the original clock source to the target sequential logic module is designed to satisfy the timing constraint in the design constraint.

In the working process of the chip, the clock is the synchronous beat of the chip synchronous working system. It is the same as the nervous system of human body, and is used to command and ensure the normal operation of various functional modules in the chip, so the correctness and stability of the clock tree of the chip are especially important in the design process of the chip.

The hierarchical design is the most common design method of a large-scale chip, the chip to be designed is divided into a plurality of sub-modules, each sub-module is designed independently and then called by a top module, and as the clock tree balance is carried out on each sub-module independently, the whole chip only needs to pay attention to the clock delay of a register at the interface of the sub-modules, so that the design period is obviously improved, and the timing sequence problem is localized. Based on the design method, the physical realization of the current large-scale chip adopts a bottom-up mode, the whole chip is divided into a plurality of sub-modules to be respectively realized and then integrated together by a top layer. The design of the clock tree also adopts a bottom-up mode, firstly, the top layer and the sub-modules respectively realize the clock tree design, and then the top layer is spliced to verify the connectivity of the clock. If the connectivity is not satisfied, the module re-clocks the tree; if the logic has a problem or the submodule has a problem of clock leakage definition, the logic is fed back to a chip clock designer for re-planning.

However, on one hand, because the clock tree design is in the early stage of the chip design, and the clock tree analysis and implementation are in the later stage of the chip design, a large amount of other design analysis work exists between the clock tree design and the clock tree design, if the clock tree analysis and implementation stage finds that the clock tree has problems, the scheme in the early stage of the design often needs to be modified, so that a large amount of work between the two stages is possibly invalid, the iteration time is increased, and the chip design period is prolonged. On the other hand, the clock realization work of the current large-scale chip is usually realized independently by sub-modules from bottom to top, and then a top-level splicing is adopted to verify connectivity and correctness, the mode has high dependency on the constraint file of the sub-modules, if the clock tree in the constraint file of the sub-modules has problems, the sub-modules cannot discover themselves, and the problems can only be discovered when the top-level splicing is performed at the later stage, and the iteration risk is increased because the time for solving the problems is delayed.

Disclosure of Invention

The invention aims to: the method overcomes the defects of the prior art and provides a method for extracting the clock tree based on the comprehensive netlist in chip design and application thereof. The invention analyzes the clock tree in the logic synthesis step of the chip design flow, simultaneously segments the clock structure into each module under the condition of determining the coherence of the full-chip clock network, and forms the clock tree realization guide file of the later clock tree realization step, thereby reducing the work of the iterative process of clock tree verification from the logic synthesis stage to the clock tree realization stage, and improving the efficiency and the correctness of the clock tree realization work.

In order to achieve the above object, the present invention provides the following technical solutions:

a method for extracting clock tree based on synthesized netlist in chip design includes following steps:

in the logic synthesis step, logic synthesis netlist information of a chip top layer and sub-modules, module information of chip segmentation and clock constraint file information are obtained;

splicing the clock structure of the whole chip according to the acquired information, and acquiring a point defined by a clock from a clock constraint file as an initial clock source;

based on the clock structure information of the whole chip, tracking from an initial clock source to the back step by adopting a recursive algorithm to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree;

and after tracking is finished, classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file.

Further, the step of tracking backward step by using a recursive algorithm from the initial clock source is as follows,

s310, using the initial clock source as a top-level clock source;

s320, acquiring a top-level clock source, and judging whether a clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule; if yes, go to step S331; otherwise, go to step S332;

s331, executing step S3311 when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the clock source, and executing step S3312 when determining that the clock is connected to the clock terminal of the flip-flop inside one of the submodules from the clock source;

s3311, configuring the segment of clock as a top-level clock tree, configuring the clock source as a start point of the segment of clock tree, configuring the analog IP port or the chip output port as an end point of the segment of clock tree, and performing step S340;

s3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; configuring the flip-flop from the input end of the sub-module to the inside as a sub-module clock tree, configuring the input end of the sub-module as the starting point of the segment clock tree, configuring the flip-flop inside the sub-module as the end point of the segment clock tree, and executing step S340;

s332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule, if so, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source as the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree; configuring the output end of the submodule as a top-level next-level clock source, and returning to the step S320 for next-level backward tracking;

s340, ending the tracking.

Further, the clock tree implementation guidance file comprises a top-level clock tree implementation guidance file and sub-module clock tree implementation guidance files, the top-level clock tree implementation guidance file comprises start point and end point information of the top-level clock tree, and the sub-module clock tree implementation guidance file comprises start point and end point information of each sub-module clock tree.

And further, communication account information of clock tree implementing personnel is obtained, and the top-level clock tree implementing guide file and the sub-module clock tree implementing guide file are sent to the clock tree implementing personnel according to the communication account information.

And further, after analyzing the logic synthesis netlist and the clock constraint file information of the top layer of the chip and each submodule of the chip by a time sequence analysis tool, splicing the clock structure of the whole chip.

Further, the module information is a sub-module list.

The invention also provides a chip design method, which at least comprises a clock design step, a logic synthesis step, a layout step, a clock tree realization step and a wiring step;

in the logic synthesis step, a clock tree implementation guide file is obtained by the method of any one of the preceding claims and is used as guide information of the later clock tree implementation step.

The invention also provides a chip design system, which at least comprises a clock design unit, a logic synthesis unit, a layout unit, a clock tree realization unit and a wiring unit;

the logic synthesis unit includes a clock analysis module configured to: the clock tree realization guide file is obtained through the method of any one of the preceding claims, and is sent to the clock tree realization unit.

The invention also provides a device for extracting the clock tree based on the comprehensive netlist in the chip design, which comprises the following structures:

the information acquisition module is used for acquiring logic synthesis netlist information of a top layer and sub-modules of the chip, module information of chip segmentation and clock constraint file information in the logic synthesis step;

the initialization module is used for splicing the clock structure of the whole chip according to the acquired information and acquiring a point defined by a clock from a clock constraint file as an initial clock source;

the clock tree tracking module is used for tracking the clock structure information of the whole chip from the initial clock source by adopting a recursive algorithm step by step to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree;

and the result processing module is used for classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file after the tracking is finished.

Further, the clock tree tracking module is configured to perform the steps of:

s310, using the initial clock source as a top-level clock source;

s320, acquiring a top-level clock source, and judging whether a clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule; if yes, go to step S331; otherwise, go to step S332;

s331, executing step S3311 when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the clock source, and executing step S3312 when determining that the clock is connected to the clock terminal of the flip-flop inside one of the submodules from the clock source;

s3311, configuring the segment of clock as a top-level clock tree, configuring the clock source as a start point of the segment of clock tree, configuring the analog IP port or the chip output port as an end point of the segment of clock tree, and performing step S340;

s3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; configuring the flip-flop from the input end of the sub-module to the inside as a sub-module clock tree, configuring the input end of the sub-module as the starting point of the segment clock tree, configuring the flip-flop inside the sub-module as the end point of the segment clock tree, and executing step S340;

s332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule, if so, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source as the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree; configuring the output end of the submodule as a top-level next-level clock source, and returning to the step S320 for next-level backward tracking;

s340, ending the tracking.

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects as examples:

on one hand, the correctness of the clock tree can be verified in the logic synthesis step, and compared with the method of verifying the correctness of the clock tree in the clock tree implementation step in the later stage of the chip design flow, the method can remarkably reduce the workload from the logic synthesis stage to the clock tree implementation stage in the iteration process of clock tree verification, thereby shortening the clock tree verification period, further reducing the waste of design resources and shortening the chip design period.

On the other hand, a clock tree network can be extracted based on the comprehensive netlist by using a time sequence analysis tool, the analysis process of the clock tree adopts a top-down mode, the continuity of the full-chip clock structure is firstly determined, then the clock structure is segmented to each sub-module according to module division information and used as a guide file of the clock tree implementation stage at the later stage of chip design, and the working efficiency and the accuracy of the clock tree implementation stage are improved. Meanwhile, the clock tree design can be carried out on the premise of ensuring connectivity by the top layer and the sub-module of the chip, so that the constraint files of the module are not completely relied on, the design of the sub-module and the top layer does not need iteration, and the iteration time of the physical verification of the chip is shortened.

Drawings

Fig. 1 is a basic flowchart of a method for extracting a clock tree based on a synthesized netlist in a chip design according to an embodiment of the present invention.

Fig. 2 is a detailed flowchart of a method for extracting a clock tree based on a synthesized netlist in a chip design according to an embodiment of the present invention.

Fig. 3 is a diagram illustrating a structure of a full-chip clock tree network according to an embodiment of the present invention.

Detailed Description

The method and application for extracting clock tree based on synthesized netlist in chip design disclosed in the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that technical features or combinations of technical features described in the following embodiments should not be considered as being isolated, and they may be combined with each other to achieve better technical effects. In the drawings of the embodiments described below, the same reference numerals appearing in the respective drawings denote the same features or components, and may be applied to different embodiments. Thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

It should be noted that the structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are only for the purpose of understanding and reading the present disclosure, and are not intended to limit the scope of the invention, which is defined by the claims, and any modifications of the structures, changes in the proportions and adjustments of the sizes and other dimensions, should be construed as falling within the scope of the invention unless the function and objectives of the invention are affected. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be executed out of order from that described or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

Examples

Referring to fig. 1, a method for extracting a clock tree based on a synthesized netlist in a chip design is provided.

The method comprises the following steps:

and S100, acquiring a comprehensive netlist, a clock constraint file and a module list.

In the logic synthesis step of the chip design flow, a logic synthesis netlist is generated, and the logic synthesis netlist records the connection relation between each logic module in the chip. In this embodiment, in the logic synthesis step, logic synthesis netlist information of the top layer and the sub-modules of the chip, and module information and clock constraint file information of chip segmentation are obtained.

The module information of the chip segmentation preferably adopts a sub-module list.

And S200, splicing the full-chip clock structure according to the comprehensive netlist and the clock constraint file to obtain a clock source.

Specifically, the time sequence analysis tool can be used to splice the clock structure of the whole chip after the logic synthesis netlist and the clock constraint file of the top layer and the sub-module are respectively read in.

Meanwhile, a point defined by the clock can be obtained from the clock constraint file to serve as an initial clock source.

S300, tracking backwards step by adopting a recursive algorithm from a clock source; in the tracking process, the starting point and the end point of the top layer and the module clock tree are determined according to the tracking path of the clock tree.

In the step, based on the clock structure information of the whole chip, tracking is carried out step by step from an initial clock source by adopting a recursive algorithm, and the whole chip clock tree network is formed by step tracking. During the tracking process, the starting point and the ending point of the top-level clock tree and the sub-module clock tree can be determined according to the tracking path of the clock tree.

In the tracking process, starting from the top clock source, the start and end points of the top clock tree and each sub-module clock tree are determined as follows, as shown in fig. 2.

A) If the clock is directly connected to the analog IP port from the clock source or the clock is directly connected to the chip output port from the clock source, the section of clock is configured as a top-level clock tree. At this time, the clock source is used as the starting point of the segment clock tree (the top-level clock tree), and the analog IP port or the chip output port is used as the ending point of the segment clock tree.

B) If the clock penetrates from the clock source to a certain submodule and is finally connected to the clock end of a trigger in the submodule, the section of the clock from the clock source to the input end of the submodule is configured into a top-level clock tree, the clock source is used as the starting point of the section of the clock tree, and the input end of the submodule is used as the end point of the section of the clock tree.

Meanwhile, the section of clock from the input end of the sub-module to the internal trigger is configured into a sub-module clock tree, the input end of the sub-module is the starting point of the section of clock tree (the sub-module clock tree), namely the clock source of the section of clock tree, and the internal trigger of the module is the end point of the section of clock tree.

C) If the clock passes through a sub-module from the clock source, i.e. the clock passes into the sub-module and passes out from the sub-module, the input end of the sub-module from the clock source is configured as the top clock tree, the clock source is the starting point of the segment of clock tree, and the input end of the sub-module is the end point of the segment of clock tree.

Meanwhile, the input end of the submodule to the output end of the submodule is used as a submodule clock tree, the input end of the submodule is used as the starting point of the section of clock tree, and the output end of the submodule is used as the end point of the section of clock tree.

Then, the output end of the sub-module is used as the top-next clock source (i.e. the clock starting point of the top-next clock tree), and the tracking is continued step by step until the clock is connected to the clock end of the flip-flop or the port of the analog IP or the output port of the chip, and the tracking is finished. The full-chip clock tree network can be formed through the step-by-step tracking process.

Accordingly, in this embodiment, the step of tracking back step by step using the recursive algorithm from the initial clock source may be as follows.

S310, the initial clock source is used as a top-level clock source.

S320, acquiring a top-level clock source, and judging whether the clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule. If yes, go to step S331; otherwise, step S332 is executed.

S331, when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the aforementioned clock source, performs step S3311. Step S3312 is performed when it is determined that the clock is connected from the clock source to the clock terminal of the flip-flop inside one of the submodules.

S3311, configure this section of clock as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the aforesaid simulation IP port or chip output port as the terminal point of this section of clock tree; step S340 is performed.

S3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; configuring a trigger from the input end of the submodule to the inside as a submodule clock tree, configuring the input end of the submodule as the starting point of the section of clock tree, and configuring the trigger inside the submodule as the end point of the section of clock tree; step S340 is performed.

S332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule; if yes, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source to the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; and configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree.

And configuring the output terminal of the sub-module as the top-level next-level clock source, and returning to step S320 for performing the next-level backward tracking, wherein the top-level next-level clock source is used as the top-level clock source in step S320.

S340, ending the tracking.

The process of forming a full-chip clock tree network by the above-described tracking process is now described in detail with reference to fig. 3.

In fig. 3, a top layer C represents a top layer part of a chip, a module a and a module B belong to a sub-module part of chip division, an analog IP is an internal IP of the chip, and a flip-flop m and a flip-flop n are arranged inside the module a. Wherein, the ports a, e and f are chip ports; the port b is the port of the module A; ports c and d are ports of module B, and port g is an analog IP port.

According to the tracking rule, the clock paths a → b, a → c, a → g, a → e are the top clock tree; b → flip-flop m and flip-flop n are the module A clock tree; c → d is the module B clock tree.

S400, finishing tracking, classifying the clock structures of the top layer and the sub-modules, and forming a clock tree implementation guide file.

In this embodiment, after the tracking is finished, the clock structure information of the top-level clock tree and the sub-module clock tree may be classified to form a clock tree implementation guidance file.

Specifically, the instruction file can be implemented by classifying and respectively using all clock source and end point information of the top layer and the sub-modules as clock trees. At this time, the clock tree implementation guide file may include a top-level clock tree implementation guide file and a sub-module clock tree implementation guide file.

The top-level clock tree implementation guide file comprises starting point and end point information of the top-level clock tree.

The sub-module clock tree implementation guide file comprises starting point and end point information of each sub-module clock tree.

The clock tree implementation guide file can be sent to a later clock tree implementation engineer to serve as a guide file for the chip later clock tree implementation. Specifically, communication account information of clock tree implementing personnel (including but not limited to a clock tree implementing engineer, and also other related personnel) may be obtained, and the top-level clock tree implementing instruction file and the sub-module clock tree implementing instruction file are sent to the clock tree implementing personnel according to the communication account information.

According to the technical scheme provided by the embodiment, the clock tree analysis step is adjusted to the logic synthesis step in the chip design flow from the layout step in the later stage of the chip design flow, the clock information is extracted based on the logic synthesis netlist by using a time sequence analysis tool to form a clock tree network, and then the clock trees are classified to form a clock tree realization guide file to be used as the guide information of the later clock tree realization step. On one hand, because the correctness of the clock tree is analyzed and verified in the logic synthesis step, compared with the method for analyzing and verifying the correctness of the clock tree in the clock tree realization step in the conventional chip design flow, the technical scheme can obviously reduce the work from the logic synthesis to the clock tree realization of the iteration process of the clock tree verification, shorten the clock tree verification period, reduce the waste of design resources and shorten the chip design period. On the other hand, a full-chip clock tree network is extracted from the logic comprehensive netlist, the clock tree analysis process adopts a top-down mode, the continuity of the full-chip clock structure is firstly determined, then the clock structure is segmented into each submodule according to module division information, a clock tree implementation guide file is formed, and the efficiency and the accuracy of later clock tree implementation work can be improved. Meanwhile, the top layer and the sub-modules of the chip can carry out clock tree design on the premise of ensuring connectivity, do not depend on constraint files completely, do not need iteration at the same time, and improve the efficiency of clock tree design.

The invention further provides a chip design method.

The chip design method at least comprises a clock design step, a logic synthesis step, a layout step, a clock tree realization step and a wiring step. Preferably, the chip design method may include a specification formulation step, an architecture design step, a clock design step, a code compiling step, a simulation verification step, a logic synthesis step, a form verification step, a testability design step, a layout step, a clock tree implementation step, a wiring step, a form verification step, a parasitic parameter extraction step, a timing verification step, and a physical layout verification step.

In the logic synthesis step, the clock tree implementation guide file may be obtained by: acquiring logic comprehensive netlist information of a top layer and sub-modules of a chip, module information of chip segmentation and clock constraint file information; splicing the clock structure of the whole chip according to the acquired information, and acquiring a point defined by a clock from a clock constraint file as an initial clock source; based on the clock structure information of the whole chip, tracking from an initial clock source to the back step by adopting a recursive algorithm to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree; and after tracking is finished, classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file. And taking the clock tree realization guide file as the guide information of the clock tree realization step in the later period.

Other technical features are referred to in the previous embodiments and are not described herein.

In another embodiment of the present invention, a chip design system is further provided.

The chip design system at least comprises a clock design unit, a logic synthesis unit, a layout unit, a clock tree realization unit and a wiring unit. Preferably, the chip design method may include a specification formulation unit, an architecture design unit, a clock design unit, a code compiling unit, a simulation verification unit, a logic synthesis unit, a form verification unit, a testability design unit, a layout unit, a clock tree implementation unit, a wiring unit, a form verification unit, a parasitic parameter extraction unit, a timing verification unit, and a physical layout verification unit.

Wherein the logic synthesis unit comprises a clock analysis module. The clock analysis module is configured to: acquiring logic comprehensive netlist information of a top layer and sub-modules of a chip, module information of chip segmentation and clock constraint file information; splicing the clock structure of the whole chip according to the acquired information, and acquiring a point defined by a clock from a clock constraint file as an initial clock source; based on the clock structure information of the whole chip, tracking from an initial clock source to the back step by adopting a recursive algorithm to form a whole-chip clock tree network; in the tracking process, determining the starting point and the end point of a top-level clock tree and a sub-module clock tree according to the tracking path of the clock tree; after the tracking is finished, classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree realization guide file; and sending the clock tree realization guide file to the clock tree realization unit.

Referring to the foregoing embodiment for other technical features, the logic synthesis unit may include a corresponding processing module to perform corresponding information processing, which is not described herein again.

The invention further provides a device for extracting the clock tree based on the synthesized netlist in the chip design.

The device comprises an information acquisition module, an initialization module, a clock tree tracking module and a result processing module.

The information acquisition module is used for acquiring logic synthesis netlist information of a top layer and sub-modules of the chip, module information of chip segmentation and clock constraint file information in the logic synthesis step.

And the initialization module is used for splicing the clock structure of the whole chip according to the acquired information and acquiring a point defined by the clock from the clock constraint file as an initial clock source.

The clock tree tracking module is used for tracking from the initial clock source to the backward step by adopting a recursive algorithm based on the clock structure information of the whole chip to form a whole-chip clock tree network; and in the tracking process, determining the starting point and the end point of the top-level clock tree and the sub-module clock tree according to the clock tree tracking path.

And the result processing module is used for classifying the clock structure information of the top-layer clock tree and the sub-module clock tree to form a clock tree implementation guide file after the tracking is finished.

In this embodiment, the clock tree tracking module is configured to perform the following steps:

s310, the initial clock source is used as a top-level clock source.

S320, acquiring a top-level clock source, and judging whether a clock is directly connected to the analog IP port from the clock source or directly connected to the chip output port or connected to the clock end of a trigger in a submodule; if yes, go to step S331; otherwise, step S332 is executed.

S331, when determining that the clock is directly connected to the analog IP port or directly connected to the chip output port from the clock source, performs step S3311, and when determining that the clock is connected to the clock terminal of the flip-flop in one of the submodules from the clock source, performs step S3312.

S3311, configure the segment of clock as the top level clock tree, configure the clock source as the start point of the segment of clock tree, configure the analog IP port or the chip output port as the end point of the segment of clock tree, and execute step S340.

S3312, configure the aforesaid clock source to the input end of the submodule as the top clock tree, and configure the aforesaid clock source as the starting point of this section of clock tree, configure the input end of this submodule as the terminal point of this section of clock tree; and configuring the flip-flop from the input end of the sub-module to the inside as a sub-module clock tree, configuring the input end of the sub-module as the starting point of the segment clock tree, configuring the flip-flop from the inside of the sub-module as the ending point of the segment clock tree, and executing step S340.

S332, judging whether the clock penetrates into a submodule from the clock source and penetrates out of the submodule, if so, configuring the clock source to the input end of the submodule as a top-level clock tree, configuring the clock source as the starting point of the section of clock tree, and configuring the input end of the submodule as the end point of the section of clock tree; configuring the input end of the submodule to the output end of the submodule into a submodule clock tree, configuring the input end of the submodule into the starting point of the section of clock tree, and configuring the output end of the submodule into the end point of the section of clock tree; and configuring the output end of the submodule as a top-level next-level clock source, and returning to the step S320 for next-level backward tracking.

S340, ending the tracking.

Other technical features are described in the previous embodiment and are not described in detail herein.

In the foregoing description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the various components may be selectively and operatively combined in any number within the intended scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be interpreted as inclusive or open-ended, rather than exclusive or closed-ended, by default, unless explicitly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. Common terms found in dictionaries should not be interpreted too ideally or too realistically in the context of related art documents unless the present disclosure expressly limits them to that. Any changes and modifications of the present invention based on the above disclosure will be within the scope of the appended claims.