阅读说明：本技术 Cpu配置方法、cpu配置装置及芯片仿真方法 (CPU configuration method, CPU configuration device and chip simulation method ) 是由 唐飞 朱佳轶 常志恒 于 2021-07-02 设计创作，主要内容包括：本申请提供了一种CPU配置装置、CPU配置方法及芯片仿真方法,其中,所述CPU配置方法,应用于芯片仿真时通过CPU配置引擎对被测试对象进行配置,所述被测试对象具有多个与CPU相连接的子模块,所述方法包括：为与所述CPU连接的每一所述子模块配置一CPU配置引擎；以及基于每一所述CPU配置引擎配置各子模块。本申请通过例化复制多份CPU配置引擎,分别连接到每一个独立的具有CPU配置接口的子模块上,完成多个子模块配置的并行下载从而缩短了每一个测试用例的仿真时间。同时,支持多种API供用户进行扩展性编程,并为每一个CPU配置引擎搭配后门访问模式,进一步提高配置效率,缩短配置时间,在相同的时间内完成更多测试用例的测试。(The application provides a CPU configuration device, a CPU configuration method and a chip simulation method, wherein the CPU configuration method is used for configuring a tested object through a CPU configuration engine when being applied to chip simulation, the tested object is provided with a plurality of sub-modules connected with a CPU, and the method comprises the following steps: configuring a CPU configuration engine for each sub-module connected with the CPU; and configuring each submodule based on each CPU configuration engine. The method and the device have the advantages that multiple CPU configuration engines are copied in an instancing mode and are respectively connected to each independent sub-module with the CPU configuration interface, and the parallel downloading of the configuration of the sub-modules is completed, so that the simulation time of each test case is shortened. Meanwhile, various APIs are supported for the user to conduct the extensible programming, a back door access mode is matched for each CPU configuration engine, the configuration efficiency is further improved, the configuration time is shortened, and the test of more test cases is completed in the same time.)

1. A CPU configuration method is applied to chip simulation and configures a tested object through a CPU configuration engine, wherein the tested object is provided with a plurality of sub-modules connected with a CPU, and the method is characterized by comprising the following steps: configuring a CPU configuration engine for each sub-module connected with the CPU; and

configuring each submodule based on each CPU configuration engine.

2. The CPU configuration method of claim 1, wherein the CPU configuration engine is configured with an application program interface, the method further comprising: and performing expansibility programming based on the application program interface.

3. The CPU configuration method according to claim 1 or 2, further comprising:

and configuring each submodule through a quick configuration downloading mode supporting the configuration of the backdoor.

4. A CPU configuration device, which is used for configuring a tested object through a CPU configuration engine when being applied to chip simulation, wherein the tested object is provided with a plurality of sub-modules connected with a CPU, and the CPU configuration device is characterized by comprising:

and the CPU configuration engines are respectively in communication connection with the sub-modules and are configured to be used for respectively configuring the sub-modules.

5. The CPU configuration apparatus of claim 4, wherein the CPU configuration engine is configured with: and the application program interface is used for the user to perform extensible programming.

6. The CPU configuration device of claim 5, wherein the application program interface is configured to: ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by address and/or ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by register or memory name.

7. The CPU configuration device according to any of claims 4-6, wherein the CPU configuration engine is configured to: and a rapid configuration downloading mode of back door configuration is supported, so that the configuration of each submodule is realized without handshaking logic through a CPU bus.

8. A chip simulation method, wherein the CPU configuration apparatus of any one of claims 1 to 3 or the CPU configuration apparatus of any one of claims 4 to 7 is applied to configure a test object.

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a CPU configuration method, a CPU configuration apparatus, and a chip simulation method.

Background

In an Application Specific Integrated Circuit (ASIC) verification process, generally, we will refer to chip level (chip level/system level), sub-system level (sub-system level) and module level (module level/unit level) by hierarchical division, which is beneficial to disassembling functional modules, realizing the parallel work cooperation of personnel, and improving the execution efficiency of projects. The appropriate complexity module also helps to estimate the appropriate workload and personnel allocation from both design and verification considerations, the design is ultimately integrated by modularity, and the verified environment, after modularity, can also be easily reused in a more advanced verification environment. Any test case typically requires a DUT internal register or memory to be configured to operate in a particular mode through the CPU interface before sending a stimulus. When performing chip system level and subsystem level verification tasks, all modules included in the system need to be configured in corresponding working modes through a CPU interface.

In the prior art, only one CPU configuration interface is provided for one chip system level and subsystem level verification environment, and in a conventional verification process, all configuration information is downloaded to corresponding sub-modules one by one according to needs by using the unique CPU configuration interface. The configuration time required for the test case is completely dependent on the number of configured items, and the more the number of items, the longer the time is.

Because only a unique CPU configuration interface is provided, each configuration needs to be downloaded one by one, a large amount of configuration time is consumed, the number of configured items and the simulation configuration time are in a linear growth relationship, and the simulation efficiency is greatly reduced along with the increase of the number of configured items.

Disclosure of Invention

In view of the above technical problems in the prior art, the present application provides a CPU configuration apparatus and a CPU configuration method for completing module-level configuration in parallel by using a multi-CPU emulation configuration engine, so as to improve the system-level emulation task configuration efficiency.

In order to achieve the above object, the present application provides a CPU configuration method, which is applied to chip simulation to configure a tested object through a CPU configuration engine, where the tested object has a plurality of sub-modules connected to a CPU, and the method includes: configuring a CPU configuration engine for each sub-module connected with the CPU; and configuring each submodule based on each CPU configuration engine.

Optionally, the CPU configuration engine is configured with an application program interface, and the method further includes: and performing expansibility programming based on the application program interface.

Optionally, the CPU configuration method further includes: and configuring each submodule through a quick configuration downloading mode supporting the configuration of the backdoor.

In order to achieve the above object, the present application provides a CPU configuration apparatus, which is applied to chip simulation and configures a tested object through a CPU configuration engine, where the tested object has a plurality of sub-modules connected to a CPU, and the apparatus includes: and the CPU configuration engines are respectively in communication connection with the sub-modules and are configured to be used for respectively configuring the sub-modules.

Optionally, the CPU configuration engine is configured with: and the application program interface is used for the user to perform extensible programming.

Optionally, the application program interface is configured to: ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by address and/or ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by register or memory name.

Optionally, the CPU configuration engine is configured to: and a rapid configuration downloading mode of back door configuration is supported, so that the configuration of each submodule is realized without handshaking logic through a CPU bus.

In order to achieve the above object, the present application provides a chip simulation method, which applies the above-mentioned CPU configuration apparatus or the above-mentioned CPU configuration apparatus to configure a tested object.

The method and the device have the advantages that multiple CPU configuration engines are copied in an instancing mode and are respectively connected to each independent sub-module with the CPU configuration interface, and the parallel downloading of the configuration of the sub-modules is completed, so that the simulation time of each test case is shortened. Meanwhile, various APIs are supported for the user to conduct the extensible programming, a back door access mode is matched for each CPU configuration engine, the configuration efficiency is further improved, the configuration time is shortened, and the test of more test cases is completed in the same time.

Drawings

FIG. 1 is a schematic diagram of a CPU and a CPU configuration device according to an embodiment of the present application;

fig. 2 is a schematic diagram of a CPU configuration method provided in an embodiment of the present application.

Detailed Description

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the present application is not limited to the following embodiments, but includes various changes, substitutions, and alterations within the technical scope of the present disclosure. The terms "first," "second," and the like may be used to explain various elements, the number of elements is not limited by such terms. These terms are only used to distinguish one element from another. Thus, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment. The singular forms "a", "an" and "the" do not exclude the plural forms unless the context requires otherwise.

In the following description, the terms "comprises" or "comprising" are used to indicate features, numbers, steps, operations, elements, parts, or combinations thereof, and do not exclude other features, numbers, steps, operations, elements, parts, or combinations thereof.

In an Application Specific Integrated Circuit (ASIC) verification process, the verification process is divided according to levels, and generally the verification process is called a chip level (chip level/system level), a subsystem level (sub-system level) and a module level (module level/unit level). Proper design of module complexity also helps to estimate the appropriate workload and personnel allocation from both design and verification aspects, the design is ultimately integrated by modularity, and the verified environment, after modularity, can also be easily reused in a more advanced verification environment. Generally, any test case needs to configure the internal register or memory of the DUT through the CPU interface before sending a stimulus, so that it can operate in a specific mode. When performing chip system level and subsystem level verification tasks, all modules included in the system need to be configured in corresponding working modes through a CPU interface.

For a chip system level and subsystem level verification environment, only one CPU configuration interface is provided, and in the traditional verification process, all configuration information can be downloaded to corresponding sub-modules one by one according to needs by using the unique CPU configuration interface. The configuration time required for the test case is completely dependent on the number of configured items, and the more the number of items, the longer the time is.

Because only a unique CPU configuration interface is provided, each configuration is downloaded one by one, a large amount of configuration time is consumed, the number of configured items and the simulation configuration time are in a linear growth relationship, and the simulation efficiency is greatly reduced along with the increase of the number of configured items.

In order to solve the above technical problem, this embodiment provides a CPU configuration method, which is applied to configure a tested object (DUT) during chip simulation, where the tested object includes a plurality of sub-modules, each of which includes a module 0 to a module 7, as shown in fig. 1, taking the case where the CPU includes a main CPU and three sub-CPUs, each of which includes a sub-CPU 1, a sub-CPU 2 and a sub-CPU 3, each of the sub-CPUs connects to a plurality of sub-modules, where the sub-CPU 1 connects to the module 0, the module 1 and the module 2, the sub-CPU 2 connects to the module 3, the module 4 and the module 5, and the sub-CPU 3 connects to the module 6 and the module 7.

The method provided by the embodiment is shown in fig. 2, and includes: configuring a CPU configuration engine (namely, CPU configuration engines 0 to 7 in FIG. 1) for each sub-module connected with a CPU (main CPU or any sub-CPU); and configuring the submodules based on each CPU configuration engine.

By the arrangement, the submodules can be configured in parallel, and the time for configuring the CPU is greatly reduced.

Optionally, the CPU configuration engine is configured with an Application Programming Interface (also called API Interface), which is a predefined Interface (e.g. function, HTTP Interface), or a convention for linking different components of a software system, and is used to provide a set of routines that the Application and a developer can access based on certain software or hardware, without accessing source code or understanding details of internal working mechanisms.

The API interface may include: the method comprises the following steps of ordinary reading, ordinary writing, burst reading, burst writing, mask writing and the like according to addresses, and ordinary reading, ordinary writing, burst reading, burst writing, mask writing and the like according to register or memory names. The user can call the API interface in a self-coding mode to write the configuration codes of the respective modules.

Optionally, the method for configuring the CPU further includes: and performing extensible programming based on the application program interface.

Optionally, the CPU configuration method further includes: and configuring each submodule through a quick configuration downloading mode supporting the configuration of the backdoor.

The premise of back door configuration is that each corresponding CPU configuration engine acquires the logic hierarchical relationship between the register and the memory of the configured object, then rewrites the value of the configured object into the corresponding configuration value through a strong assignment statement provided by verilog description language, or reads the current value of the configured object by using a strong value statement.

Optionally, with continuing reference to fig. 1, this embodiment provides a CPU configuration apparatus, which is applied to chip simulation, where a CPU (main CPU or sub-CPU) is connected to a plurality of sub-modules, and includes: and the CPU configuration engines are respectively in communication connection with the sub-modules and are configured for respectively configuring the sub-modules.

Optionally, the CPU configuration engine is configured with: an application program interface (not shown) for extensible programming by a user.

Optionally, the application program interface is configured to: ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by address and/or ordinary read, ordinary write, burst read, burst write, masked write, etc. operations by register or memory name.

Optionally, the CPU configuration engine is configured to: and a rapid configuration downloading mode of back door configuration is supported, so that the configuration of each submodule is realized without handshaking logic through a CPU bus.

Optionally, this embodiment provides a chip simulation method, which applies the CPU configuration apparatus described above or the CPU configuration apparatus described above to configure a DUT.

The method and the device have the advantages that multiple CPU configuration engines are copied in an instancing mode and are respectively connected to each independent sub-module with the CPU configuration interface, and the parallel downloading of the configuration of the sub-modules is completed, so that the simulation time of each test case is shortened. Meanwhile, various APIs are supported for the user to conduct the extensible programming, a back door access mode is matched for each CPU configuration engine, the configuration efficiency is further improved, the configuration time is shortened, and the test of more test cases is completed in the same time.

Since the technical contents and features of the present invention have been disclosed above, those skilled in the art can make various substitutions and modifications without departing from the spirit of the present invention based on the teaching and disclosure of the present invention, and therefore, the scope of the present invention is not limited to the disclosure of the embodiments, but includes various substitutions and modifications without departing from the present invention, and is covered by the claims of the present patent application.