阅读说明：本技术 半导体工艺所用的方法 (Method for semiconductor processing ) 是由 蔡承晏 吴仲强 黄泰维 锺鸿钦 李威缙 李达元 苏庆煌 庄媖涓 刘冠廷 于 2019-02-01 设计创作，主要内容包括：此处所述的实施例关于对半导体基板上的不同晶体管的金属栅极中所用的材料进行预沉积处理。在一实施例中,方法包括暴露第一装置的第一含金属层与第二装置的第二含金属层至反应物,以分别形成多个单层于第一含金属层与第二含金属层上。第一装置与第二装置位于基板上。第一装置包括第一栅极结构,且第一栅极结构包括第一含金属层。第二装置包括第二栅极结构,且第二栅极结构包括第二含金属层,而第一含金属层与第二含金属层不同。暴露第一含金属层与第二含金属层上的单层至氧化剂,以提供单层所用的羟基封端表面。之后形成第三含金属层于第一含金属层与第二含金属层上的单层的羟基封端表面上。(embodiments described herein relate to pre-deposition processing of materials used in metal gates of different transistors on a semiconductor substrate. In one embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively. The first device and the second device are located on the substrate. The first device includes a first gate structure, and the first gate structure includes a first metal-containing layer. The second device includes a second gate structure, and the second gate structure includes a second metal-containing layer, and the first metal-containing layer is different from the second metal-containing layer. Exposing the monolayer on the first metal-containing layer and the second metal-containing layer to an oxidizing agent to provide a hydroxyl terminated surface for the monolayer. A third metal-containing layer is then formed on the hydroxyl-terminated surface of the monolayer over the first metal-containing layer and the second metal-containing layer.)

1. A method for semiconductor processing, comprising:

Exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively, the first device and the second device being on a substrate, the first device including a first gate structure, the first gate structure including the first metal-containing layer, the second device including a second gate structure, the second gate structure including the second metal-containing layer, the first metal-containing layer being different from the second metal-containing layer;

Exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidizing agent to provide a hydroxyl-terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and

Forming a third metal-containing layer on the hydroxyl-terminated surfaces of the monolayers above the first metal-containing layer and the second metal-containing layer.

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to pre-processing work function materials for different types of metal gates on the same semiconductor substrate.

Background

In fabricating field effect transistors, such as fin field effect transistors, metal gates may be used instead of polysilicon gates to improve device performance. The step of forming the metal gate may include sequentially forming a gate dielectric layer, a barrier layer, a work function layer, and a metal liner layer in the high aspect ratio trench, and then filling the trench with a gate material. The work function layer may be made of different materials for different types of transistors, such as p-type field effect transistors or n-type field effect transistors, to fine tune the threshold voltage of the transistors and to improve the electrical performance of the device as desired. However, as dimensions shrink, new challenges arise.

Disclosure of Invention

an embodiment of the present invention provides a method for a semiconductor process, including: exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively, the first device and the second device being on a substrate, the first device including a first gate structure, the first gate structure including the first metal-containing layer, the second device including a second gate structure, the second gate structure including the second metal-containing layer, the first metal-containing layer being different from the second metal-containing layer; exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidizing agent to provide a hydroxyl-terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and forming a third metal-containing layer on the hydroxyl-terminated surface of the monolayer over the first metal-containing layer and the second metal-containing layer.

Drawings

Fig. 1A and 1B are flow diagrams of exemplary methods of fabricating semiconductor devices in some embodiments.

Fig. 2-4 are partial perspective views of a semiconductor device corresponding to various stages of fabrication in some embodiments.

Fig. 5-11 are partial cross-sectional views of a semiconductor device at various stages of fabrication in some embodiments.

Fig. 12 shows a simplified semiconductor device with portions of the gate structure in three device regions during an intermediate stage of the process.

Fig. 13 illustrates a simplified semiconductor device at an intermediate stage of processing in some embodiments.

Fig. 14A-14C illustrate X-ray photoelectron spectra of titanium aluminum carbide deposited on different substrates in some embodiments.

Description of reference numerals:

A-A': section plane

T1: a first thickness

T2: second thickness

T3: third thickness

T4, T5, T6: thickness of

100: flow chart

102. 104, 106, 108, 110, 112, 114, 116, 118, 120, 122: step (ii) of

200: substrate

201. 1200, 1300: semiconductor device with a plurality of semiconductor chips

202: fin

206. 240: interfacial dielectric layer

208: virtual grid

210: mask and method for manufacturing the same

212: virtual grid structure

212a, 212 b: replacement gate structure

213a, 213b, 213 c: source/drain region

214. 230, 1301, 1303, 1305: groove

216: isolation region

218: interlayer dielectric layer

220: gate spacer

224. 259: upper surface of

232: surface of

234: etching process

242. 1210, 1310: gate dielectric layer

244. 1208, 1308: work function adjusting layer

245: cover layer

247: barrier layer

248: patterned mask structure

250 a: first device region

250b, and (3): second device region

251: single layer

252: bottom anti-reflective coating

253: pretreatment process

254: photoresist

255: metallic backing layer

257: grid metal

261. 263: treated surface

265: hydroxy end capping

270. 272, 297, 299, 1360, 1362, 1364: illustration of the drawings

293. 295: mixing layer

1202. 1204, 1206, 1302, 1304, 1306: device area

1212: metal layer

1312: a first metal layer

1314: second metal layer

1316: a third metal layer

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The specific components and arrangements are disclosed to simplify the present disclosure and not to limit the present disclosure. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the various examples of the present disclosure may be repeated with reference numbers, but such repetition is merely intended to simplify and clarify the description and does not imply that there is a similar correspondence between elements having the same reference numbers in different embodiments and/or arrangements.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. Elements may also be rotated through 90 or other angles, and directional terminology is used for purposes of illustration only.

Embodiments of the present invention generally relate to semiconductor devices and, more particularly, to pre-processing work function materials for different types of metal gates on the same semiconductor substrate. Generally, the pretreatment may passivate the surface of the work function material to produce a monolayer such as alumina or silica. The pretreatment may ensure that the layer subsequently deposited on the passivated surface of the work function material has a more uniform thickness in the metal gates of different kinds of transistors to minimize the impact on the gap-filling performance and/or threshold voltage of other layers in the metal gates. Other embodiments include methods of providing different metal layers between a work function adjusting layer and a gate dielectric layer for different device regions of a field effect transistor, such as an n-type field effect transistor or a p-type field effect transistor device, to adjust the multi-threshold voltage of the n-type or p-type device. Different metal layers may affect the composition and thickness of the work function adjusting layer and change the work function value of the work function adjusting layer deposited thereon. Different work function adjusting layers on different substrates can provide different n-type work functions to achieve the purpose of adjusting the multi-threshold voltage without stacking a plurality of metal layers. Thus, more space is provided for metal gate filling.

Some embodiments of the invention are summarized above. It is understood that the pre-treatment process may be implemented in a planar transistor device or a three-dimensional transistor device (e.g., the semiconductor device 201 according to an embodiment of the present invention). Some of the implementable devices described herein include fin fets, horizontal wraparound fets, vertical wraparound fets, nanowire channel fets, strained semiconductor devices, soi devices, or other devices that may be advantageous for mitigating problems such as those related to loading effects and/or substrate-related growth processes due to pre-processing.

Fig. 1A and 1B show a flowchart 100 of an exemplary method of fabricating a semiconductor device 201 in various embodiments of the present invention. Fig. 2 to 4 are partial perspective views of the semiconductor device corresponding to various stages of the flowchart in fig. 1A and 1B, and fig. 5 to 11 are partial sectional views of the semiconductor device corresponding to various stages of the flowchart in fig. 1A and 1B. It is noted that flowchart 100 may be used to form any other semiconductor structure not mentioned herein. It will be understood by those of ordinary skill in the art that the drawings and descriptions are not intended to limit all of the processes for forming semiconductor devices and related structures. Although the disclosure and figures described herein contain various steps, the order of the steps is not limited, nor does it imply the presence or absence of intervening steps. Unless specifically mentioned, the sequence of steps in the figures or illustrated are for explanation only and do not exclude the possibility of individual steps actually being performed simultaneously or in a partially rather than fully overlapping manner.

A step 102 beginning with flowchart 100 provides a substrate 200 having a dummy gate structure 212 formed on a plurality of fins 202 on substrate 200, as shown in figure 2. The substrate 200 may be or include a semiconductor base substrate, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate may comprise a semiconductor element (e.g., silicon or germanium), a semiconductor compound, a semiconductor alloy, or a combination thereof. Other substrates may also be used.

Each fin 202 provides an active region where one or more devices are formed. The fin 202 may be fabricated by performing suitable processes on the substrate 200, including masking, photolithography, and/or etching processes, to form the trench 214 into the substrate 200, while leaving the fin (e.g., fin 202) extending upward from the substrate 200. Fins 202 may be patterned by any suitable method. For example, the method of patterning fin 202 may employ one or more photolithography processes, including a double patterning or a multiple patterning process. Generally, double patterning or multiple patterning processes include photolithography and self-aligned processes, which produce a pattern pitch that may be smaller than that obtained using a single direct photolithography process. For example, some embodiments form a sacrificial layer on a substrate and pattern the sacrificial layer using a photolithography process. Spacers may be formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may be used to pattern fin 202 and form trench 214.

An insulating material, such as an oxide (e.g., silicon oxide), nitride, the like, or combinations thereof, may then be filled into the trenches 214 using a suitable deposition technique. Other insulating materials formed by any acceptable process may also be used. The insulating material may be recessed using an acceptable etch process to form isolation regions 216. Fins 202 may protrude upward from between adjacent isolation regions 216 due to the recessing of the insulating material.

The isolation regions 216 may separate the semiconductor device 201 into various device regions. In the illustrated example, the semiconductor device 201 includes a first device region 250a and a second device region 250 b. One or more devices may be formed in the first device region 250a and one or more devices may be formed in the second device region 250 b. For example, each of the first and second device regions 250a and 250b may include a certain type of device (e.g., p-type device or n-type device), and the device characteristics may be different in each of the first and second device regions 250a and 250 b. In some embodiments, the semiconductor device 201 may be a multi-threshold voltage integrated circuit device for optimizing delay or power. In these examples, the devices in the first device region 250a and the second device region 250b may be n-type ultra-low threshold voltage devices, n-type standard voltage devices, n-type high threshold voltage devices, p-type ultra-low threshold voltage devices, p-type standard threshold voltage devices, p-type high threshold voltage devices, or any combination thereof. For example, an n-type device (e.g., an n-type finfet device) may be located in the first device region 250a and may be an n-type standard threshold voltage device, while another n-type device may be located in the second device region 250b and may be an n-type ultra low threshold voltage device. It is understood that one of ordinary skill in the art may employ any type of device in the device region and may employ any number of metal gates, each comprising a combination of various types of work function modifying layers (as described below) and/or layers, to achieve the desired multi-threshold voltage.

Dummy gate structure 212 is then formed on fin 202. The dummy gate structures 212 each include an interfacial dielectric layer 206, a dummy gate 208, and a mask 210. The interfacial dielectric layer 206, the dummy gate 208, and the mask 210 used for the dummy gate structure 212 may be formed by sequentially forming respective layers and then patterning the layers to form the dummy gate structure 212. For example, the layer for interfacial dielectric layer 206 may comprise or may be silicon oxide, silicon nitride, the like, or multiple layers thereof, and may be thermally and/or chemically grown on fin 202, or conformably deposited (e.g., plasma enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique). The layer used for the dummy gate 208 may comprise or may be silicon (e.g., polysilicon) or another material, which may be deposited by chemical vapor deposition, physical vapor deposition, or any suitable deposition technique. The layer used for the mask 210 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof, deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any suitable deposition technique. The layers for the mask 210, the dummy gate 208, and the interfacial dielectric layer 206 may then be patterned to form the mask 210, the dummy gate 208, and the interfacial dielectric layer 206 for each dummy gate structure 212, and the patterning process may be performed by photolithography and one or more etching processes.

Step 104 forms gate spacers 220 along sidewalls of dummy gate structure 212 (e.g., sidewalls of interfacial dielectric layer 206, dummy gate 208, and mask 210), and gate spacers 220 are formed on fin 202. For example, the gate spacers 220 may be formed by conformably depositing one or more layers of the gate spacers 220, rather than isotropically etching one or more layers. One or more layers of the gate spacer 220 may comprise a material different from that used for the dummy gate structure 212. In one embodiment, the gate spacers 220 may comprise or may be a dielectric material such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multilayers thereof, or combinations thereof, and may be deposited by chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. An anisotropic etch process such as a reactive ion etch, a neutral beam etch, or any suitable etch process may then be performed to remove portions of the spacer layer and form the gate spacers 220, as shown in fig. 3.

After forming gate spacers 220, source/drain regions 213a and 213b may be formed in fin 202. In some examples, dummy gate structure 212 may be used as a mask and etched recessed into fin 202, such that recesses are formed on both sides of dummy gate structure 212. Epitaxial material may then be epitaxially grown in the recesses to form source/drain regions 213a and 213 b. In additional or alternative embodiments, source/drain regions 213a and 213b may be formed by implanting dopants into fin 202 and/or epitaxial source/drain regions using dummy gate structure 212 as a mask, such that source/drain regions are formed on both sides of dummy gate structure 212.

An interlayer dielectric 218 may then be formed over the substrate 200 and the gate spacers 220. In some embodiments, the semiconductor device 201 may also include a contact etch stop layer (not shown) below the interlayer dielectric layer 218 and above the substrate 200 and the gate spacers 220. The contact etch stop layer may comprise or may be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The interlayer dielectric layer 218 may comprise tetraethoxysilane oxide, silicon oxide, a low dielectric constant material (a material having a dielectric constant lower than silicon oxide, such as silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on oxide, carbon silicon material, compounds thereof, composites thereof, the like, or combinations thereof.) the deposition of the interlayer dielectric layer 218 may be spin-on, chemical vapor deposition, flowable chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, or any suitable deposition technique, followed by a chemical-mechanical planarization process to planarize the interlayer dielectric layer 218 and remove the dummy gate structures 212 to define an upper surface 224 substantially coplanar with the upper surface of the dummy gates 208 of the gate structures 212, as shown in fig. 3.

In step 106, the dummy gate structure 212 is removed using one or more etching processes. Once dummy gate structure 212 is removed, trench 230 is formed to expose at least a portion of surface 232 of isolation region 216 (see fig. 4) and the channel surface of fin 202. The trench 230 allows a gate structure, such as a replacement gate structure, to be formed therein. In some examples, the dummy gate 208 exposed at the upper surface 224 of the ild 218 is removed by an etching process, and then the interfacial dielectric layer 206 is removed by a different etching process. The etch process may comprise a suitable wet etch, dry (plasma) etch, and/or other suitable process. For example, the dry etching process may employ chlorine-containing gases, fluorine-containing gases, other etching gases, or combinations thereof. The wet etching solution may comprise ammonium hydroxide, hydrofluoric acid or diluted hydrofluoric acid, deionized water, tetramethylammonium hydroxide, other suitable wet etching solutions, or combinations thereof. Trenches 230 are thus formed between gate spacers 220 (where dummy gate structures 212 are removed) and the channel region of fin 202 is exposed through trenches 230.

fig. 5 to 11 are cross-sectional views of the semiconductor device at a subsequent stage of fabrication. The cross-sectional views of fig. 5 to 11 correspond to the section a-a' in fig. 4. Section a-a' is along fin 202 and is generally perpendicular to the longitudinal direction of trench 230.

Step 108 forms a layer for the replacement gate structures 212a and 212b for the first device region 250a and the second device region 250b in the trench 230 (i.e., where the dummy gate structure 212 is removed). In the illustrated embodiment, the layers used to replace the gate structures 212a and 212b include an interfacial dielectric layer 240, a gate dielectric layer 242, a cap layer 245, and optionally a barrier layer 247, which are sequentially formed in the trench 230 between the gate spacers 220 in the first device region 250a and the second device region 250b, as shown in fig. 5. Interfacial dielectric layer 240 is formed on the sidewalls and top of fin 202 along the channel region defined under the replacement gate structure and between the source/drain regions. For example, interfacial dielectric layer 240 may be any suitable dielectric layer formed by thermal oxidation or chemical oxidation of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride) formed by fin 202, and/or by chemical vapor deposition, atomic layer deposition, molecular beam deposition, or any suitable deposition technique.

A gate dielectric layer 242 may be conformally deposited in the trench 230 over the interfacial dielectric layer 240, on the sidewalls of the gate spacers 220, and on the upper surfaces of the interlayer dielectric layer 218 and the contact etch stop layer, if employed. The gate dielectric layer 242 may comprise or may be silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other suitable dielectric materials. The high-k dielectric material may have a dielectric constant greater than about 4.0 (e.g., about 7.0), and may comprise a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof. The deposition method of the gate dielectric layer 242 may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique.

A cap layer 245 and a barrier layer 247 may then be conformally deposited over the gate dielectric layer 242. The cap layer 245 and the barrier layer 247 may comprise tantalum and/or titanium nitrides, silicides, carbonitrides, and/or aluminum nitrides; tungsten nitrides, carbonitrides, and/or carbides; (ii) an analog; or combinations of the foregoing; and the deposition method may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or another deposition technique. In some examples, a cap layer 245 (e.g., a titanium nitride layer) is conformally formed on the gate dielectric layer 242, and a barrier layer 247 (e.g., a tantalum nitride layer) is conformally formed on the cap layer 245. In some examples, barrier layer 247 may be a work function adjusting layer or portion thereof. In some examples, barrier layer 247 may be omitted. Although cap layer 245 and barrier layer 247 in the figures are each a single layer, it should be understood that one or more barrier layers and/or cap layers may be implemented in any desired order, depending on the desired application and threshold voltage of the device.

After forming the gate dielectric layer 242, the cap layer 245, and the barrier layer 247, the workfunction adjusting layer 244 may be conformally formed on the barrier layer 247. The work function adjusting layer 224 may be or include a single layer of material or multiple layers of different materials. Although the work function adjusting layer 244 is shown as a single layer, it is understood that the work function adjusting layer 244 may comprise one or more layers of work function material, depending on the desired application and threshold voltage of the device. In the embodiment shown in fig. 6, the work function layer 244 is a work function layer formed in the first device region 250a and the second device region 250 b.

The work function value is related to the material composition of the work function adjusting layer 244. The material of the work function adjusting layer 244 is selected to adjust its work function value so that a desired threshold voltage for devices to be formed in the respective regions may be achieved. Suitable examples of work function materials for p-type devices may include titanium aluminum nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, tungsten carbonitride, other suitable materials having a work function between 4.8eV and 5.2eV, or a combination of any of the above. Suitable examples of work function materials for n-type devices may include titanium, aluminum, tantalum aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable materials having a work function between 3.9eV and 4.3eV, or a combination of any of the above. In some embodiments, the work function adjusting layer 244 for a pfet includes respective layers of titanium aluminum nitride and titanium nitride, while the work function adjusting layer 244 for an nfet includes respective layers of titanium aluminum carbide and titanium aluminum oxide. In some examples, the work function adjusting layer 244 for an n-type field effect transistor comprises respective layers of titanium aluminum carbide and titanium nitride. Any of the materials described herein may be deposited in any desired order.

The deposition method of the work function adjusting layer 224 may be atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, and/or any other suitable process. In one example described herein, the work function adjusting layer 244 is formed using an atomic layer deposition process at a temperature between about 200 ℃ and about 600 ℃. The thickness of the work function adjusting layer 244 may be varied and adjusted by varying parameters of the atomic layer deposition process, such as the number of deposition cycles, the number of precursor pulses, the pulse frequency, the substrate temperature, the pressure, and the like. It should be understood that various work function adjusting layer deposition, patterning, and etching steps may be performed to create multiple threshold voltage devices.

Step 110 places a patterned masking structure 248 over a second device region 250b of the semiconductor device 201 of the substrate 200, as shown in fig. 6. The patterned mask structure 248 overfills the trenches 230 and covers the exposed surfaces of the second device region 250 b. The patterned mask structure protects the field effect transistors in the second device region 250b from damage during the etching/patterning process and exposes the first device region 250a of the semiconductor device 201 for subsequent processes, such as etching. In some embodiments, the patterned mask structure 248 may include a photoresist 254 patterned by a photolithography process, and may further include a bottom anti-reflective coating 252 filled in the trench 230 of the second device region 250 b.

Step 112 performs an etch process to remove the work function adjusting layer 244 not covered by the patterned masking structure 248 from the trench 230 of the field effect transistor in the first device region 250a, as shown in fig. 6. Once the work function adjusting layer 244 is removed, the barrier layer in the trench 230 of the field effect transistor in the first device region 250a is exposed. The etching process may be a wet etching process, which may dip or bubble the substrate 200 into an etching solution. In other or additional embodiments, the work function adjusting layer 244 in the first device region 250a may be removed using a dry process, such as a gas phase or plasma process. In some embodiments, a combination of wet and dry processes may be employed to remove the work function adjusting layer 244 from desired areas. In some examples, the method of removing the work function adjusting layer 244 from the trench 230 employs a wet process, such as dipping or immersing the substrate into an etching solution in a wet bath. In this case, the etching solution may be an alkaline, neutral, or acidic solution having a pH value within a predetermined range, depending on the kind of material of the work function adjusting layer 244 to be removed.

Although the work function adjusting layer 244 in the drawings is a single layer, the work function adjusting layer 244 may include multiple layers of different materials, as described above. It can thus be appreciated that the etch process 234 in some examples removes one or more of the multiple layers in the work-function adjusting layer 244 and retains one or more of the multiple layers in the work-function adjusting layer 244 after the etch process 234.

After step 114 removes the work function adjusting layer 244 from the trench 230 of the field effect transistor in the first device region 250a, the patterned masking structure 248 is removed from the second device region 250b, as shown in fig. 7. The method of removing patterned mask structure 248 may employ any suitable process, such as photoresist stripping or ashing.

Fig. 7 shows the semiconductor device 201 at an intermediate stage of processing, which exposes the barrier layer 247 in the trenches 230 of the field effect transistors in the first device region 250a, and the work function adjusting layer 244 in the trenches 230 of the field effect transistors in the second device region 250 b. In other examples of the foregoing, the work function adjusting layer 244 in the trench 230 of the field effect transistor in the first device region 250a and the work function adjusting layer 244 in the trench 230 of the field effect transistor in the second device region 250b are exposed, and the work function adjusting layers 244 in the first device region 250a and the second device region 250b may be different materials. Although the subsequent description in fig. 8-11 may refer to barrier layer 247 in trench 230 for field effect transistors in first device region 250a, and work function adjustment layer 244 in trench 230 for field effect transistors in second device region 250 b; it will be appreciated by those of ordinary skill in the art that these illustrations may implement different layers (e.g., different layers having different materials) of the work function adjusting layer 244 in different device regions (e.g., the first device region 250a and the second device region 250 b).

The surface of barrier layer 247 and/or the surface of work function adjusting layer 244 may be oxidized due to exposure to the external environment after deposition of the work function adjusting layer. For example, the semiconductor device may be transferred ex situ to another process chamber of the process system, such as an etch chamber, for processing, such as removing the work function adjusting layer. Oxidation of the barrier layer 247 and the work function adjusting layer 244, which may contain transition metals such as tantalum, titanium, or the like, tends to have a hydrogen-terminated surface upon exposure to an external environment such as the atmosphere. However, the barrier layer 247 and the work function adjusting layer 244 having a hydrogen-terminated surface have lower reactivity to a metal liner layer deposited by a subsequent atomic layer than a hydroxyl-terminated surface, thereby affecting the growth rate of the metal liner layer deposited by the subsequent atomic layer.

Various embodiments include an in-situ pretreatment or pre-deposition treatment process that includes immersing the barrier layer and/or the work function adjusting layer in a reactive agent to provide a treated surface for the barrier layer and/or the work function adjusting layer prior to depositing the metallic liner layer in an atomic layer deposition process. The treated surface has a monolayer of reactants formed thereon. The monolayer of oxide oxidizes when exposed to an external environment (e.g., the atmosphere) or an oxidizing agent, terminating the monolayer of reactants with hydroxyl groups, and the hydroxyl groups can react significantly with subsequent atomic layer deposition used to form the metallic liner layer. Through the pre-treatment process, the work function of the subsequently deposited metallic liner layer may be independent of the quality of the underlying surface (e.g., the underlying work function adjusting layer having the oxidized surface layer). In addition, the growth rate of the subsequently deposited metal liner layer is independent of variations in the substrate surface (e.g., the surface of the barrier layer or work function layer) that may affect the growth rate and thickness of the subsequently deposited metal liner layer. For subsequent atomic layer deposition of the metal liner layer, the pre-treated barrier layer and/or the work function adjusting layer may provide the same post-treatment initiation surface. Thus, the loading effect of the subsequent atomic layer deposition caused by the growth related to the substrate can be alleviated.

A pretreatment process 253 is performed at step 116 to immerse the respective layers exposed in the trenches 230 of the field effect transistors in the first device region 250a and the second device region 250b in a reactant. For the exposed layer, the pre-treatment process 253 provides treated surfaces 261 and 263 with a monolayer 251 of reactants formed thereon, as shown in FIG. 8. When the monolayer of reactants is later exposed to an environment, such as air or an oxidizing agent, the monolayer of reactants will be oxidized to form a hydroxyl terminated surface. The term "immersion" may refer to introducing the precursor into the chamber and closing the inlet and exhaust ports for a predetermined time (e.g., 2 seconds to 5 minutes) to allow the substrate surface to absorb or react with the precursor. The term "pre-treatment" may be in communication with the terms "surface treatment", "pre-deposition immersion", "immersion treatment", or "pre-immersion".

In various embodiments, the reactant comprises an aluminum-based precursor or a silicon-based precursor. Exemplary aluminum-based precursors can include, but are not limited to, trimethylaluminum, triethylaluminum, dimethylethylaminoalkane, dimethylaluminum hydride, tri-tert-butylaluminum, triisobutylaluminum, trimethylaminoalane, triethylaminoalane, any suitable aluminum-containing organometallic precursor, or a combination of any of the foregoing. Exemplary silicon-based precursors may include, but are not limited to, silanes or organosilanes. The silane may comprise silane, disilane, trisilane, tetrasilane, or a combination of any of the foregoing. The organosilane comprises a compound of formula R_ySi_xH_(2x+2-y)Wherein R is independently methyl, ethyl, propyl, or butyl. The organosilane can be methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, tris (dimethylamino) silane, or a combination of any of the foregoing. In some examples, the silicon-based precursor may be free of carbon.

The deposition thickness of the metallic liner layer (e.g., titanium nitride) deposited after 20 atomic layer deposition cycles, 40 atomic layer deposition cycles, or 90 atomic layer deposition cycles is substantially the same on both the silicon-based substrate and the aluminum-based substrate, and thus the aluminum-based precursor and the silicon-based precursor can be selected. Thus, providing or passivating the surfaces of the different layers of the FET with a single layer 251 of aluminum or silicon allows the formation of a liner layer of metal (e.g., TiN) deposited by subsequent atomic layer deposition at the same growth rate (and thus the same thickness).

The pre-treatment process 253 can employ a chemical vapor deposition process such as atomic layer deposition, plasma enhanced cyclic chemical vapor deposition, pulsed chemical vapor deposition, or any other suitable process such as an implantation process. In some embodiments, the pretreatment process employs an atomic layer deposition immersion treatment process. During an atomic layer deposition immersion process, the semiconductor device 201 is heated above the condensation temperature of the reactants (e.g., aluminum-based or silicon-based precursors) but below the thermal decomposition temperature of the reactants. The semiconductor device 201 is then exposed, immersed, or soaked in a reactant, causing the reactant to be absorbed and reacted with the surface of the layer exposed in the trenches 230 of the field effect transistors in the first device region 250a and in the trenches 230 of the field effect transistors in the second device region 250 b. The reactants form a monolayer 251 on the treated surfaces 261 and 263. The semiconductor device 201 is then exposed to the atmosphere or an oxidizing agent to spontaneously form a native oxide (e.g., aluminum oxide or silicon oxide) on the single layer of reactant. Insets 270 and 272 in fig. 8A and 8B are partial enlarged views of the monolayer 251 with the reactant of the hydroxyl termination 265, respectively, and the monolayer 251 is formed on the barrier layer 247 and the work function adjusting layer 244. In the examples shown in fig. 8A and 8B, R refers to a species containing aluminum or silicon.

In some examples, a monolayer of aluminum oxide is formed in an atomic layer deposition immersion process on the barrier layer 247 of the field effect transistors in the first device region 250a and on the work function adjusting layer 244 of the field effect transistors in the second device region 250 b. The ald dip process initially sets the temperature of the semiconductor device 201 in the process chamber to between about 20 ℃ and about 130 ℃, such as between about 60 ℃ and about 100 ℃. An aluminum-based precursor (such as trimethyl aluminum or triethyl aluminum described above) may be introduced into the process chamber such that the semiconductor device 201 is immersed or bubbled into the aluminum-based precursor. The flow rate of trimethylaluminum or triethylaluminum into the process chamber may be from about 50sccm to aboutBetween 8000sccm, such as between about 300sccm and about 5000sccm, for example between about 500sccm and about 2000 sccm. The time for which the semiconductor device 201 is immersed or bubbled into the trimethylaluminum or triethylaluminum may be between about 1 second and about 300 seconds to form a monolayer of aluminum on the surfaces of the barrier layer 247 and the work function adjusting layer 244. The time of immersion can be adjusted to obtain the desired amount of alumina on and/or in the exposed layer. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a time period ranging from about 10 seconds to about 60 seconds. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a time period ranging from about 5 seconds to about 20 seconds. In some examples, the semiconductor device 201 is immersed in trimethylaluminum or triethylaluminum for a time between about 30 seconds and about 120 seconds. In some embodiments, the semiconductor device 201 is immersed in triethylaluminum at a flow rate of 600sccm for a period of time between about 30 seconds and about 80 seconds. The monolayer thickness of aluminum may be between aboutTo aboutBetween, such as aboutTo aboutBetween, e.g. aboutTo aboutIn the meantime. After absorbing trimethylaluminum or triethylaluminum on the surface of the barrier layer 247 or on the surface of the work function adjusting layer 244, the atomic layer deposition control system interrupts the flow of trimethylaluminum or triethylaluminum to the process chamber. The semiconductor device 201 is then transferred to another process chamber for deposition of subsequent metal layers. As the semiconductor device 201 exits the process chamberThe vacuum is broken and an oxidizing agent is introduced into the aluminum monolayer, causing the aluminum monolayer to convert to an aluminum oxide monolayer.

In one example, a single layer of silicon oxide is formed on the barrier layer 247 of the field effect transistors in the first device region 250a and on the work function adjustment layer 244 of the field effect transistors in the second device region 250b, which may be formed using an atomic layer deposition immersion process. The ald dip process may initially set a temperature of the semiconductor device 201 in the process chamber between about 20 ℃ and about 130 ℃, such as between about 60 ℃ and about 100 ℃. A silicon-containing precursor, such as the aforementioned silane or disilane, may be introduced into the process chamber such that the semiconductor device 201 is immersed or bubbled into the silicon-containing precursor. The silane or disilane may be flowed into the process chamber at a flow rate of about 50sccm to about 8000sccm, such as about 300sccm to about 5000sccm, or such as about 500sccm to about 2000 sccm. The semiconductor device 201 may be dipped or bubbled into the silane or disilane for between about 1 second and about 300 seconds to form a single layer of silicon on the surfaces of the barrier layer 247 and the work function adjusting layer 244. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 10 seconds and about 60 seconds. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 5 seconds and about 20 seconds. In some examples, the semiconductor device 201 is immersed in silane or disilane for between about 30 seconds and about 120 seconds. In one embodiment, the semiconductor device is immersed in the silane for between about 15 seconds and about 120 seconds. In another embodiment, the semiconductor device 201 is immersed in disilane for between about 15 seconds and about 60 seconds. The silicon thickness of a single layer may be between aboutTo aboutBetween, such as aboutTo aboutOr, for example, between aboutTo aboutIn the meantime. After absorbing silane or disilane on the surface of the barrier layer 247 and on the surface of the work function adjusting layer 244, the atomic layer deposition control system interrupts the flow of silane or disilane to the process chamber. The semiconductor device 201 is then transferred to another process chamber for deposition of subsequent metal layers. The semiconductor device 201 may break a vacuum upon exiting the process chamber and may direct an oxidizing agent toward the monolayer of silicon, causing the monolayer of silicon to convert to a monolayer of silicon oxide.

In other or additional embodiments, the atomic layer deposition process may employ two or more reactants to produce alumina or silica. In this example, the semiconductor device 201 is then alternately exposed to pulses of two or more reactants to perform a pretreatment process, with the pulses separated by a step of evacuating and/or purging the process chamber.

In some examples, the semiconductor device 201 is exposed to a second reactant (e.g., water in a vapor phase or other oxidizing agent) after a monolayer of a first reactant (e.g., an aluminum-based precursor or a silicon-based precursor) is absorbed on exposed surfaces of the respective layers in trenches of the field effect transistors in the first device region 250a and the second device region 250 b. Upon exposure to the second reactant, available molecules of the first reactant absorb and react with the second reactant to form a monolayer-scale alumina or silica. The process may be repeated to form a monolayer on the surface layer again and again until the desired thickness is achieved.

In some examples, a monolayer of aluminum oxide is formed in an atomic layer deposition process on the barrier layer 247 of the field effect transistors in the first device region 250a and on the work function adjusting layer 244 of the field effect transistors in the second device region 250 b. The ald process initially sets a temperature of the semiconductor device 201 in the process chamber between about 20 ℃ and about 500 ℃, such as between about 250 ℃ and about 500 ℃. Pulse input is firstReactants such as trimethyl aluminum or triethyl aluminum described above are introduced into the process chamber to immerse or bubble the semiconductor device 201 in the trimethyl aluminum or triethyl aluminum. The flow rate of trimethylaluminum or triethylaluminum into the process chamber is between about 10sccm to about 6000sccm, such as between about 100sccm to about 3000sccm, for example between about 100sccm to about 3000 sccm. The immersion time for forming the aluminum layer on the surfaces of the barrier layer 247 and the work function adjusting layer 244 may be between about 1 second and about 300 seconds. For example, the immersion time may be between about 1 second to about 180 seconds. In some examples, the immersion time may be between about 5 seconds to about 120 seconds. In some examples, the immersion time may be between about 30 seconds to about 60 seconds. After pulsing the first reactant, a vacuum is drawn and/or a purge gas, such as an inert gas, is delivered. The inert gas can be any suitable inert gas such as argon, helium, neon, or a combination of any of the above. The inert gas may be flowed into the process chamber at a flow rate of about 100sccm to about 10000sccm, such as about 1000sccm to about 6000 sccm. The evacuation and/or purge gas may remove any residual trimethylaluminum, triethylaluminum, or byproducts from the process chamber. After evacuation and/or purging, a second reactant, such as water, ozone, hydrogen peroxide, or any suitable oxidizing agent, is pulsed into the process chamber. One or more second reactant molecules may be bonded to the aluminum layer to form a monolayer-scale aluminum oxide layer. The flow rate of the second reactant into the process chamber may be between about 10sccm to about 8000sccm, such as between about 300sccm to about 5000sccm, or such as between about 500sccm to about 2000 sccm. A vacuum and/or purge may be performed again to remove byproducts from the process chamber. These steps may be repeated, e.g., in a continuous cycle, until the alumina on the surfaces of barrier layer 247 and work function adjusting layer 244 has accumulated to a desired thickness. For example, the thickness of the alumina may be between aboutTo aboutBetween, such as aboutTo aboutDepending on the atomic layer deposition cycle.

In some examples, a single layer of silicon oxide is formed in an atomic layer deposition process on the barrier layer 247 of the field effect transistors in the first device region 250a and on the work function adjusting layer 244 of the field effect transistors in the second device region 250 b. The ald process initially sets a temperature of the semiconductor device 201 in the process chamber between about 20 ℃ and about 500 ℃, such as between about 200 ℃ and about 500 ℃. A first reactant, such as silane or disilane, as described above, is pulsed into the process chamber to immerse or bubble the semiconductor device 201 in the silane or disilane. The flow rate of silane or disilane into the process chamber is between about 10sccm to about 3000sccm, such as between about 300sccm to about 1000 sccm. The pulse time for forming the silicon layer on the surfaces of the barrier layer 247 and the work function adjusting layer 244 may be between about 1 second and about 300 seconds. For example, the pulse time may be between about 10 seconds to about 60 seconds. In some examples, the pulse time may be between about 5 seconds to about 90 seconds. In some examples, the pulse time may be between about 30 seconds to about 120 seconds. After pulsing the first reactant, a vacuum is applied and/or a purge gas, such as an inert gas, is delivered. The inert gas can be any suitable inert gas such as argon, helium, neon, or a combination of any of the above. The inert gas may be flowed into the process chamber at a flow rate of about 100sccm to about 6000sccm, such as about 1000sccm to about 3000 sccm. The evacuation and/or purge gas may remove any residual silane, disilane, or byproducts from the process chamber. After evacuation and/or purging, a second reactant, such as water, ozone, hydrogen peroxide, or any suitable oxidizing agent, is pulsed into the process chamber. One or more second reactant molecules may be bonded to the silicon layer to form a monolayer-scale silicon oxide layer. The pulse time of the second reactant may be between about 1 second and about 300 seconds. For example, pulsesThe attack time may be between about 10 seconds to about 60 seconds. In some examples, the pulse time may be between about 5 seconds to about 90 seconds. In some examples, the pulse time may be between about 30 seconds to about 120 seconds. The flow rate of the second reactant into the process chamber may be between about 10sccm to about 8000sccm, such as between about 300sccm to about 5000sccm, or such as between about 500sccm to about 2000 sccm. A vacuum and/or purge may be performed again to remove residual second reactant and byproducts from the process chamber. These steps may be repeated, e.g., in a continuous cycle, until the silicon oxide on the surfaces of barrier layer 247 and work function adjusting layer 244 has accumulated to a desired thickness. For example, the thickness of the silicon oxide may be between aboutTo aboutBetween, such as aboutTo aboutDepending on the atomic layer deposition cycle.

In this example, after the pretreatment process 253, the field effect transistors are covered or passivated with a single layer of aluminum oxide or silicon oxide that is exposed to the layers (e.g., the barrier layer 247 and the work function adjusting layer 244) of the pretreatment process 253. The single layer of alumina or silica is thin (e.g., less than) Therefore, the impact on the gap-filling performance and/or threshold voltage of other layers in the trench 230 can be minimized. When the semiconductor device 201 leaves the process chamber for subsequent atomic layer deposition of a metal layer, the monolayer of aluminum oxide or silicon oxide is exposed to air, which may further terminate the primary dangling bonds with hydroxyl groups that may significantly react to form a metallic liner layer in the subsequent atomic layer deposition. Thus the formation of a subsequently deposited metal liner layerThe long rate may be independent of variations in the substrate surface (e.g., barrier layer 247 or work function adjusting layer 244). Conversely, the pre-treated barrier layer and the work function adjusting layer may provide the same surface for subsequent atomic layer deposition for the metallic liner layer. Thus, the loading effect of the subsequent atomic layer deposition caused by the growth related to the substrate can be alleviated.

Step 118, after processing the surfaces of the exposed layer (e.g., the barrier layer in the trench 230 for the field effect transistor in the first device region 250a and the work function adjusting layer 244 in the trench 230 for the field effect transistor in the second device region 250b), conformably deposits a metal liner layer 255 in the trench 230 (e.g., on the processed surface 261 of the barrier layer 247 and the processed surface 263 of the work function adjusting layer 244), as shown in fig. 9. For example, the metal liner layer 255 may be made of a similar material as the cap layer 245. For example, the metallic liner layer 255 may be or include tantalum and/or titanium nitrides, silicon nitrides, carbon nitrides, and/or aluminum nitrides; tungsten nitrides, carbonitrides, and/or carbides; (ii) an analog; or a combination of the foregoing. In some examples, the metal liner layer 255 is titanium nitride. In some examples, the metal liner layer 255 is tantalum nitride. In some examples, the metal liner layer 255 is titanium oxynitride. In some examples, the metal liner layer 255 is tantalum oxynitride. Although the metal liner layer 255 is shown as a single layer, it is contemplated that the metal liner layer 255 may include one or more of the other layers described herein. The metal liner 255 and any other layers deposited on the processed surfaces 261 and 263 may also be used to set the work function value of the gate metal 257. In some examples, the deposition method of the metallic liner layer 255 is atomic layer deposition. In other examples, the metal liner layer 255 may be deposited by plasma enhanced chemical vapor deposition, molecular beam deposition, or any other deposition technique.

In some embodiments, in forming the metallic liner layer 255, the oxygen in the monolayer 251 may react with a precursor used to form the metallic liner layer 255 to form a mixed layer between the metallic liner layer 255 and the monolayer 251 (e.g., aluminum oxide or silicon oxide). In one embodiment, in the illustrations 297 and 299 of fig. 9, hybrid layers 293 and 295 are formed over the monolayer 251 in the first device region 250a and the second device region 250b, respectively, in an enlarged view. For example, the mixed layer may be a titanium aluminum oxide compound, depending on the materials of the metal liner layer 255 and the single layer. In addition, since the metallic liner layer 255 is purged of oxygen when formed, the oxygen level in the monolayer may be lower than the oxygen level before the metallic liner layer 255 is formed.

Due to the pretreatment process 253, the growth rate of the metallic liner layer 255 formed by atomic layer deposition on the barrier layer 247 and the work function adjusting layer 244 is almost the same because the field effect transistors in the first device region 250a and the field effect transistors in the second device region 250b have the same starting surfaces (e.g., the treated surfaces 261 and 263 with a single layer of aluminum oxide or silicon oxide). As a result, the metal liner layer 255 may have a uniform thickness over the barrier layer 247 and the work function adjusting layer 244. In addition, since the monolayer of aluminum oxide or silicon oxide has a hydroxyl termination 265, which facilitates reaction with one or more precursors of the atomic layer deposition used to form the metallic liner layer 255, the growth time of the metallic liner layer 255 on the barrier layer 247 and the work function adjusting layer 244 during atomic layer deposition can be improved. For example, immersion of a barrier layer, such as tantalum nitride, in triethylaluminum (at a flow rate of 600sccm) for 15 seconds may increase the thickness of a liner metal layer, such as titanium nitride, by about 46% as compared to non-immersion of the barrier layer in triethylaluminum. Immersion of the barrier layer, e.g., TaN, in triethylaluminum (at a flow rate of 600sccm) for 10 seconds may increase the thickness of the liner metal layer, e.g., TiN, by about 40% as compared to non-immersion of the barrier layer in triethylaluminum. Immersion of the barrier layer, e.g., TaN, in triethylaluminum (at a flow rate of 600sccm) for 5 seconds increased the thickness of the liner metal layer, e.g., TiN, by about 32% compared to the barrier layer not immersed in triethylaluminum. A similar growth pattern may be found on the work function adjusting layer. These phenomena show that the use of an aluminum-based pre-soak process can enhance the growth of metal liner on the treated surfaces 261 and 263 during the ald process. Thus, some embodiments locate the metallic liner layer 255 on a single layer of aluminum oxide or silicon oxide after depositing the metallic liner layer 255.

Step 120 is to form a metal liner layer 255 on the processed surfaces 261 and 263, and then to form a gate metal 257 on the metal liner layer 255 and fill the trench 230 defined in the ild layer 218 to replace the gate structures 212a and 212 b. The gate metal 257 may extend beyond the trench 230 to a predetermined thickness, as shown in fig. 10. In various embodiments, the gate metal 257 may be or comprise a conductive material such as aluminum, copper, titanium, tantalum, aluminum titanium, titanium aluminum nitride, titanium nitride, tantalum nitride, aluminum tantalum, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tungsten nitride, molybdenum nitride, platinum, ruthenium, other suitable conductive materials, or combinations thereof. In some examples, the gate metal 257 is tungsten. The gate metal 257 may be formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, electroplating, atomic layer deposition, and/or other suitable processes.

A planarization process (e.g., chemical mechanical planarization) may be performed to planarize the top surface of the semiconductor device 201 in step 122. The planarization process may remove the gate metal 257, the metal liner 255, the monolayer 251, the barrier layer 247, the cap layer 245, the work function adjusting layer 244, and the gate dielectric layer 242 above the top surface of the ild 218, as shown in fig. 11. Once the planarization process is completed, the upper surface 259 of the ild layer 218 is exposed.

Subsequent processing may be performed on the semiconductor device 201 fabricated according to the flowchart 100 to form various structures and regions. For example, subsequent processes may form multiple layers (e.g., metal layers or intermetal dielectric layers) of various contact/via/line and interconnect structures on the substrate 200 including the semiconductor device 201, which are configured to connect various structures to form functional circuitry (which may include one or more devices such as one or more semiconductor devices 201). Various interconnect structures may employ various conductive materials such as copper, tungsten, and/or silicide. In one example, a damascene process and/or a dual damascene process may be used to form a copper-related multilevel interconnect structure. In addition, additional process steps may be performed before, during, or after flowchart 100, and some of the above steps may be replaced or omitted depending on the application.

Various embodiments described above may provide the same starting surface for subsequent atomic layer deposition by pre-treating the exposed surfaces of the barrier layer and/or the work function adjusting layer, thereby mitigating substrate-related loading. The work function layer's growth characteristics relative to the substrate can be used to tune the threshold voltage of an n-type or p-type field effect transistor device to multiple threshold voltages. In some multi-threshold metal gates, the semiconductor device may include two or more device regions, and each device region may include a p-type device or an n-type device. Fig. 12 shows a simplified semiconductor device 1200 in an intermediate stage of processing, and portions of the gate structure in three device regions 1202, 1204, and 1206. Each device region includes n-type devices. Each n-type device in device regions 1202, 1204, and 1206 has a work function adjusting layer 1208 on the gate dielectric layer 1210. A metal layer 1212, such as a work function adjusting layer (e.g., titanium nitride, tantalum nitride, titanium aluminum nitride, or titanium silicon nitride) for p-type devices, is typically formed between the work function adjusting layer 1208 and the gate dielectric layer 1210 and has a different thickness to affect the work function of the metal gate. In the example shown in fig. 12, the metal layer 1212 in the device region 1202 has a first thickness T1; metal layer 1212 in device region 1204 has a second thickness T2, and second thickness T2 is greater than first thickness T1; and metal layer 1212 in device region 1206 has a third thickness T3, and third thickness T3 is greater than second thickness T2. Since the work function of a metal gate depends in part on the conductivity of metal layer 1212, providing the same metal layer 1212 with different thicknesses may effectively vary and separate the work functions of different metal gates in device regions 1202, 1204, and 1206. However, as the dimensions of finfet devices are reduced, it may not be practical to adjust the multiple threshold voltages with different thicknesses, since the space for the metal layer may be reduced or limited.

Various embodiments described herein adjust the multiple threshold voltages used for n-type or p-type devices without forming a multilayer film stack between the work function adjusting layer and the gate dielectric layer. Conversely, by providing different metal layers between the work function adjusting layer and the gate dielectric layer for n-type or p-type devices, the metal gate work function of different device regions may be adjusted. Because the growth behavior of some work function materials has strong correlation with the substrate, the composition and thickness of the work function adjusting layer in different device regions can be changed due to different metal layers below the work function adjusting layer. Fig. 13 illustrates a simplified semiconductor device 1300 at an intermediate stage of processing in some embodiments. The semiconductor device 1300 may be a multi-threshold voltage integrated circuit device, such as the semiconductor device 201 described above. For clarity of illustration, only a portion of the gate structure shown in the inset 1360, 1362, and 1364 will be discussed. Other elements of the semiconductor device 1300, such as the source/drain regions 213a, 213b, and 213c, the gate spacers 220, the isolation region 216, the fin 202, and the interlayer dielectric 218, may be referred to in conjunction with the semiconductor device 201 described above with reference to fig. 5.

In one embodiment, the semiconductor device 1300 has three device regions 1302, 1304, and 1306, and each device region includes an n-type device. Similar to the semiconductor device 201 described above, the n-type devices in the device regions 1302, 1304, and 1306 may be n-type low threshold voltage devices, n-type standard threshold voltage devices, or n-type high threshold voltage devices, depending on the application. Although the devices described herein are n-type devices, it should be understood that the concepts may also be applied to p-type devices such as p-type fin field effect transistor devices. Each n-type device in the device regions 1302, 1304, and 1306 has a work function adjusting layer 1308 over the gate dielectric layer 1310. Similar to the work function adjusting layer 244 described above, suitable examples of the work function adjusting layer 1308 can include titanium, aluminum, tantalum aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, or other suitable materials having a work function between 3.9eV and 4.3 eV. In one embodiment, the work function adjusting layer 1308 is titanium aluminum carbide. Similar to gate dielectric layer 242, gate dielectric layer 1310 may comprise or may be silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other suitable dielectric materials. In some embodiments, the gate dielectric layer 1310 may be a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, or lead, multiple layers thereof, or combinations thereof.

Between the gate dielectric layer 1310 and the work function adjusting layer 1308 in the respective device regions 1302, 1304, and 1306, a first metal layer 1312, a second metal layer, a third metal layer, and a fourth metal layer are provided,The second metal layer 1314 and the third metal layer 1316 are used to adjust the work function value of the metal gate. The first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 may be titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, a composite containing a metal nitride (e.g., titanium nitride-silicon nitride), or any suitable metal such as those described above for the cap layer 245 and the barrier layer 247. In one embodiment, the thickness T4 of the first metal layer 1312, the thickness T5 of the second metal layer 1314, and the thickness T6 of the third metal layer 1316 are substantially the same, such as aboutIn some examples, thickness T4, thickness T5, and thickness T6 may each be between aboutTo aboutBetween, such as aboutTo aboutIn the meantime. Unlike the semiconductor device 1200 of fig. 12, in which the same metal layer 1212 is formed with different thicknesses for adjusting the multi-threshold voltage of the n-type field effect transistor, the first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 may have different chemical structures from each other. In one embodiment, the first metal layer 1312 in the device region 1302 is titanium nitride, the second metal layer 1314 in the device region 1304 is tantalum nitride, and the third metal layer 1316 in the device region 1306 is titanium nitride-silicon nitride. Since the growth behavior of the work function adjusting layer 1308, such as titanium aluminum carbide, is strongly substrate dependent (i.e., the composition and thickness of the titanium aluminum carbide is substrate dependent), the use of different metal layers in the respective device regions 1302, 1304, and 1306 results in the titanium aluminum carbide layer having different film thicknesses and characteristics, thereby changing the work function value of the work function adjusting layer 1308. In some embodiments, carbon on titanium nitride-silicon nitrideThe difference between the thickness of titanium aluminum carbide on tantalum nitride and the thickness of titanium aluminum carbide on tantalum nitride may be between about 12% to about 15%, while the difference between the thickness of titanium aluminum carbide on titanium nitride and the thickness of titanium aluminum carbide on tantalum nitride may be between about 28% to about 39%.

FIGS. 14A-14C show X-ray photoelectron spectra of the major components of titanium aluminum carbide deposited on titanium nitride-silicon nitride, tantalum nitride, and titanium nitride substrates. In the figure, the measured photoelectron intensity is plotted in arbitrary units (A.U.) as a function of the binding energy. The X-ray photoelectron spectroscopy uses X-rays to dislodge nuclear electrons present on the surface of titanium aluminum carbide. The kinetic energy of the electrons is measured to obtain the electron binding energy of the atoms of interest (e.g., aluminum, carbon, and silicon). The titanium aluminum carbide is deposited on the titanium nitride-silicon nitride, tantalum nitride, and titanium nitride substrate at a temperature between about 350 c and about 420 c and at a pressure between about 1Torr and about 20 Torr. For the aluminum spectrum (Al,2p) in fig. 14A, it measures the peak of electrons emitted from the shell 2p of aluminum atoms. Titanium aluminum carbide deposited on titanium nitride showed the highest aluminum spectral signal (background spectrum subtracted from measured spectrum of about 4.7 by about 1.8), while titanium aluminum carbide deposited on tantalum nitride and titanium aluminum carbide deposited on titanium nitride-silicon nitride showed lower aluminum spectral signals, indicating that titanium aluminum carbide measured more aluminum when deposited on titanium nitride substrates. Thus, titanium aluminum carbide on a titanium nitride substrate may have more positive charge carriers than titanium aluminum carbide on tantalum nitride or titanium nitride-silicon nitride because of the higher aluminum concentration in its titanium aluminum carbide.

For the carbon spectrum (C,1s) in fig. 14B, it measures the peak of electrons emitted from the shell 1s of the carbon atom. Titanium aluminum carbide deposited on titanium nitride showed the highest carbon spectral signal (background spectrum subtracted from measured spectrum of about 7.3 by about 4), while titanium aluminum carbide deposited on tantalum nitride and titanium aluminum carbide deposited on titanium nitride-silicon nitride showed lower carbon spectral signals, indicating that titanium aluminum carbide measured more carbon as deposited on titanium nitride.

For the silicon spectrum (Si,2p) in fig. 14C, it measures the peak of electrons emitted from the shell 2p of the silicon atom. Titanium aluminum carbide deposited on tantalum nitride shows the highest silicon spectral signal (background spectrum subtracted from measured spectrum of about 4.5 by about 2.7), while titanium aluminum carbide deposited on titanium nitride shows the lowest silicon spectral signal, indicating that titanium aluminum carbide measured more silicon when deposited on tantalum nitride. The higher silicon strength in titanium aluminum carbide indicates that titanium aluminum carbide on tantalum nitride is thinner than titanium aluminum carbide on titanium nitride because the silicon signal of the underlying fin (e.g., fin 202) is easier to detect.

The X-ray photoelectron spectra of fig. 14A-14C indicate that providing different substrates results in titanium aluminum carbide with different film thicknesses and properties. Thus, by using different metal layers in the respective device regions 1302, 1304, and 1306, titanium aluminum carbide with different film thicknesses and characteristics can be formed. Different titanium carbide aluminum films on different substrates can provide different n-type work functions for adjusting the multi-threshold voltage without stacking multiple layers of metal. This provides more space for filling a metal gate or other suitable work function adjusting layer for the device.

The processes for forming the different metal layers in the respective device regions 1302, 1304, and 1306 are as follows. After forming a gate dielectric layer 1310 in the trenches 1301, 1303, and 1305 between the gate spacers in the device regions 1302, 1304, and 1306, a first metal layer 1312, such as titanium nitride, is formed on the gate dielectric layer 1310 in the trenches 1301, 1303, and 1305 in the device regions 1302, 1304, and 1306. A patterned mask (e.g., patterned mask structure 248 as described above) may then be located over the device region 1302 of the semiconductor device 1300. The patterned mask overfills the trenches and covers the exposed surfaces of device region 1302, exposing device regions 1304 and 1306 for subsequent processing such as etching. One or more etching processes may then be performed to selectively remove the first metal layer 1312 from the trenches in the device regions 1304 and 1306, leaving the first metal layer 1312 in the trenches in the device region 1302.

A second metal layer 1314 such as tantalum nitride is then formed in the trenches in the device regions 1302, 1304, and 1306. Similarly, a patterned mask is deposited over the device region 1304 of the semiconductor device 1300. One or more etching processes may then be performed to selectively remove second metal layer 1314 from the trenches in device regions 1302 and 1306, leaving second metal layer 1314 in the trenches in device region 1304. A third metal layer 1316, such as tin-nitride, is then formed in the trenches of device regions 1302, 1304, and 1306. A patterned mask is deposited over the device region 1306 of the semiconductor device 1300. One or more etching processes may then be performed to selectively remove the third metal layer 1316 from the trenches in the device regions 1302 and 1304 and leave the third metal layer 1316 in the trenches in the device region 1306. In this manner, a first metal layer 1312 (e.g., titanium nitride) may be formed in the device region 1302 between the gate dielectric layer 1310 and the work function adjusting layer 1308, a second metal layer 1314 (e.g., tantalum nitride) may be formed in the device region 1304 between the gate dielectric layer 1310 and the work function adjusting layer 1308, and a third metal layer 1316 (e.g., titanium nitride-silicon nitride) may be formed in the device region 1306 between the gate dielectric layer 1310 and the work function adjusting layer 1308. The above method may change the composition and thickness of the work function adjusting layer 1308 (e.g., titanium aluminum carbide) to adjust the multi-threshold voltage as desired.

After forming the work function adjusting layer 1308 on the first metal layer 1312, the second metal layer 1314, and the third metal layer 1316 in the respective device regions 1302, 1304, and 1306, processes are performed on the semiconductor device 1300 to form a metal liner layer and a gate metal, as described above in conjunction with figures 9-11. Subsequent processing may be performed on the semiconductor device 1300 to form multiple layers of structures or regions, such as contacts/vias/lines and interconnect structures, as required for a functionally integrated device.

Various embodiments described herein may provide various advantages. It is to be understood that not necessarily all advantages may be described herein, that no particular advantage may be required in any embodiment, and that other embodiments may provide different advantages. For example, embodiments described herein include methods and structures associated with a pre-deposition process, including dipping a particular layer (e.g., a work function adjusting layer, a barrier layer, a capping layer, other suitable metal layer, or the like) that has been deposited in a trench of a field effect transistor (e.g., for a standard threshold voltage device) or a trench of another field effect transistor (e.g., for an ultra-low threshold voltage device) into a reactant to provide a treated surface, followed by depositing a subsequent metallic liner layer on the treated surface of the particular layer. In various embodiments, the pre-deposition treatment process forms a monolayer of reactants on the treated surface. The single layer of reactants may be exposed to an external environment or any suitable oxidizing agent for oxidation, among other advantages, including providing different metal layers between the work function modifying layer and the gate dielectric layer to adjust the multiple threshold voltages for n-type or p-type devices, which may be used in different device regions of field effect transistors such as n-type field effect transistors or p-type field effect transistors. Different metal layers may affect the composition and thickness of the work function adjusting layer to change the work function of the work function adjusting layer deposited thereon. The distinction of work function adjusting layers (e.g., titanium aluminum carbide) on different substrates can provide different n-type work functions for the purpose of multi-threshold voltage adjustment without the need to stack multiple metal layers. As such, more space may be provided to fill in a metal gate or other suitable work function adjusting layer for the device.

In one embodiment, a method for semiconductor processing is provided. The method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form a plurality of monolayers on the first metal-containing layer and the second metal-containing layer, respectively, the first device and the second device being on a substrate, the first device including a first gate structure, the first gate structure including the first metal-containing layer, the second device including a second gate structure, the second gate structure including the second metal-containing layer, the first metal-containing layer being different from the second metal-containing layer. The method also includes exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidizing agent to provide a hydroxyl terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and forming a third metal-containing layer on the hydroxyl-terminated surface of the monolayer over the first metal-containing layer and the second metal-containing layer.

In some embodiments, the reactant comprises an aluminum-based precursor, and the aluminum-based precursor comprises trimethylaluminum, triethylaluminum, dimethylethylaminoalkane, dimethylaluminum hydride, tri-tert-butylaluminum, triisobutylaluminum, trimethylaminylalkane, triethylaminylalkane, an aluminum-containing organometallic precursor, or a combination thereof.

In some embodiments, the monolayer on the first metal-containing layer and the second metal-containing layer is aluminum oxide.

In some embodiments, the first device and the second device are different types of devices including n-type ultra low threshold voltage devices, n-type standard voltage devices, n-type high threshold voltage devices, p-type ultra low threshold voltage devices, p-type standard threshold voltage devices, or p-type high threshold voltage devices.

In some embodiments, the first metal-containing layer is tantalum nitride and the third metal-containing layer is titanium nitride.

In some embodiments, the second metal-containing layer comprises titanium aluminum carbide or titanium aluminum oxide.

In some embodiments, the reactant comprises a silicon-containing precursor, and the silicon-containing precursor comprises silane, disilane, trisilane, tetrasilane, or combinations thereof.

In some embodiments, the monolayer on the first metal-containing layer and the second metal-containing layer is silicon oxide.

In some embodiments, the monolayer on the first metal-containing layer and the second metal-containing layer is formed by an atomic layer deposition process, and the third metal-containing layer is formed by an atomic layer deposition process.

Another embodiment is a semiconductor device. The semiconductor device includes a substrate; and a first device having a first gate structure on the substrate. The first gate structure comprises a gate dielectric layer positioned on the substrate; a barrier layer on the gate dielectric layer; a single layer of alumina or silica on the barrier layer; a metal liner layer on the single layer of alumina or silica on the barrier layer; and a gate metal on the metal liner layer.

In some embodiments, the semiconductor device further includes a second device having a second gate structure on the substrate. The second gate structure includes: a gate dielectric layer on the substrate; a barrier layer on the gate dielectric layer; a work function adjusting layer on the barrier layer; a single layer of alumina or silica on the work function adjusting layer; a metal pad layer on the single layer of alumina or silica on the work function adjusting layer; and a gate metal on the metal liner layer.

In some embodiments, the work function adjusting layer and the barrier layer are different materials.

In some embodiments, the first device and the second device are different types of devices including n-type ultra low threshold voltage devices, n-type standard voltage devices, n-type high threshold voltage devices, p-type ultra low threshold voltage devices, p-type standard threshold voltage devices, or p-type high threshold voltage devices.

Yet another embodiment provides a method. The method includes forming a gate dielectric layer in a first trench and a second trench, each of the first trench and the second trench defined in a dielectric structure and intersecting a fin on a substrate; forming a first metal layer on the gate dielectric layer in the first trench; forming a second metal layer on the gate dielectric layer in the second trench, wherein the first metal layer and the second metal layer have different chemical compositions; forming a work function adjusting layer directly on the first metal layer in the first groove and the second metal layer in the second groove, wherein the thickness of the work function adjusting layer on the first metal layer is different from that of the work function adjusting layer on the second metal layer; and forming a gate on the work function adjusting layer in the first trench and the second trench.

In some embodiments, the method further includes forming a gate dielectric layer in the third trench, and the third trench is defined in the gate structure and intersects the fin on the substrate; forming a third metal layer on the gate dielectric layer in the third trench, wherein the third metal layer, the first metal layer and the second metal layer have different chemical compositions; forming a work function adjusting layer directly on the third metal layer in the third groove, wherein the thickness of the work function adjusting layer on the third metal layer is different from that of the work function adjusting layer on the second metal layer; and forming a gate on the work function adjusting layer in the third trench.

In some embodiments, the work function adjusting layer comprises tantalum aluminum, tantalum aluminum carbide, titanium aluminum oxide, hafnium aluminum, titanium aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof.

In some embodiments, the work function adjusting layer is titanium aluminum carbide.

In some embodiments, the first metal layer, the second metal layer, and the third metal layer each comprise titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, or titanium nitride-silicon nitride.

In some embodiments, the first metal layer is titanium nitride, the second metal layer is tantalum nitride, and the third metal layer is titanium nitride-silicon nitride.

In some embodiments, the first metal layer, the second metal layer, and the third metal layer have substantially the same thickness.

The features of the above-described embodiments are helpful to one of ordinary skill in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that such equivalent substitutions may be made without departing from the spirit and scope of the present invention, and that changes, substitutions, or alterations may be made without departing from the spirit and scope of the present invention.