阅读说明：本技术 半导体器件和方法 (Semiconductor device and method ) 是由 廖志腾 戴嘉成 翁子展 邱意为 郑志玄 于 2018-11-26 设计创作，主要内容包括：方法包括形成在衬底之上延伸第一高度的半导体鳍,在半导体鳍上方和衬底上方形成伪介电材料,在伪介电材料上方形成伪栅极材料,伪栅极材料在衬底之上延伸第二高度,使用多个蚀刻工艺蚀刻伪栅极材料以形成伪栅极堆叠件,其中,多个蚀刻工艺的每个蚀刻工艺均是不同的蚀刻工艺,其中,伪栅极堆叠件在第一高度处具有第一宽度,并且其中,伪栅极堆叠件在第二高度处具有与第一宽度不同的第二宽度。本发明的实施例还涉及半导体器件和方法。(The method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material above the semiconductor fin and above the substrate, forming a dummy gate material above the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using a plurality of etching processes to form a dummy gate stack, wherein each etching process of the plurality of etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width. Embodiments of the invention also relate to semiconductor devices and methods.)

1. A method of forming a semiconductor device, comprising:

Forming a semiconductor fin extending a first height above a substrate;

Forming a dummy dielectric material over the semiconductor fin and over the substrate;

Forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate; and

Etching the dummy gate material using a plurality of etch processes to form a dummy gate stack, wherein each etch process of the plurality of etch processes is a different etch process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

2. the method of claim 1, wherein the second width is between 2% and 10% greater than the first width.

3. The method of claim 1, wherein one etch process of the plurality of etch processes comprises a pulsed plasma power and another etch process of the plurality of etch processes comprises a constant plasma power.

4. The method of claim 1, wherein a passivation gas is used during one of the plurality of etching processes and is not used during another of the plurality of etching processes.

5. The method of claim 4, wherein the passivation gas is HBr and O₂A mixture of (a).

6. The method of claim 1, wherein the dummy gate stack has a third width at a third height that is lower than the first height, and wherein the third width is different than the first width.

7. The method of claim 1, further comprising:

Removing the dummy gate stack to form an opening; and

Filling the opening with a replacement gate stack, wherein the replacement gate stack has a fourth width at the first height, and wherein the replacement gate stack has a fifth width at the second height that is different from the fourth width.

8. The method of claim 1, wherein one of the plurality of etch processes forms a first sidewall slope in a first portion of the dummy gate stack and another of the plurality of etch processes forms a second sidewall slope in a second portion of the dummy gate stack, wherein the second sidewall slope is different from the first sidewall slope.

9. A method of forming a semiconductor device, comprising:

Forming a dummy gate layer over a substrate;

Forming a first opening in the dummy gate layer, comprising:

Performing a first plasma etch process including a first pulsed bias having a first duty cycle related to a first desired metal gate width at a first height above the substrate;

Performing a second plasma etch process including a second pulsed bias having a second duty cycle related to a second desired metal gate width at a second height above the substrate; and

performing a third plasma etch process including a third pulsed bias having a third duty cycle related to a third desired metal gate width at a third height above the substrate;

Forming a dielectric material in the first opening;

Removing the remaining part of the dummy gate layer to form a second opening; and

Forming a metal gate in the second opening, the metal gate having the first desired metal gate width at the first height above the substrate, the second desired metal gate width at the second height above the substrate, and the third desired metal gate width at the third height above the substrate.

10. a semiconductor device, comprising:

A semiconductor fin protruding above a substrate by a first height; and

A gate stack spanning the semiconductor fin, a first portion of the gate stack having a first width at the first height, a second portion of the gate stack having a second width different from the first width proximate a top surface of the gate stack, and a third portion of the gate stack having a third width different from the first width proximate a bottom surface of the gate stack, wherein a portion of the gate stack extending from the first height to the top surface of the gate stack and a portion of the gate stack extending from the first height to the bottom surface of the gate stack have different sidewall slopes.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing layers of insulating or dielectric materials, conductive materials, and semiconductor materials over a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit components and elements on the various material layers.

The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise in each of the processes used, and these additional problems should be solved.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a semiconductor device, including: forming a semiconductor fin extending a first height above a substrate; forming a dummy dielectric material over the semiconductor fin and over the substrate; forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate; and etching the dummy gate material using a plurality of etching processes to form a dummy gate stack, wherein each etching process of the plurality of etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a dummy gate layer over a substrate; forming a first opening in the dummy gate layer, comprising: performing a first plasma etch process including a first pulsed bias having a first duty cycle related to a first desired metal gate width at a first height above the substrate; performing a second plasma etch process including a second pulsed bias having a second duty cycle related to a second desired metal gate width at a second height above the substrate; and performing a third plasma etch process including a third pulsed bias having a third duty cycle related to a third desired metal gate width at a third height above the substrate; forming a dielectric material in the first opening; removing the remaining part of the dummy gate layer to form a second opening; and forming a metal gate in the second opening, the metal gate having the first desired metal gate width at the first height above the substrate, the second desired metal gate width at the second height above the substrate, and the third desired metal gate width at the third height above the substrate.

Still another embodiment of the present invention provides a semiconductor device including: a semiconductor fin protruding above a substrate by a first height; and a gate stack spanning the semiconductor fin, a first portion of the gate stack having a first width at the first height, a second portion of the gate stack having a second width different from the first width proximate a top surface of the gate stack, and a third portion of the gate stack having a third width different from the first width proximate a bottom surface of the gate stack, wherein a portion of the gate stack extending from the first height to the top surface of the gate stack and a portion of the gate stack extending from the first height to the bottom surface of the gate stack have different sidewall slopes.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments.

Fig. 2 illustrates a substrate according to some embodiments.

Figure 3 illustrates the formation of a film stack according to some embodiments.

Fig. 4 illustrates formation of a mandrel according to some embodiments.

Fig. 5 illustrates formation of a spacer layer according to some embodiments.

Fig. 6 illustrates formation of a spacer according to some embodiments.

FIG. 7 illustrates removal of a mandrel according to some embodiments.

Fig. 8 illustrates patterning of a film stack according to some embodiments.

fig. 9 illustrates formation of a fin according to some embodiments.

Fig. 10 illustrates the formation of an insulating material according to some embodiments.

Fig. 11 illustrates formation of a shallow trench isolation region according to some embodiments.

Fig. 12A-12B illustrate formation of a dummy gate layer according to some embodiments.

Figure 13 illustrates the formation of a film stack according to some embodiments.

Fig. 14 illustrates formation of a mandrel according to some embodiments.

Fig. 15 illustrates formation of a spacer layer according to some embodiments.

Fig. 16 illustrates formation of a spacer according to some embodiments.

FIG. 17 illustrates removal of a mandrel according to some embodiments.

Fig. 18 illustrates patterning of a film stack according to some embodiments.

Fig. 19 illustrates further patterning of the film stack according to some embodiments.

Fig. 20A-20B illustrate a dummy gate layer according to some embodiments.

Fig. 21A-21B illustrate a first etch process of a dummy gate layer according to some embodiments.

Fig. 22A-22B illustrate a second etch process for a dummy gate layer according to some embodiments.

Fig. 23A-23B illustrate a third etch process of a dummy gate layer according to some embodiments.

Fig. 24A-24C illustrate exemplary dummy gate profile shapes according to some embodiments.

FIG. 25 illustrates a dummy gate according to some embodiments.

Fig. 26A-26B illustrate the formation of spacers according to some embodiments.

Fig. 27A-27B illustrate the formation of a gate spacer layer according to some embodiments.

Fig. 28A-28B illustrate the formation of gate spacers according to some embodiments.

fig. 29A-29D illustrate the formation of epitaxial source/drain regions according to some embodiments.

Fig. 30A-30B illustrate the formation of a contact etch stop layer according to some embodiments.

Fig. 31A-31B illustrate the formation of an interlayer dielectric according to some embodiments.

Fig. 32A-32B illustrate a planarization process according to some embodiments.

Fig. 33A-33B illustrate removal of dummy gates according to some embodiments.

Fig. 34A-34B illustrate the formation of a replacement gate stack according to some embodiments.

Fig. 35A-35B illustrate the formation of a hard mask according to some embodiments.

Fig. 36A-36B illustrate the formation of an interlayer dielectric according to some embodiments.

Fig. 37A-37B illustrate the formation of contact openings according to some embodiments.

Fig. 38A-38B illustrate formation of contacts according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

semiconductor devices and methods of forming semiconductor devices are provided according to some embodiments. Specifically, a dummy gate is formed using a plurality of etching steps, and the profile shape of the dummy gate can be controlled by controlling the parameter or condition of each etching step. For example, the width of the portion of the dummy gate may be controlled by controlling parameters of an etching step of the portion where the dummy gate is formed. In this way, the profile shape of the dummy gate can be "tuned" to improve process yield or device performance. Etch step parameters that may be controlled include passivation gas flow rate, pulse voltage bias duty cycle, pulse plasma generation power duty cycle, bias voltage, or other parameters. Some embodiments discussed herein are discussed in the context of finfets formed using a gate-last process. In other embodiments, a gate first process may be used. Moreover, some embodiments contemplate various aspects for planar devices such as planar FETs.

fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments. The FinFET includes a fin 74 located on the substrate 50. Isolation regions 72 are located on substrate 50, and fins 74 protrude above adjacent isolation regions 72 and protrude from between adjacent isolation regions 72. A gate dielectric layer 118 is along the sidewalls of fin 74 and over the top surface of fin 74, and a gate fill 120 is over gate dielectric layer 118. Source/drain regions 102 are disposed in an opposite side of fin 74 relative to gate dielectric layer 118 and gate fill 120. Fig. 1 further shows a reference cross section used in subsequent figures. Section a-a is along a lateral axis of fin 74, which extends in the direction of, for example, gate fill 120. Cross section B-B is perpendicular to cross section a-a and along the longitudinal axis of fin 74, which extends in the direction of current flow, for example, between source/drain regions 102. Section C-C is a section parallel to section B-B, but offset from fin 74 of the FinFET. For clarity, the figures that follow refer to these reference sections.

Fig. 2-38B are cross-sectional views of intermediate stages in fabrication of a FinFET according to some embodiments. Fig. 2 to 11 show the reference section a-a in fig. 1. Fig. 12A shows a reference section a-a in fig. 1, and fig. 12B shows a reference section B-B in fig. 1. Fig. 13 to 19 show a reference section B-B in fig. 1. Fig. 20A, 21A, 22A and 23A are shown along a reference section B-B in fig. 1, and fig. 20B, 21B, 22B and 23B are shown along a reference section C-C in fig. 1. Fig. 24A to 24C are shown along a reference section C-C in fig. 1. Fig. 25 shows the reference section B-B in fig. 1. In fig. 26A-38B, the diagram ending with the "a" symbol is shown along the reference section a-a in fig. 1, and the diagram ending with the "B" symbol is shown along the similar section B-B.

Fig. 2 illustrates a substrate 50 according to some embodiments. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer may be provided over a substrate such as a silicon substrate or a glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; and the like or combinations thereof.

The substrate 50 shown in fig. 2 includes a first region 50B and a second region 50C. The first region 50B may be used to form an n-type device such as an NMOS transistor (e.g., an n-type FinFET). The second region 50C may be used to form a p-type device such as a PMOS transistor (e.g., a p-type FinFET). In some embodiments, first region 50B and second region 50C are both used to form the same type of device, such as both regions being used for either an n-type device or a p-type device. The first and second regions 50B, 50C may be located apart from one another, and any number of structures (e.g., isolation regions, active devices, etc.) may be disposed between the first and second regions 50B, 50C.

in fig. 3, a film stack is formed over a substrate 50. The film stack is used during processing to form features in the substrate 50 that are part of the minimum lithographic pitch. In some embodiments, the process is a self-aligned double patterning (SADP) process, wherein the features formed are half of the minimum lithographic pitch. In other embodiments, the process may be a self-aligned quad patterning (SAQP) process, wherein the features formed are one-quarter of the minimum lithographic pitch. The film stack includes an anti-reflective coating (ARC) layer 52, a mask layer 54, and a mandrel layer 56. In other embodiments, the film stack may include more or fewer layers.

ARC52 is formed over substrate 50 and facilitates exposure and focusing of an overlying photoresist layer during patterning of the photoresist layer (discussed below). In some embodiments, ARC52 may be formed of SiON, SiC, a material doped with oxygen (O) and nitrogen (N), or the like. In some embodiments, ARC52 is substantially free of nitrogen and may be formed from an oxide.

A mask layer 54 is formed over ARC 52. The mask layer 54 may be formed of a hard mask material and may include a metal and/or a dielectric material. In some embodiments, mask layer 54 comprises a metal such as titanium nitride, titanium, tantalum nitride, tantalum, and the like. In some embodiments, masking layer 54 comprises a dielectric formed of oxide, nitride, or the like. The mask layer 54 may be formed by PVD, radio frequency PVD (rfpvd), Atomic Layer Deposition (ALD), or the like. In subsequent process steps, a pattern is formed in the mask layer 54. The pattern in mask layer 54 is then transferred to substrate 50 using mask layer 54 as an etch mask.

Mandrel layer 56 is a sacrificial layer formed over mask layer 54. Mandrel layer 56 may be formed of a material having a high etch selectivity with respect to the underlying layers (e.g., with respect to mask layer 54). The mandrel layer 56 may be formed of a material such as amorphous silicon, polysilicon, silicon nitride, silicon oxide, or the like, or a combination thereof, and may be formed using a process such as Chemical Vapor Deposition (CVD), PECVD, or the like.

In fig. 4, mandrel layer 56 is patterned to form mandrel 58. Mandrel layer 56 may be patterned using any suitable photolithographic technique. As an example of patterning mandrel layer 56, a tri-layer photoresist structure (not shown) may be formed over the film stack. The tri-layer photoresist structure may include a lower layer, an intermediate layer, and an upper layer. The upper layer may be formed of a photosensitive material such as photoresist, and the photosensitive material may include an organic material. The lower layer may be a bottom anti-reflective coating (BARC). The intermediate layer may be formed of or include an inorganic material such as a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The intermediate layer may have a high etch selectivity with respect to the upper and lower layers. In some embodiments, the upper layer serves as an etch mask for patterning the intermediate layer, and the intermediate layer serves as an etch mask for patterning the lower layer.

the upper layer may be patterned after formation using any suitable lithographic technique to form openings therein. After patterning of the upper layer, an etching process is performed to transfer the pattern of the openings in the upper layer to the intermediate layer. The etching process may be anisotropic. After transferring the pattern of openings to the intermediate layer, the intermediate layer may be trimmed to adjust the size of the openings. In some cases, the pitch of the openings in the intermediate layer may be about equal to the minimum lithographic pitch after trimming. After trimming of the intermediate layer, an etching process is performed to transfer the pattern of the intermediate layer to the underlying layer. In some embodiments, the upper layer may be removed during an etching process that transfers the pattern of the intermediate layer to the lower layer.

After the pattern is transferred to the underlying layer, an etching process is performed to transfer the underlying pattern to mandrel layer 56. The etching process may remove portions of the mandrel layer 56 exposed by the intermediate and underlying layers. In an embodiment, the etching process may be dry etching. For example, the etching process may expose the mandrel layer 56 to a plasma source and one or more etchant gases. The etching process may include inductively coupled plasma (ICR) etching, Transformer Coupled Plasma (TCP) etching, Electron Cyclotron Resonance (ECR) etching, Reactive Ion Etching (RIE), and the like. As shown in fig. 4, the remaining portion of mandrel layer 56 forms mandrel 58. In some embodiments, the etching process used to transfer the pattern to mandrel layer 56 may remove the intermediate layer and partially remove portions of the underlying layer. An ashing process may be performed to remove remaining residues of the intermediate and/or lower layers.

in fig. 5, a spacer layer 62 is formed over mask layer 54 and mandrel 58. After formation, spacer layer 62 extends along mask layer 54 and the top surface of mandrel 58 and the sidewalls of mandrel 58. The material of the spacer layer 62 may be selected to have a high etch selectivity relative to the mask layer 54. The spacer layer 62 may be formed of AlO, AlN, AlON, TaN, TiN, TiO, Si, SiO, SiN, a metal alloy, or the like, and may be deposited using any suitable process, such as ALD, CVD, or the like.

In fig. 6, a suitable etching process is performed to remove the horizontal portions of spacer layer 62. In some embodiments, the etchant used to etch the horizontal portions of spacer layer 62 is Cl₂、CH₄、N₂Ar, and the like, or combinations thereof. After the etching process, vertical portions of spacer layer 62 remain along the sides of mandrel 58, and are referred to hereinafter as spacers 64. The etching process may be anisotropic such that the thickness of the spacers 64 is not significantly reduced.

In fig. 7, mandrel 58 is removed. Mandrel 58 may be removed by a suitable etching process, such as by including, for example, CF₄、CH₃F、H₂、N₂An etchant of Ar, or the like, or a combination thereof. The etching process may include any other suitable etchant that may remove mandrel 58 without substantially damaging spacer 64. In addition, a wet etch process may also be performed to remove the remaining spacer and mandrel material. In some embodiments, the spacer etching process and the mandrel removal process are performed in the same process chamber.

In fig. 8, the mask layer 54 is patterned using the spacers 64 as an etch mask. Any suitable chemistry (such as CF) may be used₄、HBr、Cl₂、O₂ar, etc., or combinations thereof) to perform a suitable etching process, such as anisotropic etching. In fig. 9, a fin 68 is formed in the substrate 50. Fin 68 is formed by using patterned masking layer 54 as an etch mask to etch ARC52 and substrate 50, thereby forming a trench in substrate 50. The semiconductor strips created between the trenches form fins 68. The etch may be performed using any acceptable etch process, and may use, for example, Cl₂、N₂、CH₄And the like or combinations thereof. The etching process may be anisotropic. In some cases, the spacers 64, patterned masking layer 54, or patterned ARC52 may be consumed in the process. In some embodiments, a cleaning process may be performed to remove the spacers 64, the patterned masking layer 54, and any residual material of the patterned ARC 52.

In fig. 10, an insulating material 70 is formed over substrate 50 and between adjacent fins 68. The insulating material 70 may be an oxide, such as silicon oxide, nitride, or the like, or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (fcvd) (e.g., CVD based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), or the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In some cases, once the insulating material is formed, an annealing process may be performed. In some embodiments, a planarization process such as grinding or Chemical Mechanical Polishing (CMP) may be performed to expose the top surface of fin 68.

In fig. 11, insulating material 70 is recessed to form Shallow Trench Isolation (STI) regions 72. Insulating material 70 is recessed such that fins 68 in first region 50B and second region 50C protrude from between adjacent STI regions 72. The top surface of STI region 72 may have a flat surface (as shown in fig. 11), a convex surface, a concave surface (e.g., a concave surface), other shapes, or combinations thereof. In some embodiments, the top surface of STI region 72 may be formed flat, convex, and/or concave by an appropriate etching process. Insulative material 70 may be recessed using an acceptable etch process, such as an etch process that is selective to the material of insulative material 70. For example, chemical oxide removal with dilute hydrofluoric acid (dHF) or other techniques may be used. In some embodiments, fin 74, fin 68, and/or substrate 50 may be doped after forming STI region 72.

In fig. 12A to 12B, a dummy dielectric layer 76 is formed on the fin 74. Fig. 12A shows a structure along a section a-a similar to that shown in fig. 1, and fig. 12B shows a structure along a section B-B similar to that shown in fig. 1. The dummy dielectric layer 76 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques (e.g., thermal oxidation). A dummy gate layer 78 is formed over dummy dielectric layer 76. Dummy gate layer 78 may be deposited over dummy dielectric layer 76 and then planarized, such as by CMP. Dummy gate layer 78 may be a conductive material and may be selected from the group consisting of polysilicon (poly-silicon), poly-silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. In some embodiments, amorphous silicon is deposited and recrystallized to produce polysilicon. Dummy gate layer 78 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. Dummy gate layer 78 may be made of other materials that have a high etch selectivity with respect to the etching of the isolation regions. In this example, a single dummy gate layer 78 is formed across the first region 50B and the second region 50C. In other embodiments, separate dummy gate layers may be formed in the first and second regions 50B and 50C. In some embodiments, the thickness T1 of the portion of dummy gate layer 78 overlying fin 74 may be between about 85nm and about 95nm, and the thickness T2 of the portion of dummy gate layer 78 overlying STI region 72 may be between about 140nm and about 150 nm.

In fig. 13, a film stack is formed over dummy gate layer 78. The film stack is used during processing to form features in dummy gate layer 78. The film stack includes ARC 80, mask layer 82, and mandrel layer 84. ARC 80 is formed over dummy gate layer 78. ARC 80 may be formed from a material selected from the same candidate material for ARC52 and may be formed using a method selected from the group of the same candidate methods used to form ARC 52. ARCs 52 and 80 may be formed of the same material or may comprise different materials. In some embodiments, ARC 80 may be formed to have a thickness between about 15nm and about 25 nm.

A mask layer 82 is formed over ARC 80. The mask layer 82 may be formed of a material selected from the same candidate materials for the mask layer 54, and may be formed using a method selected from the group of the same candidate methods for forming the mask layer 54. Masking layers 54 and 82 may be formed of the same material or may comprise different materials. In some embodiments, the mask layer 82 may be formed to have a thickness between about 90nm and about 110 nm.

Mandrel layer 84 is formed over mask layer 82. Mandrel layer 84 may be formed from a material selected from the same candidate materials for mandrel layer 56 and may be formed using a method selected from the group of the same candidate methods used to form mandrel layer 56. Mandrel layers 56 and 84 may be formed of the same material, or may comprise different materials. In some embodiments, mandrel layer 84 may be formed to have a thickness between about 90nm and about 110 nm.

In fig. 14, mandrel layer 84 is patterned to form mandrel 86. Mandrel layer 84 may be patterned using any suitable photolithographic technique. As an example of patterning mandrel layer 84, a tri-layer photoresist structure (not shown) may be formed over the film stack. The tri-layer photoresist structure may include a lower layer, an intermediate layer, and an upper layer. The photoresist may be patterned with a pattern of mandrels 86 and an etching process may remove the portions of mandrel layer 84 exposed by the photoresist. The remaining portion of mandrel layer 84 forms mandrel 86, as shown in fig. 14.

In fig. 15, a spacer layer 90 is formed over the mask layer 82 and mandrel 86. Spacer layer 90 may be formed from a material selected from the same candidate materials for spacer layer 62 and may be formed using a method selected from the group of the same candidate methods used to form spacer layer 62. Mandrel spacer layers 62 and 90 may be formed of the same material, or may comprise different materials. For example, the spacer layer 90 may be formed of SiN using an ALD process.

In fig. 16, a suitable etching process is performed to remove horizontal portions of spacer layer 90 to form spacers 92. The horizontal portions of spacer layer 90 may be removed in a manner similar to the method of removing the horizontal portions of spacer layer 62. After the etching process, vertical portions of the spacer layer 90 remain along the sides of the mandrel 86, and are referred to hereinafter as spacers 92. In fig. 17, the mandrel 86 is removed. Mandrel 86 may be removed by a suitable etching process, such as by including, for example, CF₄、CH₃F、H₂、N₂An etchant such as Ar, other etchant, or a combination thereof. A wet clean process may also be performed to remove residual spacer and mandrel material. In some embodiments, the spacer etching process and the mandrel removal process are performed in the same process chamber.

In fig. 18, a suitable etching process is performed to pattern the mask layer 82. The spacer 92 serves as an etching mask, and thus, the pattern of the spacer 92 is transferred to the mask layer 82 to form an opening in the mask layer 82. The etching process may be similar to that described above with respect to patterned masking layer 54, or may be a different process. In fig. 19, a suitable etch process is performed to etch ARC 80 using patterned masking layer 82 as an etch mask. The etching process may be any acceptable etching process and may be an anisotropic etching process. In some cases, ARC 80 and dummy gate layer 78 may be etched in the same etch process.

Fig. 19-24C illustrate the patterning of dummy gate layer 78 to form dummy gate 94 according to an embodiment. In fig. 21A to 24C, portions of the dummy gate 94 are labeled as a first dummy gate portion 94A and a second dummy gate portion 94B. For clarity, the patterning of only two dummy gates 94 is shown in fig. 20A to 23B. Fig. 20A, 21A, 22A, and 23A show a cross section along B-B shown in fig. 1, which is a cross section along fin 74. Fig. 20B, 21B, 22B, and 23B show cross-sections along C-C shown in fig. 1 that are parallel to B-B and offset from the cross-section of B-B such that no portion of fin 74 is included. Accordingly, fig. 20A, 21A, 22A, and 23A show portions of dummy gate layer 78 over fin 74, and fig. 20B, 21B, 22B, and 23B show portions of dummy gate layer 78 over STI regions 72.

fig. 20A-20B show dummy gate layer 78 (shown in fig. 19) prior to patterning. In fig. 21A-21B, a first etch process 93 is performed to etch portions of dummy gate layer 78. A first etch process 93 patterns dummy gate layer 78 and forms a first dummy gate portion 94A. In some embodiments, dummy gate layer 78 is etched by first etch process 93 to a depth D1 (shown in fig. 21A) approximately equal to a thickness T1 of a portion of dummy gate layer 78 overlying fin 74. In other embodiments, the first etch process 93 etches the dummy gate layer 78 to a greater or lesser depth. In some embodiments, the dummy dielectric layer 76 (shown in fig. 21A) on the fin 74 serves as an etch stop for the first etch process 93, and thus the depth D1 may be approximately equal to the thickness T1. In this way, the portion of dummy gate layer 78 (shown in fig. 21B) located over STI region 72 may be etched to a depth D2 that is greater than depth D1. In some embodiments, the first etch process 93 may etch the dummy gate layer 78 to a depth D2 of between about 85nm and about 95 nm. In some embodiments, parameters of the first etch process 93 may be controlled to form a first dummy gate portion 94A having a desired profile or shape, as will be described in more detail below. The first etch process 93 may remove some or all of the spacers 92. In some embodiments, the first etch process 93 includes an anisotropic etch performed by a plasma process, as described in more detail below.

in fig. 22A-22B, a second etch process 95 is performed to further etch portions of dummy gate layer 78. Second etch process 95 etches dummy gate layer 78 and forms second dummy gate portion 94B. In some embodiments, second etch process 95 etches dummy gate layer 78 to a depth D3. In some embodiments, the dummy dielectric layer 76 serves as an etch stop for the second etch process 95. In some embodiments, second etch process 95 may etch dummy gate layer 78 to a depth D3 of between about 49nm and about 59 nm. In some embodiments, parameters of the second etch process 95 may be controlled to form the second dummy gate portion 94B with a desired profile or shape, as will be described in more detail below. In some embodiments, the second etch process 95 includes an anisotropic etch performed by a plasma process, as will be described in more detail below.

In fig. 23A-23B, a third etch process 97 is performed to further etch portions of dummy gate layer 78. In some embodiments, the third etch process 97 is an "over etch" process that removes residues (e.g., "stringers") and provides some additional etching of the second dummy gate portion 94B. In some embodiments, parameters of the third etch process 97 may be controlled to reshape the second dummy gate portion 94B to have a desired profile or shape, as will be described in more detail below. In some embodiments, the third etch process 97 includes an anisotropic etch performed by a plasma process, also described in more detail below. In this manner, dummy gate 94 is formed from dummy gate layer 78 using first etch process 93, second etch process 95, and third etch process 97. In some embodiments, additional etching processes may be used.

In some embodiments, the profile shape of the dummy gate 94 may be controlled by controlling parameters of the first etch process 93, the second etch process 95, and/or the third etch process 97. For example, different widths of dummy gate 94 at different locations along dummy gate 94 may be controlled. The widths W1, W2, and W3 shown in fig. 23B as illustrative examples indicate three locations along the dummy gate 94 that may be controlled by the first etch process 93, the second etch process 95, and/or the third etch process 97. Other locations, more locations, or fewer locations along dummy gate 94 may be used to characterize the profile shape of dummy gate 94. Width W1 is about 5nm above the location on dummy gate 94 that is flush with the top surface of fin 74. Width W2 is at a location on dummy gate 94 that is substantially flush with the top surface of adjacent fin 74. In some cases, width W2 is located at approximately the top of second dummy gate portion 94B. Width W3 is about 10nm above the bottom of dummy gate 94 on dummy gate 94.

In some embodiments, the profile shape of the first dummy gate portion 94A may be controlled by controlling parameters of the first etch process 93. For example, the width W1 of the dummy gate 94 may be controlled in this manner. In some embodiments, the first etch process 93 includes a plasma etch process performed in a process chamber, wherein a process gas is supplied into the process chamber. In some embodiments, the plasma generation power may be pulsed between a low power and a high power during the first etch process 93. During the first etch process 93, the applied bias voltage may be pulsed between a low voltage and a high voltage. The low power may include zero power and the low voltage may include zero voltage. The plasma generating power or bias voltage may be pulsed as a rectangular or square wave, but other pulse shapes may be used. In some embodiments, the plasma generation power and the bias voltage may have synchronized pulses such that the plasma generation power and the bias voltage are in their respective low or high states simultaneously. In some embodiments, the plasma is a direct plasma. In other embodiments, the plasma is a remote plasma that is generated in a separate plasma generation chamber connected to the process chamber. The process gas may be activated into the plasma by any suitable method of generating a plasma, such as Transformer Coupled Plasma (TCP) systems, Inductively Coupled Plasma (ICP) systems, magnetically enhanced reactive ion techniques, electron cyclotron resonance techniques, and the like.

The process gas used in the first etch process 93 may include, for example, CF₄、CHF₃、Cl₂、H₂、N₂Ar, other gases or combinations of gases. In some embodiments, the process gas also includes HBr, O, for example₂Other gases or combinations of gases. Such as N₂Carrier gases such as Ar, He, etc. may be used to carry the process gases into the process chamber. The process gas can be flowed into the process chamber at a rate between about 300sccm and about 400 sccm. For example, the etching gas may be flowed into the process chamber at a rate between about 30sccm and about 50sccm, and the passivating gas may be flowed into the process chamber at a rate between about 200sccm and about 300 sccm. In some embodiments, the passivation gas may be HBr and O₂In which HBr: O₂Is between about 3:1 and about 5: 1.

The first etch process 93 may be performed using a bias voltage having a high voltage between about 600 volts and about 700 volts. The first etch process 93 may be performed using a plasma generation power having a high power between about 1000 watts to about 1500 watts. In some embodiments, the plasma generation power or bias voltage may be pulsed with a duty cycle between about 2% and about 8%, and may have a pulse frequency between about 100Hz and about 200 Hz. The first etching process 93 may be performed at a temperature of about 38 ℃ to about 43 ℃. The pressure in the process chamber can be between about 20mTorr and about 30 mTorr.

In some embodiments, the profile shape of the first dummy gate portion 94A may be controlled by controlling the flow rate of the passivation gas into the process chamber during the first etch process 93. For example, increasing the flow rate of the passivation gas by between about 1% and about 5% may increase the width W1 by between about 2 angstroms and about 12 angstroms. In some embodiments, the profile shape of the first dummy gate portion 94A may be controlled by controlling the duty cycle of the simultaneous plasma generation power and bias voltage pulse. For example, increasing the duty cycle of the synchronization pulse by an amount between about 1% and about 3% may cause the width W1 to increasePlus about 0.38nm and aboutIn the meantime. By controlling the flow rate of the passivation gas and the duty ratio of the synchronization pulse, the profile and width of the first dummy gate portion 94A can be controlled. For example, the width of the first dummy gate portion 94A after the first etch process 93 may be increased or decreased by controlling these etch parameters. Specifically, the width W1 near the bottom of the first dummy gate portion 94A may be controlled. In some cases, changing the parameters may cause the first dummy gate portion 94A to be wider near the bottom, have a substantially constant width, or be wider near the top.

In some embodiments, the profile shape of dummy gate 94 may be controlled by controlling parameters of second etch process 95. For example, the width W2 of the dummy gate 94 may be controlled in this manner. In some embodiments, the second etch process 95 comprises a plasma etch process performed in a process chamber, wherein process gases are supplied into the process chamber, which may be the same process chamber used for the first etch process 93. In some embodiments, the plasma generation power may be maintained at a substantially constant power during the second etch process 95. During the second etch process 95, the applied bias voltage may be pulsed between a low voltage and a high voltage. The low voltage may comprise a zero voltage. The bias voltage may be pulsed as a rectangular or square wave, but other pulse shapes may be used. In some embodiments, the plasma is a direct plasma. In other embodiments, the plasma is a remote plasma that is generated in a separate plasma generation chamber connected to the process chamber. The process gas may be activated into the plasma by any suitable method of generating a plasma, such as a TCP system, an ICP system, a magnetically enhanced reactive ion technique, an electron cyclotron resonance technique, or the like.

The process gas used in the second etch process 95 may include, for example, CF₄、CHF₃、Cl₂、H₂、N₂Ar, other gases or combinations of gases. In some embodiments, the toolProcess gases also include such gases as HBr, O₂Other gases or combinations of gases. Such as N₂Carrier gases such as Ar, He, etc. may be used to carry the process gases into the process chamber. The etch gas may be flowed into the process chamber at a rate between about 120sccm and about 250 sccm.

The second etch process 95 may be performed using a bias voltage having a low voltage between about 600 volts and about 700 volts and having a high voltage between about 800 volts and about 900 volts. The second etch process 95 may be performed using a substantially constant plasma generation power of between about 500 watts and about 700 watts. In some embodiments, the bias voltage may be pulsed with a duty cycle between about 5% and about 8%, and may have a pulse frequency between about 100Hz and about 300 Hz. The second etching process 95 may be performed at a temperature of about 34 ℃ to about 50 ℃. The pressure in the process chamber can be between about 70mTorr and about 90 mTorr.

In some embodiments, the profile shape of the dummy gate 94 may be controlled by controlling the low voltage and/or the high voltage of the pulsed bias voltage during the second etch process 95. For example, increasing the high voltage by between about 1% and about 3.5% may cause the width W2 to decrease by aboutAnd the combinationIn the meantime. In some embodiments, the profile shape of the dummy gate 94 may be controlled by controlling the duty cycle of the bias voltage pulse. For example, increasing the duty cycle of the bias voltage pulse by an amount between about 1% and about 3% may decrease the width W2 by between about 1.12nm and about 1.96 nm. By controlling the voltage and duty cycle of the pulsed bias voltage, the profile and width of dummy gate 94 can be controlled. For example, the width of the dummy gate 94 after the second etch process 95 may be increased or decreased by controlling these etch parameters. In particular, the width W2 of dummy gate 94 near the top of fin 74 may be controlled. In some cases, changing the parameter may cause first dummy gate portion 94A or second dummy gate portion 94B to be inWider near the bottom, have a substantially constant width, or be wider near the top.

In some embodiments, the profile shape of dummy gate 94 may be controlled by controlling parameters of third etch process 97. For example, the width W3 of the dummy gate 94 may be controlled in this manner. In some embodiments, the third etch process 97 includes a plasma etch process performed in a process chamber, wherein the process gas is supplied into the process chamber, which may be the same process chamber used for the first etch process 93 or the second etch process 95. In some embodiments, the plasma generation power may be maintained at a substantially constant power during the third etch process 97. During the third etch process 97, the applied bias voltage may be pulsed between a low voltage and a high voltage. The low voltage may comprise a zero voltage. The bias voltage may be pulsed as a rectangular or square wave, but other pulse shapes may be used. In some embodiments, the plasma is a direct plasma. In other embodiments, the plasma is a remote plasma that is generated in a separate plasma generation chamber connected to the process chamber. The process gas may be activated into the plasma by any suitable method of generating a plasma, such as a TCP system, an ICP system, a magnetically enhanced reactive ion technique, an electron cyclotron resonance technique, or the like.

The process gas used in the third etch process 97 may include, for example, CF₄、CHF₃、Cl₂、H₂、N₂Ar, other gases or combinations of gases. In some embodiments, the process gas also includes HBr, O, for example₂Other gases or combinations of gases. Such as N₂Carrier gases such as Ar, He, etc. may be used to carry the process gases into the process chamber. The process gas can be flowed into the process chamber at a rate between about 400sccm and about 550 sccm. For example, the etching gas may be flowed into the process chamber at a rate between about 130sccm and about 210sccm, and the passivating gas may be flowed into the process chamber at a rate between about 200sccm and about 250 sccm. In some embodiments, the passivation gas may be HBr and O₂In which HBr: O₂Is between about 3:1 and about 4: 1.

The third etch process 97 may be performed using a bias voltage having a low voltage between about 850 volts and about 900 volts and having a high voltage between about 900 volts and about 950 volts. The third etch process 97 may be performed using a substantially constant plasma generation power of between about 250 watts and about 350 watts. In some embodiments, the bias voltage may be pulsed with a duty cycle between about 10% and about 20%, and may have a pulse frequency between about 100Hz and about 200 Hz. The third etch process 97 may be performed at a temperature between about 40 ℃ to about 50 ℃. The pressure in the process chamber can be between about 70mTorr and about 90 mTorr.

In some embodiments, the profile shape of the dummy gate 94 may be controlled by controlling the flow rate of the passivation gas to the process chamber during the third etch process 97. For example, a reduction in the flow rate of the passivation gas of between about 0.5% and about 2% may result in a reduction in the width W3 of aboutAnd the combinationIn the meantime. In some embodiments, the profile shape of the dummy gate 94 may be controlled by controlling the duty cycle of the bias voltage pulse. For example, increasing the duty cycle of the bias voltage pulse by an amount between about 1% and about 3% may increase the width W3 by about 0.24nm and aboutin the meantime. By controlling the flow rate of the passivation gas and the duty cycle of the bias voltage pulses, the profile and width of the dummy gate 94 may be controlled. For example, the width of the dummy gate 94 after the third etch process 97 may be increased or decreased by controlling these etch parameters. Specifically, the width W3 near the bottom of the dummy gate 94 may be controlled. In some cases, changing the parameters may cause the second dummy gate portion 94B to be wider near the bottom, have a substantially constant width, or be wider near the top. In this way, can be directed toThe particular application controls the profile shape of dummy gate 94, for example, to produce a metal gate having a particular profile. In some cases, the profile shape of dummy gate 94 may be controlled to reduce the likelihood of certain process defects occurring.

As described above, the dummy gate 94 is etched by using a separate etching process, and by controlling parameters of the etching process, the profile shape of the dummy gate 94 can be controlled. The parameters of the etch process may include a passivation gas flow rate, a bias voltage, a pulse duty cycle, or other parameters. In this manner, different portions of dummy gate 94 may be etched to have a desired profile, shape, or sidewall slope. The desired profile may include, for example, a convex shape, a concave shape, a slanted shape, or other shapes. In some embodiments, the desired profile may include portions of dummy gate 94 having different slopes, different widths, or other different characteristics. In some embodiments, the portion of dummy gate 94 disposed over fin 74 (e.g., first dummy gate portion 94A) may be formed to have a different profile, shape, or sidewall slope than the portion of dummy gate 94 disposed adjacent fin 74 (e.g., second dummy gate portion 94B). Fig. 24A-24C show illustrative examples of some profile shapes of dummy gate 94 that may be formed using the techniques described herein. These are exemplary profile shapes, and other profile shapes are also within the scope of the present invention.

Fig. 24A shows an exemplary dummy gate 94, wherein a top width near a top of dummy gate 94 and a bottom width near a bottom of dummy gate 94 are both greater than an intermediate width between the top width and the top width. As shown in the example of fig. 24A, the width W2 is less than the width W1 or the width W3. For this example profile shape, the width W1 may be greater than the width W3, less than the width W3, or approximately the same as the width W3. In some embodiments, a profile shape similar to that shown in fig. 24A may be formed such that width W1 is between about 0% and about 10% greater than width W2, and width W3 is between about 0% and about 10% greater than width W2.

Fig. 24B shows an exemplary dummy gate 94, wherein a top width near a top of dummy gate 94 is greater than a middle width, and a bottom width near a bottom of dummy gate 94 is less than the middle width. As shown in the example of fig. 24B, width W1 is greater than width W2, and width W2 is greater than width W3. In other cases, width W1 may be substantially the same as width W2, or width W2 may be substantially the same as width W3. In some embodiments, a profile shape similar to that shown in fig. 24B may be formed such that width W1 is between about 0% and about 10% greater than width W2, and width W2 is between about 0% and about 10% greater than width W3. In some embodiments, a tapered profile shape similar to that shown in fig. 24B may be formed using techniques described herein to allow for improved metal gate fill (described below).

Fig. 24C shows an exemplary dummy gate 94, wherein a top width near a top of dummy gate 94 and a bottom width near a bottom of dummy gate 94 are both smaller than the middle width. As shown in the example of fig. 24C, the width W2 is greater than the width W1 or the width W3. For this example profile shape, the width W1 may be greater than the width W3, less than the width W3, or approximately the same as the width W3. In some embodiments, a profile shape similar to that shown in fig. 24C may be formed such that width W2 is between about 0% and about 10% greater than width W1, and width W2 is between about 0% and about 10% greater than width W3. As shown in fig. 24A-24C, in some embodiments, the profile or shape of dummy gate 94 over fin 74 may be formed differently than the profile or shape of dummy gate 94 adjacent to fin 74.

Fig. 25 shows the structure shown in fig. 19 after performing a first etch process 93, a second etch process 95, and a third etch process 97 (as described above with reference to fig. 20A-24C). Turning to fig. 26A-26B, spacers 100 may be formed on the exposed surfaces of dummy gate 94, patterned masking layer 82, ARC 80, and/or fin 74. In some embodiments, the spacer 100 may be formed by a thermal oxidation process or a deposition process followed by an anisotropic etching process.

After the formation of the spacers 100, an implantation process for lightly doping the source/drain (LDD) regions 101 may be performed. In some embodiments including forming different types of devices, a mask may be formed over the first region 50B and the second region 50C left exposed. Can classify as appropriateAn impurity of type (e.g., n-type or p-type) is implanted into the exposed region of fin 74 in second region 50C. The mask may then be removed. Subsequently, another mask may be formed over the second region 50C while exposing the first region 50B, and an appropriate type of impurity may be implanted into the exposed region of the fin 74 in the first region 50B. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The LDD region 101 may have a thickness of from about 10 a¹⁵cm^-3To about 10¹⁶cm^-3the impurity concentration of (1). In some cases, annealing may be used to activate the implanted impurities.

In fig. 27A-27B, a gate spacer layer 106 is formed over the top surfaces of patterned mask layer 82, spacers 100, and fins 74 and also along the sidewalls of dummy gate 94 and patterned mask layer 82. The gate spacer layer 106 may be formed in a manner similar to the spacer layer 62 previously described. In an embodiment, the gate spacer layer 106 is formed of SiN using an ALD process. In fig. 28A-28B, a suitable etch process is performed to remove horizontal portions of the gate spacer layer 106. The horizontal portions of the gate spacer layer 106 may be removed in a manner similar to the method of removing the horizontal portions of the spacer layer 62. After the etching process, vertical portions of the gate spacer layer 106 remain along the sides of the dummy gate 94 and the patterned mask layer 82, and are referred to hereinafter as gate spacers 108.

In fig. 29A-29D, epitaxial source/drain regions 102 are formed in the fin 74 adjacent to the gate spacers 108. Epitaxial source/drain regions 102 are formed in fin 74 such that each dummy gate 94 is disposed between a respective adjacent pair of epitaxial source/drain regions 102. Epitaxial source/drain regions 102 may extend through LDD regions 101. Gate spacers 108 separate epitaxial source/drain regions 102 from the channel region of fin 74 (e.g., the portion covered by dummy gate 94) so that epitaxial source/drain regions 102 do not short to the channel region connected to fin 74. In some embodiments, epitaxial source/drain regions 102 may extend into fin 68.

Epitaxial source/drain regions 102 may be formed in the first region 50B by masking the second region 50C. The source/drain regions of fin 74 in first region 50B are then etched to form a recess. Epitaxial source/drain regions 102 are epitaxially grown in the recesses in the first region 50B. The epitaxial source/drain regions 102 may comprise any acceptable material, such as a material suitable for an n-type FinFET. For example, if fin 74 is silicon, epitaxial source/drain regions 102 may comprise silicon, SiC, SiCP, SiP, or the like. Subsequently, the mask on the second region 50C is removed.

Epitaxial source/drain regions 102 may be formed in the second region 50C by masking the first region 50B. The source/drain regions of fin 74 in second region 50C are then etched to form recesses. Epitaxial source/drain regions 102 are epitaxially grown in the recesses in the second region 50C. The epitaxial source/drain regions 102 may comprise any acceptable material, such as a material suitable for p-type finfets. For example, if fin 74 is silicon, epitaxial source/drain regions 102 may include SiGe, SiGeB, Ge, GeSn, or the like. Subsequently, the mask on the first region 50B is removed. In some embodiments, different processes may be used to form epitaxial source/drain regions 102.

Fig. 29C-29D show alternative configurations of the epitaxial source/drain regions 102. As shown, the epitaxial source/drain regions 102 may have surfaces that are raised from respective surfaces of the fins 74 and may have facets. In the embodiment shown in fig. 29C, the epitaxial source/drain regions 102 are separated. In the embodiment shown in fig. 29D, the epitaxial source/drain regions 102 merge. In some cases, epitaxial source/drain regions 102 may be separated at an initial stage of epitaxial growth and may or may not be merged during epitaxial growth to form merged epitaxial source/drain regions 102. In some cases, epitaxial source/drain regions 102 may be grown along portions of gate spacers 108 adjacent dummy gates 94.

The epitaxial source/drain regions 102 and/or the fins 74 may be implanted with dopants to form source/drain regions similar to the processes for forming lightly doped source/drain regions previously discussed with respect to fig. 26A-26B. In some cases, after implantationIs an anneal. The impurity concentration of the source/drain region may be about 10¹⁹cm^-3And about 10²¹cm^-3In the meantime. The n-type and/or p-type impurities for the source/drain regions may include suitable impurities as previously discussed. In some embodiments, after forming the gate spacers 108, the epitaxial source/drain regions 102 are implanted using the gate spacers 108 as a mask for the implantation. In some embodiments, epitaxial source/drain regions 102 are doped in-situ during growth.

In fig. 30A-30B, a Contact Etch Stop Layer (CESL)112 is formed over the patterned mask layer 82, spacers 100, epitaxial source/drain regions 102 and gate spacers 108 and also along the sidewalls of the dummy gate 94 and the patterned mask layer 82. CESL 112 may be formed in a manner similar to the method used to form spacer layer 62.

In fig. 31A to 31B, an interlayer dielectric (ILD)114 is formed over the structure shown in fig. 30A to 30B. ILD114 may be formed of a dielectric or semiconductor material and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. The semiconductor material may comprise amorphous silicon, silicon germanium (Si)_xGe_1-xWhere x is between 0 and 1), pure germanium, and the like. Other insulating or semiconducting materials formed by any acceptable process may be used.

In fig. 32A-32B, a planarization process such as CMP may be performed to make the top surface of ILD114 flush with the top surface of dummy gate 94. The planarization process may also remove portions of the patterned mask layer 82, spacers 100, gate spacers 108, or CESL 112 on the dummy gates 94 along the sidewalls of the patterned mask layer 82. After the planarization process, the top surfaces of the dummy gates 94, spacers 100, gate spacers 108, CESL 112, or ILD114 may be substantially flush. The top surface of dummy gate 94 may be exposed by ILD114 through a planarization process.

In fig. 33A-33B, the exposed portions of dummy gate 94 and the portions of dummy dielectric layer 76 directly under dummy gate 94 are removed in one or more etching steps to form recesses 116. In some embodiments, dummy gate 94 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process that selectively etches the dummy gate 94 without etching the ILD114 or the gate spacer 108. For example, in embodiments having polysilicon dummy gate 94, an etch process may selectively remove the polysilicon to form recess 116. Each recess 116 exposes a channel region of a respective fin 74. Each channel region is disposed between an adjacent pair of epitaxial source/drain regions 102. During removal, dummy dielectric layer 76 may serve as an etch stop layer when dummy gate 94 is etched. Dummy dielectric layer 76 may then be removed after removal of dummy gate 94.

In some embodiments, forming dummy gate 94 with a profile shape using the previously described techniques may result in recess 116 having a similar profile shape. For example, dummy gate 94 having a smaller intermediate width as shown in fig. 24A may produce a recess 116 having a smaller intermediate width, dummy gate 94 having a smaller bottom width as shown in fig. 24B may produce a recess 116 having a smaller bottom width, and dummy gate 94 having a larger intermediate width as shown in fig. 24C may produce a recess 116 having a larger intermediate width. These are examples, and the grooves 116 may have different profile shapes. The groove 116 may have first, second, and third widths at the positions of the width W1, the width W2, and the width W3 of the dummy gate 94, respectively. In some embodiments, the difference between the first width, the second width, and/or the third width may be between about 0% and about 20%.

In fig. 34A to 34B, a gate dielectric layer 118 and a gate filler 120 for a replacement gate are formed. A gate dielectric layer 118 is conformally deposited in the recess 116, such as on the top and sidewalls of the fin 74, on the sidewalls of the gate spacer 108, and on the top surface of the ILD 114. In some embodiments, the gate dielectric layer 118 is silicon oxide, silicon nitride, other materials, or multilayers thereof. In some embodiments, gate dielectric layer 118 is a high-k dielectric material, and in these embodiments, gate dielectric layer 118 may have a k value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 118 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like.

A gate fill 120 is deposited over gate dielectric layer 118 and fills the remaining portions of recess 116. The gate fill 120 may be a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof. After the formation of gate fill 120, a planarization process, such as CMP, may be performed to remove excess portions of the material of gate dielectric layer 118 and gate fill 120, which are located above the top surface of ILD 114. Thus, the material of the gate fill 120 and the resulting remaining portion of the gate dielectric layer 118 form the replacement gate of the resulting FinFET. The gate dielectric layer 118 and the gate filler 120 may be collectively referred to as a gate 121 or a gate stack 121.

The formation of the gate dielectric layer 118 in the first region 50B and the second region 50C may occur simultaneously such that the gate dielectric layer 118 in each region is formed of the same material, and the formation of each gate fill 120 may occur simultaneously such that the gate fill 120 in each region is formed of the same material. In some embodiments, the gate dielectric layer 118 in each region may be formed by a different process such that the gate dielectric layer 118 may be a different material, and the gate filler 120 in each region may be formed by a different process such that the gate filler 120 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate areas.

In some embodiments, forming dummy gate 94 with a profile shape using the techniques previously described may result in gate stack 121 with a similar profile shape. For example, dummy gate 94 with a smaller intermediate width as shown in fig. 24A may result in gate stack 121 with a smaller intermediate width, dummy gate 94 with a smaller bottom width as shown in fig. 24B may result in gate stack 121 with a smaller bottom width, and dummy gate 94 with a larger intermediate width as shown in fig. 24C may result in gate stack 121 with a larger intermediate width. These are examples, and gate stack 121 may have different profile shapes. The gate stack 121 may have first, second, and third widths at the positions of the width W1, the width W2, and the width W3 of the dummy gate 94, respectively. In some embodiments, the difference between the first width, the second width, and/or the third width may be between about 0% and about 10%. In some cases, the difference between the width W1, the width W2, and the width W3 of the dummy gate 94 may be different from the difference between the first width, the second width, and/or the third width of the subsequently formed gate stack 121. For example, the ratio between the third width and the second width of gate stack 121 may be greater than the ratio between width W3 and width W2 of previously formed dummy gate 94, but other differences between other widths of dummy gate 94 and gate stack 121 are possible. For example, width W3 may be between about 1% and about 15% less than width W2 of dummy gate 94, but subsequent gate stacks 121 may have a third width that is between about 1% and about 15% less than the second width. This is an example and other differences between widths are possible. In some cases, the profile or shape of gate stack 121 over fin 74 may be formed to be different than the profile or shape of gate stack 121 adjacent fin 74. In some cases, using an etching technique to control the profile shape of dummy gate 94 may improve the formation of gate dielectric layer 118 or gate fill 120. For example, a recess 116 having a shape similar to that of fig. 24B may allow for more complete filling of the recess 116 by the gate fill 120, or greater gap fill efficiency of the recess 116 by the gate fill 120. In this way, the likelihood of process defects associated with the gate fill 120 may be reduced, and thus, yield may be improved.

In fig. 35A-35B, a hard mask 122 is formed over the gate dielectric layer 118 and the gate fill 120. The hard mask 122 may provide protection for the gate spacers 108 during a subsequent self-aligned contact etch step to ensure that the self-aligned contacts do not short-circuit the gate fill 120 to the corresponding epitaxial source/drain regions 102. Hard mask 122 may be formed by recessing gate dielectric layer 118 and gate fill 120 in one or more etching steps. The etching step may comprise anisotropic dry etching. For example, the etching step may include a dry etching process using a reactive gas that selectively etches the gate dielectric layer 118 and the gate fill 120 without etching the gate spacer 108, CESL 112, or ILD 114. A hard mask 122 may be formed in the recesses and on the top surfaces of the gate spacers 108, CESL 112, and ILD 114. A planarization process, such as CMP, may then be performed to level the top surface of the hard mask 122 with the top surface of the ILD114, CESL 112, or gate spacer 108. The hard mask 122 may include one or more oxide (e.g., silicon oxide) and/or nitride (e.g., silicon nitride) layers and may be formed by CVD, PVD, ALD, Plasma Enhanced Atomic Layer Deposition (PEALD), spin-on dielectric processes, the like, or combinations thereof. In an embodiment, the hard mask 122 is SiN and is deposited with an ALD process.

In fig. 36A-36B, ILD 124 is deposited over ILD114 and hard mask 122. In an embodiment, ILD 124 is a flowable film formed by a flowable CVD process. In some embodiments, ILD 124 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD and PECVD.

In fig. 37A-37B, openings 126 and 128 for contacts are formed through ILD114, ILD 124, CESL 112, and hard mask 122. Openings 126 and 128 may be formed simultaneously or in separate processes. Openings 126 and 128 may be formed using acceptable photolithography and etching techniques. In an embodiment, opening 126 is formed before opening 128.

In fig. 38A to 38B, contacts 130 and 132 are formed in the openings 126 and 128. Liners, such as diffusion barriers, adhesion layers, etc., are formed in openings 126 and 128. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. Conductive material is formed in openings 126 and 128 above the pads. The conductive material may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, cobalt, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of ILD 124. The remaining liner and conductive material form contacts 130 and 132 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source/drain regions 102 and the contacts 130. Contact 130 is physically and electrically connected to epitaxial source/drain region 102, and contact 132 is physically and electrically connected to gate stack 121. Although the contacts 132 (e.g., gate contacts) are shown in the same cross-section as the contacts 130 (e.g., source/drain contacts), it should be understood that they may be disposed in different cross-sections. In some cases, forming the contacts in different cross-sections may help avoid shorting of contacts 130 and 132.