阅读说明：本技术 一种新型mis-hemt器件结构及其制备方法 (Novel MIS-HEMT device structure and preparation method thereof ) 是由 李迈克 于 2019-10-11 设计创作，主要内容包括：本发明提供一种新型MIS-HEMT器件结构,包括衬底,衬底的表面形成有1～2μm厚的缓冲层,缓冲层的表面形成有30～35nm厚的势垒层,势垒层的表面形成有图形化的源电极和漏电极,源电极和漏电极之间由沟道势垒层直接氧化生成有金属氧化物绝缘层,金属氧化物绝缘层与源漏电极下的势垒层表面平齐,并在金属氧化物绝缘层的表面形成有栅电极。本发明还提供一种前述新型MIS-HEMT器件结构制备方法。本申请在适当增加现有HEMT半导体器件中势垒层厚度基础上直接制备高质量金属氧化物绝缘层作为高K栅绝缘层,由此能够降低器件漏电流,提升器件性能稳定性,降低器件关键特性的恶化可能,制备方法在兼容现有HEMT器件制备流程前提下,只需增加一步氧化工艺即可成功实现器件制备。(The invention provides a novel MIS-HEMT device structure which comprises a substrate, wherein a buffer layer with the thickness of 1-2 microns is formed on the surface of the substrate, a barrier layer with the thickness of 30-35 nm is formed on the surface of the buffer layer, a patterned source electrode and a patterned drain electrode are formed on the surface of the barrier layer, a metal oxide insulating layer is generated between the source electrode and the drain electrode through direct oxidation of a channel barrier layer, the metal oxide insulating layer is flush with the surface of the barrier layer below the source electrode and the drain electrode, and a gate electrode is formed on the surface of the metal oxide insulating layer. The invention also provides a preparation method of the novel MIS-HEMT device structure. According to the method, the high-quality metal oxide insulating layer is directly prepared as the high-K gate insulating layer on the basis of properly increasing the thickness of the barrier layer in the conventional HEMT semiconductor device, so that the leakage current of the device can be reduced, the performance stability of the device is improved, and the possibility of deterioration of key characteristics of the device is reduced.)

1. The novel MIS-HEMT device structure is characterized by comprising a substrate, wherein a buffer layer with the thickness of 1-2 microns is formed on the surface of the substrate, a barrier layer with the thickness of 30-35 nm is formed on the surface of the buffer layer, a patterned source electrode and a patterned drain electrode are formed on the surface of the barrier layer, a metal oxide insulating layer is generated between the source electrode and the drain electrode through direct oxidation of a channel barrier layer, the metal oxide insulating layer is flush with the surface of the barrier layer below the source electrode and the drain electrode, and a gate electrode is formed on the surface of the metal oxide insulating layer.

2. the novel MIS-HEMT device structure of claim 1, wherein the substrate is of Si, SiC or sapphire.

3. The novel MIS-HEMT device structure of claim 1, wherein said buffer layer is undoped GaAs or undoped GaN.

4. The novel MIS-HEMT device structure of claim 1, wherein said barrier layer is AlGaAs or AlGaN.

5. the novel MIS-HEMT device structure of claim 1, wherein the thickness of the metal oxide insulating layer is 3-5 nm.

6. The novel MIS-HEMT device structure of claim 1, wherein said source and drain electrodes are of Ni/Au/Ge/Ni/Au multilayer metal structure and said gate electrode is of Ni/Au, Ni/Ti/Au or Ti/Au metal stack structure.

7. a method of fabricating a novel MIS-HEMT device structure according to any of claims 1-6, wherein the method comprises the steps of:

S1, sequentially laminating a buffer layer single crystal film with the thickness of 1-2 microns and a barrier layer single crystal film with the thickness of 30-35 nm on the surface of the substrate by using MOCVD;

S2, obtaining the graphical buffer layer and barrier layer films by photoetching the buffer layer single crystal film and the barrier layer single crystal film;

S3, depositing multiple layers of metal on the surface of the barrier layer film through magnetron sputtering or electron beam evaporation, and obtaining a patterned source electrode and a patterned drain electrode through a photoetching process;

S4, firstly, preliminarily oxidizing the barrier layer which is not protected by the source electrode and the drain electrode by an O ₂ plasma or ultraviolet irradiation method, then annealing at the high temperature of 450-500 ℃ in an O ₂ atmosphere, further oxidizing the barrier layer to generate a high-quality metal oxide insulating layer serving as a gate insulating layer, wherein the surface of the metal oxide insulating layer is flush with the surface of the barrier layer below the source electrode and the drain electrode;

and S5, obtaining a patterned metal gate electrode on the surface of the metal oxide insulating layer through a stripping process.

8. The method of claim 7, wherein in step S1, the buffer layer is made of undoped GaAs, and the barrier layer is made of AlGaAs; or the buffer layer is made of undoped GaN, and the barrier layer is made of AlGaN.

9. The method of claim 7, wherein in step S3, the deposited multilayer metal on the barrier layer film surface is Ni/Au/Ge/Ni/Au, and the metal layer thickness is 20nm/100nm/26nm/26nm/100nm in sequence.

10. The method of claim 7, wherein in step S5, the metal stack structure of the gate electrode is Ni/Au, Ni/Ti/Au or Ti/Au.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a novel MIS-HEMT device structure and a preparation method thereof.

background

A compound HEMT (High Electron Mobility Transistor) semiconductor device mainly based on GaAs and GaN has the advantages of ultrahigh frequency, High power and the like, and has a wide application prospect in the fields of wireless 5G communication, radar and the like at present. However, the leakage problem of the HEMT device of the conventional schottky gate is serious, and the critical performance of the device, such as breakdown voltage, efficiency, gain and the like, is easily deteriorated. In order to effectively suppress the gate current, the metal-insulator-semiconductor (MIS) structure is introduced into the gate of the traditional compound HEMT structure to form a MIS-HEMT device, which is an effective solution. However, the inventor of the present invention has found through research that the existing manufacturing process for forming a metal-insulator-semiconductor (MIS) HEMT device by introducing a MIS structure is complicated, and therefore how to effectively manufacture a high-K gate insulating layer becomes the focus of the technology.

Disclosure of Invention

Aiming at the technical problem that in the prior art, in order to effectively inhibit the grid current of a compound HEMT device, a metal-insulator-semiconductor (MIS) structure is introduced to form the MIS-HEMT device, but the MIS structure is used for forming the MIS-HEMT device, so that the device preparation process is complicated, the invention provides a novel MIS-HEMT device structure.

In order to solve the technical problems, the invention adopts the following technical scheme:

a novel MIS-HEMT device structure comprises a substrate, wherein a buffer layer with the thickness of 1-2 microns is formed on the surface of the substrate, a barrier layer with the thickness of 30-35 nm is formed on the surface of the buffer layer, a patterned source electrode and a patterned drain electrode are formed on the surface of the barrier layer, a metal oxide insulating layer is generated between the source electrode and the drain electrode through direct oxidation of the channel barrier layer, the metal oxide insulating layer is flush with the surface of the barrier layer below the source electrode and the drain electrode, and a gate electrode is formed on the surface of the metal oxide insulating layer.

Further, the substrate is made of Si, SiC or sapphire.

Furthermore, the buffer layer is made of undoped GaAs or undoped GaN.

further, the barrier layer is made of AlGaAs or AlGaN.

Further, the thickness of the metal oxide insulating layer is 3-5 nm.

Furthermore, the source electrode and the drain electrode adopt a Ni/Au/Ge/Ni/Au multilayer metal structure, and the gate electrode adopts a Ni/Au, Ni/Ti/Au or Ti/Au metal laminated structure.

The invention also provides a preparation method of the novel MIS-HEMT device structure, which comprises the following steps:

S1, sequentially laminating a buffer layer single crystal film with the thickness of 1-2 microns and a barrier layer single crystal film with the thickness of 30-35 nm on the surface of the substrate by using MOCVD;

s2, obtaining the graphical buffer layer and barrier layer films by photoetching the buffer layer single crystal film and the barrier layer single crystal film;

S3, depositing multiple layers of metal on the surface of the barrier layer film through magnetron sputtering or electron beam evaporation, and obtaining a patterned source electrode and a patterned drain electrode through a photoetching process;

s4, firstly, preliminarily oxidizing the barrier layer which is not protected by the source electrode and the drain electrode by an O ₂ plasma or ultraviolet irradiation method, then annealing at the high temperature of 450-500 ℃ in an O ₂ atmosphere, further oxidizing the barrier layer to generate a high-quality metal oxide insulating layer serving as a gate insulating layer, wherein the surface of the metal oxide insulating layer is flush with the surface of the barrier layer below the source electrode and the drain electrode;

And S5, obtaining a patterned metal gate electrode on the surface of the metal oxide insulating layer through a stripping process.

further, in step S1, the buffer layer is made of undoped GaAs, and the barrier layer is made of AlGaAs; or the buffer layer is made of undoped GaN, and the barrier layer is made of AlGaN.

Furthermore, in the step S3, the multilayer metal deposited on the surface of the barrier layer film is Ni/Au/Ge/Ni/Au, and the thicknesses of the metal layers are 20nm/100nm/26nm/26nm/100nm in sequence.

Further, in step S5, the metal stack structure of the gate electrode is Ni/Au, Ni/Ti/Au, or Ti/Au.

Compared with the prior art, the novel MIS-HEMT device structure and the preparation method thereof provided by the invention have the following technical advantages:

1. According to the novel MIS-HEMT device structure, the high-quality metal oxide insulating layer is directly prepared on the basis of properly increasing the thickness of the barrier layer in the conventional HEMT semiconductor device by 2-5 nm, and the metal oxide insulating layer is used as a high-K gate insulating layer or a gate oxide layer, so that the leakage current of the MIS-HEMT device can be reduced;

2. On the premise of being compatible with the existing HEMT device preparation process, the novel MIS-HEMT device structure preparation method can successfully realize the preparation of the novel MIS-HEMT device structure only by adding the oxidation process in the step S4, and compared with the existing MIS structure forming MIS-HEMT device, the MIS-HEMT device preparation process is simplified;

3. only one step of oxidation process is needed, so that the leakage current of the MIS-HEMT device can be reduced, the performance stability of the device is improved, and the possibility of deterioration of the key characteristics of the device is reduced on the premise that the cost is hardly increased.

Drawings

Fig. 1 is a schematic structural diagram of the novel MIS-HEMT device provided by the present invention.

Fig. 2a to 2d are schematic cross-sectional structure diagrams of the novel MIS-HEMT device structure preparation method provided by the present invention at each flow stage.

in the figure, 1, a substrate; 2. a buffer layer; 3. a barrier layer; 4. a source electrode; 5. a drain electrode; 6. a metal oxide insulating layer; 7. and a gate electrode.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.

In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

Referring to fig. 1, the present invention provides a novel MIS-HEMT device structure, including a substrate 1, a buffer layer 2 with a thickness of 1-2 μm is formed on a surface of the substrate 1, a barrier layer 3 with a thickness of 30-35 nm is formed on a surface of the buffer layer 2, a patterned source electrode 4 and a patterned drain electrode 5 are formed on a surface of the barrier layer 3, a metal oxide insulating layer 6 is generated between the source electrode 4 and the drain electrode 5 by directly oxidizing a channel barrier layer, and the metal oxide insulating layer 6 is flush with surfaces of the barrier layer 3 under the source electrode 4 and the drain electrode 5, that is, the metal oxide insulating layer 6 is embedded on a surface of the barrier layer 3, and a gate electrode 7 is formed on a surface of the metal oxide insulating layer 6.

as a specific example, the substrate 1 is made of conventional Si, SiC or sapphire.

In a specific embodiment, the buffer layer 2 is made of conventional undoped GaAs or undoped GaN.

in a specific embodiment, the barrier layer 3 is made of conventional AlGaAs or AlGaN.

as a specific embodiment, the thickness of the metal oxide insulating layer 6 is 3-5 nm, so that the leakage current of the device can be effectively reduced.

In a specific embodiment, the source electrode 4 and the drain electrode 5 are of a multilayer metal structure of Ni/Au/Ge/Ni/Au, that is, the source electrode 4 and the drain electrode 5 are of a stacked structure of Ni/Au/Ge/Ni/Au, and the gate electrode 7 is of a stacked structure of Ni/Au, Ni/Ti/Au or Ti/Au.

the invention also provides a preparation method of the novel MIS-HEMT device structure, which comprises the following steps:

S1, as shown in figure 2a, sequentially laminating a buffer layer 2 single crystal film with the thickness of 1-2 mu m and a barrier layer 3 single crystal film with the thickness of 30-35 nm on the surface of a substrate 1 by using MOCVD; among them, the MOCVD (Metal Organic Chemical vapor deposition) is a prior art well known to those skilled in the art;

S2, obtaining the graphical buffer layer and barrier layer films by photoetching the buffer layer 2 single crystal film and the barrier layer 3 single crystal film; wherein the photolithography process is a prior art in the manufacturing process of semiconductor devices;

S3, as shown in FIG. 2b, depositing a plurality of layers of metal on the surface of the barrier layer film through magnetron sputtering or electron beam evaporation, and obtaining a patterned source electrode 4 and a patterned drain electrode 5 through a photoetching process; magnetron sputtering or electron beam evaporation is one of the prior art of physical vapor deposition;

s4, as shown in figure 2c, firstly, the barrier layer 3 which is not protected by the source electrode 4 and the drain electrode 5 is primarily oxidized by an O ₂ plasma or ultraviolet irradiation method, then, the barrier layer 3 is further oxidized to generate a high-quality metal oxide insulating layer 6 by annealing at a high temperature of 450-500 ℃ in an O ₂ atmosphere, and the metal oxide insulating layer 6 is used as a high-K gate insulating layer, wherein the surface of the metal oxide insulating layer 6 is flush with the surface of the barrier layer 3 under the source electrode 4 and the drain electrode 5, namely, the metal oxide insulating layer 6 is directly oxidized and generated on the barrier layer 3;

S5, as shown in fig. 2d, obtaining the patterned metal gate electrode 7 on the surface of the metal oxide insulating layer 6 by lift-off process, wherein the lift-off process is the prior art in the semiconductor device manufacturing process.

As a specific example, in step S1, the buffer layer 2 is made of conventional undoped GaAs, and the barrier layer 3 is made of conventional AlGaAs; or, the buffer layer 2 is made of existing undoped GaN, and the barrier layer 3 is made of existing AlGaN, so that two device structures with different schemes can be obtained. Of course, other materials can be adopted by those skilled in the art on the basis of the above.

As a specific example, in step S3, the multilayer metal deposited on the surface of the barrier layer film is Ni/Au/Ge/Ni/Au, and the thicknesses of the metal layers are 20nm/100nm/26nm/26nm/100nm in sequence, so that the source electrode 4 and the drain electrode 5 with the multilayer metal laminated structure can be obtained.

As a specific example, in step S5, the metal laminated structure of the gate electrode 7 is Ni/Au, Ni/Ti/Au, or Ti/Au, so that the gate electrode 7 with the metal laminated structure can be obtained.

Compared with the prior art, the novel MIS-HEMT device structure and the preparation method thereof provided by the invention have the following technical advantages:

1. according to the novel MIS-HEMT device structure, the high-quality metal oxide insulating layer is directly prepared on the basis of properly increasing the thickness of the barrier layer in the conventional HEMT semiconductor device by 2-5 nm, and the metal oxide insulating layer is used as a high-K gate insulating layer or a gate oxide layer, so that the leakage current of the MIS-HEMT device can be reduced;

2. On the premise of being compatible with the existing HEMT device preparation process, the novel MIS-HEMT device structure preparation method can successfully realize the preparation of the novel MIS-HEMT device structure only by adding the oxidation process in the step S4, and compared with the existing MIS structure forming MIS-HEMT device, the MIS-HEMT device preparation process is simplified;

3. Only one step of oxidation process is needed, so that the leakage current of the MIS-HEMT device can be reduced, the performance stability of the device is improved, and the possibility of deterioration of the key characteristics of the device is reduced on the premise that the cost is hardly increased.

finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.