阅读说明：本技术 半导体器件和制造半导体器件的方法 (semiconductor device and method of manufacturing semiconductor device ) 是由 李宜静 杨宗熺 游明华 于 2018-10-08 设计创作，主要内容包括：本公开涉及半导体器件和制造半导体器件的方法。实施例是一种包括下列项的器件,包括：第一鳍,从衬底延伸；第一栅极堆叠,在第一鳍上方并且沿着第一鳍的侧壁；第一栅极间隔件,沿第一栅极堆叠的侧壁被布置；以及第一外延源极/漏极区域,在第一鳍中并且与第一栅极间隔件相邻。第一外延源极/漏极区域包括：第一外延层,在第一鳍上,第一外延层包括硅和碳；第二外延层,在第一外延层上,第二外延层具有与第一外延层不同的材料成分,第一外延层将第二外延层和第一鳍分离；以及第三外延层,在第二外延层上,并且第三外延层具有与第一外延层不同的材料成分。(The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. An embodiment is a device comprising: a first fin extending from the substrate; a first gate stack over the first fin and along sidewalls of the first fin; a first gate spacer disposed along a sidewall of the first gate stack; and a first epitaxial source/drain region in the first fin and adjacent to the first gate spacer. The first epitaxial source/drain region includes: a first epitaxial layer on the first fin, the first epitaxial layer comprising silicon and carbon; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin; and a third epitaxial layer on the second epitaxial layer, and the third epitaxial layer having a different material composition from the first epitaxial layer.)

1. A semiconductor device, comprising:

A first fin extending from a substrate;

A first gate stack over the first fin and along sidewalls of the first fin;

A first gate spacer disposed along a sidewall of the first gate stack; and

A first epitaxial source/drain region in the first fin and adjacent to the first gate spacer, the first epitaxial source/drain region comprising:

A first epitaxial layer on the first fin, the first epitaxial layer comprising silicon and carbon;

A second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer and the first fin; and

A third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

2. The device of claim 1 wherein the first epitaxial layer has a uniform thickness on the sides and bottom of the first epitaxial source/drain region.

3. the device of claim 1 wherein the first epitaxial layer is thicker at the bottom of the first epitaxial source/drain region than at the sides of the first epitaxial source/drain region.

4. The device of claim 1, wherein the first epitaxial layer has an atomic concentration of carbon in a range from 0.2% to 5%.

5. The device of claim 1, wherein the second epitaxial layer has a faceted top surface, and wherein the third epitaxial layer has a uniform thickness over the faceted top surface of the second epitaxial layer.

6. The device of claim 1, wherein the third epitaxial layer contacts the first epitaxial layer and the first gate spacer.

7. The device of claim 1, further comprising:

A second fin extending from the substrate;

A second gate stack over the second fin and along sidewalls of the second fin;

A second gate spacer disposed along a sidewall of the second gate stack; and

A second epitaxial source/drain region in the second fin and adjacent to the second gate spacer, the second epitaxial source/drain region having a different material composition than the first epitaxial source/drain region.

8. The device of claim 1 wherein the first epitaxial source/drain region extends below the first gate spacer.

9. A method of manufacturing a semiconductor device, comprising:

Depositing a first dummy gate over a first fin extending upward from a substrate and along sidewalls of the first fin;

forming first gate spacers along sidewalls of the first dummy gate;

Forming a first recess in the first fin adjacent to the first gate spacer; and

Forming a first source/drain region in the first recess, the forming a first source/drain region comprising:

Epitaxially growing a first layer in the first recess, the first layer comprising silicon and carbon;

Epitaxially growing a second layer on the first layer, the second layer having a different material composition than the first layer, the first layer separating the second layer from the first fin; and is

epitaxially growing a third layer on the second layer, the third layer having a different material composition than the first layer.

10. A method of manufacturing a semiconductor device, comprising:

forming a first dummy gate over a first fin extending upward from a substrate and along sidewalls of the first fin;

Forming first gate spacers along sidewalls of the first dummy gate;

Anisotropically etching a first recess in the first fin adjacent to the first gate spacer;

Epitaxially growing a first source/drain region in the first recess, the first source/drain region comprising a first epitaxial carbon-containing layer, a second epitaxial layer and a third epitaxial layer, the first epitaxial layer carbon-containing layer in line with the first recess, the second epitaxial layer on the first epitaxial carbon-containing layer, the second epitaxial layer having a different material composition than the first epitaxial carbon-containing layer and the third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial carbon-containing layer; and is

replacing the first dummy gate with a functional gate stack disposed over the first fin and along sidewalls of the first fin.

Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric, conductive, and semiconductor materials on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually decreasing the minimum feature size, which allows more components to be integrated in a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device including: a first fin extending from a substrate; a first gate stack over the first fin and along sidewalls of the first fin; a first gate spacer disposed along a sidewall of the first gate stack; and a first epitaxial source/drain region in the first fin and adjacent to the first gate spacer, the first epitaxial source/drain region comprising: a first epitaxial layer on the first fin, the first epitaxial layer comprising silicon and carbon; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer and the first fin; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

Embodiments of the present disclosure also provide a method of manufacturing a semiconductor device, including: depositing a first dummy gate over a first fin extending upward from a substrate and along sidewalls of the first fin; forming first gate spacers along sidewalls of the first dummy gate; forming a first recess in the first fin adjacent to the first gate spacer; and forming a first source/drain region in the first recess, the forming the first source/drain region comprising: epitaxially growing a first layer in the first recess, the first layer comprising silicon and carbon; epitaxially growing a second layer on the first layer, the second layer having a different material composition than the first layer, the first layer separating the second layer from the first fin; and epitaxially growing a third layer on the second layer, the third layer having a different material composition than the first layer.

Embodiments of the present disclosure also provide a method of manufacturing a semiconductor device, including: forming a first dummy gate over a first fin extending upward from a substrate and along sidewalls of the first fin; forming first gate spacers along sidewalls of the first dummy gate; anisotropically etching a first recess in the first fin adjacent to the first gate spacer; epitaxially growing a first source/drain region in the first recess, the first source/drain region comprising a first epitaxial carbon-containing layer, a second epitaxial layer and a third epitaxial layer, the first epitaxial carbon-containing layer in line with the first recess, the second epitaxial layer on the first epitaxial carbon-containing layer, the second epitaxial layer having a different material composition than the first epitaxial carbon-containing layer and the third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial carbon-containing layer; and replacing the first dummy gate with a functional gate stack disposed over and along sidewalls of the first fin.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments.

Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 12C, 13, 14, 15, 16, 17, 18, 19, 20, 21, and 22 are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments.

fig. 23 and 24 are cross-sectional views of an intermediate stage in the fabrication of a FinFET according to some embodiments.

Fig. 25, 26, 27, and 28 are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

fin field effect transistors (finfets) and methods of forming the same are provided according to various embodiments. An intermediate stage of forming the FinFET is shown. Some embodiments discussed herein are discussed in the context of finfets formed using a gate-last (sometimes referred to as a replacement gate process) process. In other embodiments, a gate-first (gate-first) process may be used. Some variations of the embodiments are discussed. Further, some embodiments contemplate aspects for use in planar devices such as planar FETs. Those of ordinary skill in the art will readily appreciate other modifications that may be contemplated within the scope of other embodiments. Although method embodiments are discussed in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein.

Before specifically addressing the illustrated embodiments, certain advantageous features and aspects of the disclosed embodiments will be addressed generally. In general, the present disclosure is a semiconductor device and method of forming the same for improving reliability of a FinFET device by widening a process window for a dummy gate removal process. In conventional finfets, defects or breaks in the sidewall spacers may allow the etchant used during the removal of the dummy gate to attack and damage the source/drain regions. In disclosed embodiments, the source/drain regions include an outer layer having a low etch rate relative to an etchant used during removal of the dummy gate to protect the source/drain regions from attack and damage during the dummy gate removal process. For example, if there is a defect or break in the gate seal spacer and/or the gate spacer, an outer layer having a low etch rate relative to the etchant used will protect the source/drain regions from attack and damage the source/drain regions during the dummy gate removal process. If the source/drain regions are damaged during the dummy gate removal process, the subsequent formation of the replacement gate may allow the metal of the replacement gate to extrude through the defects in the spacers and into the damaged regions of the source/drain regions. This extruded gate portion may short the gate to the source/drain regions and render the device inoperative. Furthermore, the epitaxial profile of the source/drain regions can be controlled by the disclosed embodiments. The disclosed processes and structures may improve reliability and yield of FinFET devices.

Some embodiments contemplate n-type devices (e.g., n-type finfets) and p-type devices (e.g., p-type finfets) fabricated during the fabrication process. Thus, some embodiments contemplate forming complementary devices. The following figures may show one device, but one of ordinary skill in the art will readily appreciate that multiple devices, some of which have different device types, may be formed during the process. Some aspects of the formation of complementary devices are discussed below, but these aspects are not necessarily shown in the figures.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments. The FinFET includes a fin 58 on the substrate 50. Isolation regions 56 are formed on substrate 50, and fins 58 protrude on adjacent isolation regions 56 and between adjacent isolation regions 56. A gate dielectric layer 102 is along the sidewalls and over the top surface of fin 58, and a gate electrode 106 is over gate dielectric layer 102. Source/drain regions 86 are disposed on opposite sides of fin 58 relative to gate dielectric layer 102 and gate electrode 106. Fig. 1 further shows a reference cross section used in the following figures. Cross section a-a spans the cross section of the channel, gate dielectric layer 102, and gate electrode 106 of the FinFET. Cross section B-B is perpendicular to cross section a-a and is along the longitudinal axis of fin 58 and in the direction of current flow, for example, between source/drain regions 86. Cross section C-C is parallel to cross section B-B and extends through the source/drain regions of the FinFET. For clarity, the following figures refer to these reference cross sections.

Fig. 2-6 are cross-sectional views of intermediate stages in fabrication of a FinFET according to some embodiments. Fig. 2-6 are shown along the reference cross-section a-a shown in fig. 1, except for a plurality of fins/finfets.

In fig. 2, a fin 52 is formed in a substrate 50. The substrate 50 may be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.

the substrate 50 has a region 50B and a region 50C. Region 50B may be used to form an n-type device, e.g., an NMOS transistor such as an n-type FinFET. Region 50C may be used to form a p-type device, e.g., a PMOS transistor such as a p-type FinFET. Region 50B may be physically separated from region 50C (as shown by the spacers), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 50B and region 50C. In some embodiments, both regions 50B and 50C are used to form the same type of device, e.g., both regions are used for either an n-type device or a p-type device.

Fin 52 is a semiconductor strip. In some embodiments, the fin 52 may be formed in the substrate 50 by etching a trench in the substrate 50. The etch may be any acceptable etch process, such as, for example, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be anisotropic.

In fig. 3, an insulating material 54 is formed over substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (fcvd) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, insulative material 54 is formed such that excess insulative material 54 covers fin 52.

In fig. 4, a planarization process is applied to insulating material 54. In some embodiments, the planarization process includes a Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like. The planarization process exposes the fins 52. The top surfaces of fin 52 and insulating material 54 are horizontal after the planarization process is complete.

In fig. 5, insulating material 54 is recessed to form Shallow Trench Isolation (STI) regions 56. The insulating material 54 is recessed so that the fins 58 in regions 50B and 50C protrude from between adjacent STI regions 56. Further, the top surface of the STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., a dished surface), or a combination thereof as shown. The top surface of STI regions 56 may be formed flat, convex, and/or concave by appropriate etching. STI regions 56 may be recessed using an acceptable etch process (e.g., a process selective to the material of insulating material 54). For example, useChemical oxides that can be removed by etching or applying the material SICONI tool or dilute hydrofluoric acid (dHF) acid can be used.

Those of ordinary skill in the art will readily appreciate that the process described with respect to fig. 2-5 is but one example of how the fin 58 may be formed. In some embodiments, a dielectric layer may be formed over the top surface of substrate 50; the trench may be etched through the dielectric layer; the homoepitaxial structure can be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, fins 52 in fig. 4 may be recessed and a different material than fins 52 may be epitaxially grown in their locations. In yet another embodiment, a dielectric layer may be formed over the top surface of the substrate 50; the trench may be etched through the dielectric layer; the heteroepitaxial structure may be epitaxially grown in the trench using a different material than the substrate 50; and the dielectric layer may be recessed to enable a heteroepitaxial junctionThe structures protrude from the dielectric layer to form fins 58. In some embodiments where a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the growth material may be doped in situ during growth, which may avoid pre-and post-implantation, but in-situ doping and implant doping may be used together. Further, it may be advantageous to epitaxially grow a material in the NMOS region that is different from the material in the PMOS region. In various embodiments, fin 58 may be formed of silicon germanium (Si)_xGe_1-xWhere x may be in the range of 0to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, and the like. For example, materials that may be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

In addition, appropriate doped regions (not shown, sometimes referred to as well regions) may be formed in fin 58, fin 52, and/or substrate 50. In some embodiments, a P-type doped region may be formed in region 50B and an N-type doped region may be formed in region 50C. In some embodiments, only P-type doped regions or only N-type doped regions are formed in both region 50B and region 50C.

In embodiments with different types of doped regions, the different implantation steps for regions 50B and 50C may be accomplished using a photoresist or other mask (not shown). For example, a photoresist may be formed over fin 58 and STI region 56 in region 50B. The photoresist is patterned to expose regions 50C of substrate 50, e.g., PMOS regions. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the region 50C, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into the region 50B, e.g., NMOS region. The n-type impurity may be 10 or less¹⁸cm^-3(e.g., at about 10)¹⁷cm^-3And about 10¹⁸cm^-3In between) phosphorus, arsenic, etc. implanted into the region. After implantation, e.g. by an acceptable ashing processThe photoresist is removed. After implanting region 50C, a photoresist is formed over fin 58 and STI region 56 in region 50C. The photoresist is patterned to expose regions 50B of the substrate 50, e.g., NMOS regions. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in region 50B, and the photoresist may be used as a mask to substantially prevent p-type impurities from being implanted into region 50C, e.g., a PMOS region. The p-type impurity may be 10 or less¹⁸cm^-3(e.g., at about 10)¹⁷cm^-3And about 10¹⁸cm^-3In between) boron, BF, the concentration of which is implanted into the region₂And the like. After implantation, the photoresist may be removed, for example, by an acceptable ashing process. After implanting the regions 50B and 50C, an anneal may be performed to activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in-situ during growth, which may avoid implantation, but in-situ doping and implant doping may be used together.

In fig. 6, a dummy dielectric layer 60 is formed over fin 58. Dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. Dummy gate layer 62 may be deposited over dummy dielectric layer 60 and then planarized, for example by CMP. The dummy gate layer 62 may be a conductive material and may be selected from the group consisting of polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polycrystalline silicon. The dummy gate layer 62 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. The dummy gate layer 62 may be made of other materials having a high etch selectivity for the etching of the isolation region. The mask layer 64 may comprise, for example, SiN, SiON, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50B and region 50C. In some embodiments, separate dummy gate layers may be formed in region 50B and region 50C, and separate mask layers may be formed in region 50B and region 50C.

Fig. 7-24 are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments. Fig. 7-12A and fig. 13-24 are shown along reference cross-section B-B shown in fig. 1, except for a plurality of fins/finfets. Fig. 12B-12C are shown along the reference cross-section C-C shown in fig. 1, except for a plurality of fins/finfets.

Fig. 7-12A and 13-24 illustrate region 50B and region 50C of one or more fins 58. Regions 50B and 50C may be in the same fin 58 or different fins 58. Devices in different regions 50B and 50C may be formed to have different threshold voltages.

In fig. 7, mask layer 64 is patterned using acceptable photolithography and etching techniques to form mask 74. The pattern of mask 74 may then be transferred to dummy gate layer 62 and dummy dielectric layer 60 by acceptable etch techniques to form dummy gate 72 and dummy gate dielectric layer 70, respectively. Dummy gate 72 and dummy gate dielectric layer 70 cover the respective channel regions of fin 58. The pattern of the mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a length direction substantially perpendicular to a length direction of the corresponding epitaxial fin.

In fig. 8, gate seal spacers 80 may be formed on the exposed surfaces of the dummy gate 72 and/or the fin 58. Thermal oxidation or deposition followed by anisotropic etching may form the gate seal spacers 80. In some embodiments, the gate seal spacers may be formed of a nitride, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. The gate seal spacers 80 seal the sidewalls of the subsequently formed gate stack and may serve as additional gate spacers.

in addition, an implant for lightly doped source/drain (LDD) regions 82 may be performed. In embodiments with different device types, classSimilar to the implantation discussed above in fig. 5, a mask (e.g., photoresist) may be formed over region 50B while exposing region 50C, and an appropriate type (e.g., n-type or p-type) of impurity may be implanted into exposed fin 58 in region 50C. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50C while exposing region 50B, and an appropriate type of impurity may be implanted into exposed fin 58 in region 50B. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a thickness of from about 10¹⁵cm^-3To about 10¹⁶cm^-3The impurity concentration of (1). Annealing may be used to activate the implanted impurities.

Further, gate spacers 84 are formed on the gate seal spacers 80 along the sidewalls of the dummy gate 72 and over the LDD regions 82. The gate spacers 84 may be formed by conformally depositing a material and then anisotropically etching the material. The material of the gate spacer 84 may be silicon nitride, SiCN, combinations thereof, or the like. The etch may be selective to the material of the gate spacer 84 material so that the LDD regions 82 are not etched during the formation of the gate spacer 84.

In fig. 9, 10, 11, 12A, 12B and 12C, epitaxial source/drain regions 86 are formed in fin 58 in first region 50B. Epitaxial source/drain regions 86 are formed in fin 58 such that each dummy gate 72 is disposed between a respective adjacent pair of epitaxial source/drain regions 86. In some embodiments, the epitaxial source/drain regions 86 may extend through the LDD regions 82. In some embodiments, the gate seal spacers 80 and the gate spacers 84 are used to separate the epitaxial source/drain regions 86 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source/drain regions 86 do not short the gates of the subsequently formed resulting FinFET.

During formation of epitaxial source/drain regions 86 in region 50B (e.g., NMOS region), region 50C (e.g., PMOS region) may be masked by mask 83. Referring first to fig. 9, a patterning process is performed on fin 58To form recesses 85 in the source/drain regions of fin 58. The patterning process may be performed in a manner to form a recess 85 between adjacent dummy gate stacks 72 (in the interior region of the fin 58), or between the isolation region 56 and an adjacent dummy gate stack 72 (in the end region of the fin 58). In some embodiments, the patterning process may include an appropriate anisotropic dry etch process while using the dummy gate stack 72, the gate spacers 84, and/or the isolation regions 54 as a combinatorial mask. Suitable anisotropic dry etching processes may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. In some embodiments in which RIE is used in the first patterning process, the process parameters (e.g., process gas mixture, voltage bias, and RF power) may be selected such that etching is performed primarily using physical etching (e.g., ion bombardment) rather than chemical etching (e.g., radical etching by chemical reaction). In some embodiments, the voltage bias may be increased to increase the energy of the ions used in the ion bombardment process and thereby increase the rate of physical etching. Since physical etching is anisotropic in nature and chemical etching is isotropic in nature, the etch rate of such an etch process is greater in the vertical direction than in the lateral direction. In some embodiments, inclusion of a CH may be used₃F、CH₄、HBr、O₂Ar, combinations thereof, and the like. In some embodiments, the patterning process forms a groove 85 having a U-shaped bottom surface. The groove 85 may also be referred to as a U-shaped groove 85, an example groove 85 of which is shown in fig. 9.

In fig. 10, 11 and 12A, epitaxial source/drain regions 86 in region 50B are epitaxially grown in the recesses. In fig. 10, a first layer 86A of epitaxial source/drain regions 86 is formed in region 50B. The first layer 86A may comprise SiC, SiCP, the like, or combinations thereof. The first layer 86A may be epitaxially grown to be in line with the groove 85. The epitaxial process may be performed by introducing a silicon precursor (e.g., Silane (SiH)) to the fin 58 in the recess 85₄) Dichlorosilane (DCS) (SiH)₄Cl₂) Or a combination thereof) and a carbon precursor (C)For example, methylsilane (CSiH)₆) To begin with). In an embodiment, the silicon precursor is introduced at a flow rate of from about 400sccm to about 1200sccm (e.g., about 850sccm), and the carbon precursor is introduced at a flow rate of from about 40sccm to about 100sccm (e.g., about 70 sccm). Further, the deposition can be performed at a temperature of from about 630 ℃ to about 710 ℃ (e.g., about 700 ℃) and a pressure of between about 100Torr and about 300Torr (e.g., about 200 Torr). The first layer 86A may be formed to have an atomic concentration of carbon in a range from about 0.2% to about 5% (e.g., about 3%). An atomic concentration of carbon higher than 5% may increase the source/drain resistance, which may negatively affect the device performance. This first layer 86A (e.g., SiC and/or SiCP) in region 50B has a low etch rate relative to the etchant used during removal of dummy gate 72 and may help protect source/drain regions 86 from attack and damage during the dummy gate removal process.

in fig. 11, a second layer 86B of epitaxial source/drain regions 86 is formed in region 50B. The second layer 86B may include SiP, SiCP, the like, or combinations thereof. A second layer 86B may be epitaxially grown on the first layer 86A to fill the remaining portion of the recess 85. The second layer 86B of the epitaxial source/drain regions 86 in the region 50B may have surfaces that are raised from respective surfaces of the fin 58 and may have facets. The second layer 86B may have a thickness of about 10 a¹⁹cm^-3And about 10²¹cm^-3Impurity concentration of phosphorus in between.

In fig. 12A, a cap layer 86C of epitaxial source/drain regions 86 is formed in region 50B. The cap layer 86C may include SiP or the like. The capping layer 86C may be epitaxially grown on the second layer 86B and may cover any exposed portions of the second layer 86B and the first layer 86A. The cap layer 86C may have a substantially uniform thickness over the facets of the second layer 86B. In some embodiments, the capping layer 86B has an impurity concentration of phosphorus that is lower than an impurity concentration of phosphorus in the second layer 86B. In some embodiments, the capping layer 86B has an impurity concentration of phosphorus that is higher than an impurity concentration of phosphorus in the second layer 86B.

As shown in fig. 12A, the first layer 86A has a thickness T1 at the side walls of the groove 85 and a thickness T2 at the bottom of the groove 85. In some embodiments, the thickness T1 is in the range from about 1nm to about 6nm, and the thickness T2 is in the range from about 4nm to about 12 nm. In some embodiments, the ratio of thicknesses T1/T2 is in the range from about 0.15 to about 0.4. The thickness T1 at the sidewall between 1nm and 6nm has a sufficient thickness to provide protection from wet etching during removal of the dummy gate while also not being too thick to significantly reduce the volume of the second layer 86B, since the second layer 86B may act as a stressor to strain the channel region of the device.

As a result of the epitaxial process used to form epitaxial source/drain regions 86 in regions 50B and 50C, the upper surfaces of epitaxial source/drain regions 86 have facets that extend laterally outward beyond the sidewalls of fin 58. In some embodiments, these facets merge adjacent epitaxial source/drain regions 86 of the same FinFET, as shown in the embodiment of fig. 12B. In other embodiments, the adjacent epitaxial source/drain regions 86 remain separated after the epitaxial process is completed, as shown in the embodiment of fig. 12C.

In fig. 13, 14, 15 and 16, epitaxial source/drain regions 88 are formed in fin 58 in second region 50C. Epitaxial source/drain regions 88 are formed in fin 58 such that each dummy gate 72 is disposed between a respective adjacent pair of epitaxial source/drain regions 88. In some embodiments, the epitaxial source/drain regions 88 may extend through the LDDs 82. In some embodiments, the gate seal spacers 80 and the gate spacers 84 are used to separate the epitaxial source/drain regions 86 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source/drain regions 88 do not short the gate of a subsequently formed resulting FinFET.

During formation of epitaxial source/drain regions 88 in region 50C (e.g., PMOS region), region 50B (e.g., NMOS region) may be masked by mask 89. Referring first to fig. 13, a patterning process is performed on fin 58 to form recesses 87 in the source/drain regions of fin 58. The formation of the groove 87 may be similar to the formation of the groove 85 described above and will not be repeated here. In some embodiments, however, grooves 85 and 87 are formed by different processes. The groove 87 may also be referred to as a U-shaped groove 87, an example groove 87 of which is shown in fig. 13.

in fig. 14, 15 and 16, epitaxial source/drain regions 88 in region 50C are epitaxially grown in the recesses. In fig. 14, a first layer 88A of epitaxial source/drain regions 88 is formed in region 50C. The first layer 88A may include SiC, SiGeC, SiGeBC, or the like, or combinations thereof. First layer 88A may be epitaxially grown to be in line with groove 87. In an embodiment, first layer 88A may be epitaxially grown to be in line with groove 87. The epitaxial process may be performed by introducing a silicon precursor (e.g., Silane (SiH)) to the fin 58 in the recess 87₄) Dichlorosilane (DCS) (SiH)₄Cl₂) Or a combination thereof) and a carbon precursor (e.g., methylsilane (CSiH)₆) To begin with). In an embodiment, the silicon precursor is introduced at a flow rate of from about 400sccm to about 1200sccm (e.g., about 850sccm), and the carbon precursor is introduced at a flow rate of from about 40sccm to about 100sccm (e.g., about 70 sccm). Further, the deposition can be performed at a temperature of from about 630 ℃ to about 710 ℃ (e.g., about 700 ℃) and a pressure of between about 100Torr to about 300Torr (e.g., about 200 Torr). The first layer 88A may be formed to have an atomic concentration of carbon in a range from about 0.2% to about 5% (e.g., about 3%). An atomic concentration of carbon higher than 5% may increase the source/drain resistance, which may negatively affect the device performance. This first layer 88A (e.g., SiC, SiGeC, or SiGeBC) in region 50C has a low etch rate relative to the etchant used during removal of dummy gate 72 and may help protect source/drain regions 88 from attack and damage during the dummy gate removal process.

In fig. 15, a second layer 88B of epitaxial source/drain regions 86 is formed in region 50C. The second layer 88B may comprise SiGe, SiGeB, or the like, or combinations thereof. A second layer 88B may be epitaxially grown on the first layer 88A to fill the remaining portion of the recess 87. Second layer 88B of epitaxial source/drain region 88 in region 50C may have surfaces that are raised from respective surfaces of fin 58 and may have facets. The second layer 88B may have about 10¹⁹cm^-3And about 10²¹cm^-3Impurity concentration of boron and/or germanium in between.

In fig. 16, a cap layer 88C of epitaxial source/drain regions 88 is formed in region 50C. Capping layer 88C may comprise Si, SiGe, SiGeB, etc. The cap layer 88C may be epitaxially grown on the second layer 88B and may cover any exposed portions of the second layer 88B and the first layer 88A. The cap layer 88C may have a substantially uniform thickness over the facets of the second layer 88B. In some embodiments, capping layer 88B has an impurity concentration of boron and/or germanium that is lower than an impurity concentration of boron and/or germanium in second layer 88B. In some embodiments, capping layer 88B has an impurity concentration of boron and/or germanium that is higher than an impurity concentration of boron and/or germanium in second layer 88B.

As shown in fig. 16, the first layer 88A has a thickness T1 at the side walls of the groove 87 and a thickness T2 at the bottom of the groove 87. In some embodiments, the thickness T1 is in the range from about 1nm to about 6nm, and the thickness T2 is in the range from about 4nm to about 12 nm. In some embodiments, the ratio of thicknesses T1/T2 is in the range from about 0.15 to about 0.4. The thickness T1 at the sidewalls between 1nm and 6nm has a sufficient thickness to provide protection from wet etching during removal of the dummy gate while also not being too thick to significantly reduce the volume of the second layer 88B, since the second layer 88B may act as a stressor to strain the channel region of the device.

As a result of the epitaxial process used to form epitaxial source/drain regions 88 in region 50C, the upper surface of epitaxial source/drain regions 88 has a small plane that extends laterally outward beyond the sidewalls of fin 58. In some embodiments, these facets merge adjacent epitaxial source/drain regions 88 of the same FinFET, as shown in the embodiment of fig. 12B. In other embodiments, adjacent epitaxial source/drain regions 88 remain separated after the epitaxial process is completed, as shown in the embodiment of fig. 12C.

In fig. 17, ILD 90 is deposited over fin 58. The ILD 90 may be formed of a dielectric or semiconductor material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BP)SG), Undoped Silicate Glass (USG), and the like. The semiconductor material may comprise amorphous silicon, silicon germanium (Si)_xGe_1-xWhere x may be between about 0 and 1), pure germanium, and the like. Other insulating or semiconducting materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL), not shown, is disposed between the ILD 90 and the epitaxial source/drain regions 86, gate spacers 84, gate seal spacers 80, and mask 74.

In fig. 18, a planarization process such as CMP may be performed to make the top surface of ILD 90 flush with the top surface of dummy gate 72. The planarization process may also remove the mask 74 over the dummy gate 72, as well as portions of the gate seal spacers 80 and the gate spacers 84 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate seal spacer 80, gate spacer 84, and ILD 90 are flush. Accordingly, the top surface of dummy gate 72 is exposed through ILD 90.

In fig. 19, the dummy gate 72 and the portion of dummy gate dielectric layer 70 directly under the exposed dummy gate 72 are removed in an etch step(s) to form a recess 92. In some embodiments, dummy gate 72 is removed in a wet etch process. For example, a wet etch process may utilize a material such as NH₄a wet etch chemistry such as OH that uses a reactant (etchant) that selectively etches the dummy gate 72 without significantly etching the ILD 90 or the gate spacer 84. Each recess 92 exposes a channel region of a respective fin 58. Each channel region is disposed between an adjacent pair of epitaxial source/drain regions 86. During removal, dummy gate dielectric layer 70 may serve as an etch stop layer when dummy gate 72 is etched. Dummy gate dielectric layer 70 may then be removed after dummy gate 72 is removed.

if there is a defect or break in the gate seal spacer 80 and/or the gate spacer 84, the first layer 86A, which has a low etch rate relative to the etchant used, will protect the source/drain regions 86 from attack and damage the source/drain regions 86 during the dummy gate removal process. If the source/drain regions 86 are damaged during the dummy gate removal process, the subsequent formation of the replacement gate may allow metal of the replacement gate to squeeze through the defect and into the damaged regions of the source/drain regions. This extruded gate portion may short the gate to the source/drain regions and render the device inoperative.

By having the first layers 86A and 88A of the source/drain electrodes 86 and 88 have an atomic concentration of carbon in the range of from about 0.2% to about 5%, the occurrence of metal gate extrusion is reduced. For example, by having an atomic concentration of carbon of at least about 0.2%, the metal extrusion defect rate is significantly improved. Further, when the atomic concentration of carbon is at least 2%, the metal extrusion defect rate is virtually zero, and with an atomic concentration of carbon between about 2.5% and about 5%, the metal extrusion defect rate is zero. The defect rate is reduced in part due to the reduced etch rate of the first layer comprising carbon. For example, as the atomic concentration of carbon in the first layer increases from about 1% to about 2.5%, the etch rate of the first layer decreases by about 80%.

in some embodiments, the dummy gate 72 is removed by an anisotropic dry etch process. For example, the etch process may include a dry etch process using reactive gas (es) that selectively etches the dummy gate 72 without significantly etching the ILD 90 or the gate spacer 84. In some embodiments, the gate 72 may be removed by using a wet etching process and a dry etching process.

In fig. 20, an interface layer 100 is formed in the groove 92. An interface layer 100 is conformally formed over fin 58 so that interface layer 100 lines the sidewalls and bottom surface of recess 92. The interfacial layer 100 may also cover the upper surface of the ILD 90. According to some embodiments, the interface layer 100 is an oxide of the material of the fin 58 and may be formed by, for example, oxidizing the fin 58 in the recess. The interface layer 100 may also be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, and the like.

Further, a gate dielectric layer 102 (including gate dielectric layer 102a in region 50B and gate dielectric layer 102B in region 50C) is formed over the interface layer 100. A gate dielectric layer 102 may be conformally deposited in the recess 92, for example, on the top surface and sidewalls of the fin 58 and on the sidewalls of the interface layer 100 in the recess 92. A gate dielectric layer 102 may also be formed along the top surface of the ILD 90. According to some embodiments, gate dielectric layer 102 is a high-k dielectric material having a k value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 102 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like. The layers 102a and 102b may have different material compositions or may have the same material composition.

Further, in fig. 20, a conductive material is formed to fill the groove 92. The conductive material may include one or more barrier layers, work function layers, and/or work function adjusting layers for adjusting the work function of subsequently formed gate electrodes. In an embodiment, the work function layer 103 (including work function layer 103a in region 50B and work function layer 103B in region 50C) is deposited over the gate dielectric layer 102. The work function layer 103 may be a metal-containing material, such as Al, TiC, TiN, combinations thereof, or multiple layers thereof. A gate electrode layer 104 is then deposited over the work function layer 103 and fills the recess 92. The gate electrode layer 104 can be a metal-containing material, such as W, TiN, TaN, TaC, TiO, Co, Ru, Al, combinations thereof, or multiple layers thereof. Although a single gate electrode layer 104 and a single work function layer 103 are shown, any number of gate electrode layers 104 and any number of work function layers 103 may be deposited in recess 92.

In fig. 21, a planarization process such as CMP is performed to remove excess portions of the interfacial layer 100, the gate dielectric layer 102, the work function layer 103, and the gate electrode layer 104, which are above the top surface of the ILD 90. The gate electrode layer 104 and the rest of the work function layer 103 form a gate electrode 106, and the gate electrode 106 in combination with other layers form the replacement gate of the resulting FinFET. The interface layer 100, gate dielectric layer 102, work function layer 103, and gate electrode layer 104 may be collectively referred to as the "gate" or "gate stack" of the resulting FinFET. The gate stack may extend along sidewalls of the channel region of fin 58.

The formation of the gates in regions 50B and 50C may occur simultaneously such that the gates in these regions are made of the same material. However, in other embodiments, the gates in regions 50B and 50C may be formed by different processes, such that the gates may be made of different materials. When different processes are used, various masking steps may be used to mask and expose the appropriate areas.

In fig. 22, an ILD 110 is formed over the gate stack and ILD 90. In an embodiment, the ILD 110 is a flowable thin film formed by a flowable CVD process. In some embodiments, the ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method (e.g., CVD and PECVD).

Source/drain contacts 112 and gate contacts 114 are formed through the ILDs 90 and 110. Openings for source/drain contacts 112 are formed through the ILDs 90 and 110, and openings for gate contacts 114 are formed through the ILD 110. Acceptable photolithography and etching techniques may be used to form the openings. A liner such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of ILD 110. The remaining liner and conductive material form source/drain contacts 112 and gate contacts 114 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source/drain regions 86 and 88 and the source/drain contacts 112. Source/drain contacts 112 are physically and electrically coupled to the epitaxial source/drain regions 86 and 88, and gate contacts 114 are physically and electrically coupled to the gate electrode 106. The source/drain contacts 112 and the gate contact 114 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it is understood that each of the source/drain contacts 112 and the gate contact 114 may be formed in different cross-sections, which may avoid shorting of the contacts.

Fig. 23 and 24 illustrate another configuration of the first layers 86A and 88A previously shown in fig. 16. This embodiment is similar to the previous embodiment of fig. 1-22, except that in this embodiment, the first layers 86A and 88A have a substantially uniform thickness T3 on the sidewalls and bottom of the grooves 85 and 87. Similar details regarding this embodiment as the previous embodiment will not be repeated here.

Fig. 23 is an equivalent intermediate stage of the process shown in fig. 16 (mask 89 of fig. 16 removed) and will not be described again here. In fig. 23, the first layer 86A may include SiC, SiCP, or the like, or a combination thereof, and the first layer 88A may include SiC, SiGeC, SiGeBC, or the like, or a combination thereof. First layers 86A and 88A may be epitaxially grown to be in line with grooves 85 and 87, respectively. The epitaxial process may be performed by introducing a silicon precursor (e.g., Silane (SiH) to the fin 58 in the recess 85/87₄) Dichlorosilane (DCS) (SiH)₄Cl₂) Or a combination thereof) and a carbon precursor (e.g., methylsilane (CSiH)₆) To begin with). In an embodiment, the silicon precursor is introduced at a flow rate of from about 400sccm to about 1200sccm (e.g., about 850sccm), and the carbon precursor is introduced at a flow rate of from about 10sccm to about 40sccm (e.g., about 25 sccm). Further, the deposition can be performed at a temperature of from about 630 ℃ to about 710 ℃ (e.g., about 700 ℃) and a pressure of between about 100Torr and about 300Torr (e.g., about 200 Torr). The flow rate of the carbon precursor is lower than in the previous examples. The first layer 86A/88A may be formed to have an atomic concentration of carbon in a range from about 0.2% to about 5% (e.g., about 3%). First layer 86A (e.g., SiC and/or SiCP) in region 50B and first layer 88A (e.g., SiC, SiGeC, or SiGeBC) in region 50C have a low etch rate relative to the etchant used during removal of dummy gate 72 and may help protect source/drain regions 88 from attack and damage during the dummy gate removal process.

As discussed in previous embodiments, source/drain regions 86 and 88 may be formed at different times and by different processes.

Fig. 24 illustrates further processing of the structure of fig. 23. The process between these two figures is similar to that shown and described above with reference to fig. 16 to 22, and fig. 22 is an intermediate stage equivalent to fig. 24, and the description is not repeated here.

Fig. 25-28 illustrate another configuration of the source/drain regions 86 and 88 previously illustrated in fig. 1-22. This embodiment is similar to the previous embodiment of fig. 1-22, except that in this embodiment, the recesses 85 and 87 are formed by a two-step etching process including an anisotropic etch and an isotropic etch. Similar details regarding this embodiment as the previous embodiment are not repeated here.

Fig. 25 is an intermediate stage of the same process as fig. 9 (except that in fig. 25, both grooves 85A and 87A are shown as being formed simultaneously), and the description is not repeated here. In fig. 25, grooves 85A and 87A are equivalent to the above-described grooves 85 and 87 and are formed by a first anisotropic etching process. Fig. 26 illustrates further processing of the structure of fig. 25. Although fig. 25-27 show source/drain regions 86 and 88 being formed simultaneously, source/drain regions 86 and 88 may be formed at different times and by different processes, as discussed in previous embodiments.

In fig. 26, a second etching process is performed on the grooves 85A and 87A to form grooves 85B and 87B. The second etching process may be an isotropic wet etching process. In some embodiments, a composition comprising Cl may be used₂、NF₃A combination thereof, etc., to perform an isotropic etching process. After the second etch process, the sidewalls of recesses 85B and 87B extend laterally a distance D1 below the outer sidewalls of gate spacer 84. In some embodiments, distance D1 is in a range from about 0.3nm to about 5 nm. This second etch process may increase the volume of the epitaxial source/drain regions 86, which may increase the mobility of the FinFET.

fig. 27 illustrates further processing of the structure of fig. 26. The process between these two figures is similar to that shown and described above with reference to figures 8 to 16, and figure 27 is an intermediate stage equivalent to figure 26 and will not be described again here.

As shown in fig. 27, the first layers 86A and 88A have a thickness T4 at the sidewalls of the grooves 85B and 87B and a thickness T5 at the bottoms of the grooves 85B and 87B. In some embodiments, the thickness T4 is in the range from about 3nm to about 12nm, and the thickness T5 is in the range from about 3nm to about 12 nm. Due to the larger volume of the source/drain regions, the thicknesses T4 and T5 in this embodiment may be greater than the thicknesses T1 and T2 of the previous embodiment. In this embodiment, the epitaxial process used to form first layers 86A and 88A may be longer than the epitaxial process used to form first layers 86A and 88A in the previous embodiment due to the larger volume of recesses 85B and 87B from the second etch process. In some embodiments, the ratio of thicknesses T4/T5 is in the range from about 0.3 to about 1.3. The thickness T4 at the sidewalls between 3nm and 12nm is of sufficient thickness to provide protection from wet etching during removal of the dummy gate, while also not being too thick to significantly reduce the volume of the second layers 86B and 88B, since the second layers 86B and 88B may act as stressors for applying strain to the channel region of the device.

Second layers 86B and 88B may be epitaxially grown on first layers 86A and 88A to fill the remaining portions of recesses 85B and 87B. The second layers 86B and 88B of the epitaxial source/drain regions 86 and 88 in the regions 50B and 50C may have surfaces that are raised from the respective surfaces of the fin 58, and may have facets. In this embodiment, the epitaxial process used to form second layers 86B and 88B may be longer than the epitaxial process used to form second layers 86B and 88B in the previous embodiment due to the larger volume of recesses 85B and 87B from the second etch process.

Fig. 28 illustrates further processing of the structure of fig. 27. The process between these two figures is similar to that shown and described above with reference to fig. 16 to 22, and fig. 28 is an intermediate stage equivalent to fig. 22 and will not be described again here.