阅读说明：本技术 一种逻辑门电路 (Logic gate circuit ) 是由 赵静 唐样洋 于 2018-06-01 设计创作，主要内容包括：本申请实施例提供了一种逻辑门电路,包括：上拉电路和下拉电路；上拉电路包括并联的N个P型TFET；下拉电路包括串联的N个N型MOSFET或者FINFET；N大于1；其中,所述N个P型第一类场效应晶体管的栅极与所述N个N型第二类场效应晶体管的栅极一一电连接,并作为所述逻辑门电路的N个输入端,所述N个P型第一类场效应晶体管的漏极作为所述逻辑门电路的输出端。由于TFET能够在电源电压较小时正常运行,保证了逻辑门电路的功耗较小。同时,MOSFET或者FINFET的驱动电流较大,从而解决了逻辑门电路延迟较长的问题。可见,本申请实施例在保证功耗较小的前提下,进一步解决延迟较长的问题。(The embodiment of the application provides a logic gate circuit, which comprises: a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N P-type TFETs connected in parallel; the pull-down circuit comprises N type MOSFETs or FINFETs connected in series; n is greater than 1; the gates of the N P-type first-class field effect transistors are electrically connected with the gates of the N-type second-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N P-type first-class field effect transistors serve as output ends of the logic gate circuit. Because the TFET can normally operate when the power supply voltage is low, the power consumption of the logic gate circuit is ensured to be low. Meanwhile, the drive current of the MOSFET or the FINFET is larger, so that the problem of longer delay of a logic gate circuit is solved. Therefore, the embodiment of the application further solves the problem of long delay on the premise of ensuring low power consumption.)

1. a logic gate circuit, comprising: a pull-up circuit and a pull-down circuit;

the pull-up circuit comprises N P-type first field effect transistors connected in parallel, wherein the sources of the N P-type first field effect transistors are electrically connected, the sources of the N P-type first field effect transistors are electrically connected with a power supply end, and the drains of the N P-type first field effect transistors are electrically connected; the pull-down circuit comprises N-type second-class field effect transistors which are connected in series, and in two adjacent second-class field effect transistors of the N-type second-class field effect transistors, the source electrode of one second-class field effect transistor is electrically connected with the drain electrode of the other second-class field effect transistor; one end of the two ends of the pull-down circuit, which is a drain electrode, is electrically connected with the drain electrodes of the N P-type first-class field effect transistors, and one end of the two ends of the pull-down circuit, which is a source electrode, is electrically connected with the ground end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1;

The gates of the N P-type first-class field effect transistors are electrically connected with the gates of the N-type second-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N P-type first-class field effect transistors serve as output ends of the logic gate circuit.

2. The logic gate circuit of claim 1, wherein the pull-up circuit comprises a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor are P-type first type field effect transistors; the pull-down circuit comprises a third field effect transistor and a fourth field effect transistor, wherein the third field effect transistor and the fourth field effect transistor are N-type second-class field effect transistors;

The source electrode of the first field effect transistor is electrically connected with the source electrode of the second field effect transistor and is electrically connected with the power supply end, the drain electrode of the first field effect transistor is electrically connected with the drain electrode of the second field effect transistor and is electrically connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, and the source electrode of the fourth field effect transistor is electrically connected with the ground end;

the grid electrode of the first field effect transistor is electrically connected with the grid electrode of the third field effect transistor and serves as a first input end of the logic gate circuit, the grid electrode of the second field effect transistor is electrically connected with the grid electrode of the fourth field effect transistor and serves as a second input end of the logic gate circuit, and the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor serve as output ends of the logic gate circuit.

3. The logic gate circuit of claim 1, wherein the pull-up circuit comprises a fifth field effect transistor, a sixth field effect transistor, and a seventh field effect transistor, wherein the fifth field effect transistor, the sixth field effect transistor, and the seventh field effect transistor are P-type first type field effect transistors; the pull-down circuit comprises an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor, wherein the eighth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are N-type second-class field effect transistors;

A source electrode of the fifth field effect transistor, a source electrode of the sixth field effect transistor and a source electrode of the seventh field effect transistor are electrically connected and are electrically connected with the power supply terminal, a drain electrode of the fifth field effect transistor, a drain electrode of the sixth field effect transistor and a drain electrode of the seventh field effect transistor are electrically connected and are electrically connected with a drain electrode of the eighth field effect transistor, a source electrode of the eighth field effect transistor is electrically connected with a drain electrode of the ninth field effect transistor, a source electrode of the ninth field effect transistor is electrically connected with a drain electrode of the tenth field effect transistor, and a source electrode of the tenth field effect transistor is electrically connected with a ground terminal;

A gate of the fifth field effect transistor is electrically connected with a gate of the eighth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixth field effect transistor is electrically connected with a gate of the ninth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventh field effect transistor is electrically connected with a gate of the tenth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifth field effect transistor, a drain of the sixth field effect transistor and a drain of the seventh field effect transistor serve as output ends of the logic gate circuit.

4. a logic gate circuit according to any one of claims 1 to 3,

When an input signal of at least one input end of the N input ends is a low level signal, at least one first-class field effect transistor in the N P-type first-class field effect transistors is switched on, at least one second-class field effect transistor in the N-type second-class field effect transistors is switched off, and an output signal of the output end is a high level signal;

When the input signals of all the input ends in the N input ends are high level signals, the N P-type first-class field effect transistors are all switched off, the N-type second-class field effect transistors are all switched on, and the output signals of the output ends are low level signals.

5. A logic gate circuit according to any of claims 1 to 4, characterized in that the logic gate circuit further comprises an inverting circuit, wherein:

the input end of the inverter circuit is electrically connected with the drain electrodes of the N P-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

6. A logic gate circuit, comprising: a pull-up circuit and a pull-down circuit;

the pull-up circuit comprises N P-type second-class field effect transistors which are connected in series, and in two adjacent second-class field effect transistors of the N P-type second-class field effect transistors, the source electrode of one second-class field effect transistor is electrically connected with the drain electrode of the other second-class field effect transistor; the pull-down circuit comprises N-type first field effect transistors connected in parallel, wherein the sources of the N-type first field effect transistors are electrically connected, the sources of the N-type first field effect transistors are electrically connected with a ground end, and the drains of the N-type first field effect transistors are electrically connected; one end of the pull-up circuit, which is a drain electrode, in the two ends is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and one end of the pull-up circuit, which is a source electrode, in the two ends is electrically connected with a power supply end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1;

The gates of the N-type first-class field effect transistors are electrically connected with the gates of the N P-type second-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N-type first-class field effect transistors serve as output ends of the logic gate circuit.

7. The logic gate circuit of claim 6, wherein the pull-down circuit comprises an eleventh field effect transistor and a twelfth field effect transistor, wherein the eleventh field effect transistor and the twelfth field effect transistor are N-type first type field effect transistors; the pull-up circuit comprises a thirteenth field effect transistor and a fourteenth field effect transistor, wherein the thirteenth field effect transistor and the fourteenth field effect transistor are P-type second-type field effect transistors;

A source electrode of the eleventh field effect transistor is electrically connected with a source electrode of the twelfth field effect transistor and is electrically connected with the ground terminal, a drain electrode of the eleventh field effect transistor is electrically connected with a drain electrode of the twelfth field effect transistor and is electrically connected with a drain electrode of the thirteenth field effect transistor, a source electrode of the thirteenth field effect transistor is electrically connected with a drain electrode of the fourteenth field effect transistor, and a source electrode of the fourteenth field effect transistor is electrically connected with the power supply terminal;

a gate of the eleventh field effect transistor is electrically connected with a gate of the thirteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the twelfth field effect transistor is electrically connected with a gate of the fourteenth field effect transistor and serves as a second input end of the logic gate circuit, and a drain of the eleventh field effect transistor and a drain of the twelfth field effect transistor serve as output ends of the logic gate circuit.

8. The logic gate circuit of claim 6, wherein the pull-down circuit comprises a fifteenth field effect transistor, a sixteenth field effect transistor, and a seventeenth field effect transistor, wherein the fifteenth field effect transistor, the sixteenth field effect transistor, and the seventeenth field effect transistor are N-type first type field effect transistors; the pull-up circuit comprises an eighteenth field effect transistor, a nineteenth field effect transistor and a twentieth field effect transistor, wherein the eighteenth field effect transistor, the nineteenth field effect transistor and the twentieth field effect transistor are P-type second-class field effect transistors;

A source electrode of the fifteenth field effect transistor, a source electrode of the sixteenth field effect transistor, and a source electrode of the seventeenth field effect transistor are electrically connected and electrically connected to the ground terminal, a drain electrode of the fifteenth field effect transistor, a drain electrode of the sixteenth field effect transistor, and a drain electrode of the seventeenth field effect transistor are electrically connected and electrically connected to a drain electrode of the eighteenth field effect transistor, a source electrode of the eighteenth field effect transistor is electrically connected to a drain electrode of the nineteenth field effect transistor, a source electrode of the nineteenth field effect transistor is electrically connected to a drain electrode of the twentieth field effect transistor, and a source electrode of the twentieth field effect transistor is electrically connected to the power source;

A gate of the fifteenth field effect transistor is electrically connected with a gate of the eighteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixteenth field effect transistor is electrically connected with a gate of the nineteenth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventeenth field effect transistor is electrically connected with a gate of the twentieth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifteenth field effect transistor, a drain of the sixteenth field effect transistor and a drain of the seventeenth field effect transistor serve as output ends of the logic gate circuit.

9. The logic gate circuit as claimed in any one of claims 6 to 8, wherein when the input signal of at least one of the N input terminals is a high level signal, at least one of the N P-type second type field effect transistors is turned off, at least one of the N-type first type field effect transistors is turned on, and the output signal of the output terminal is a low level signal;

When the input signals of all the input ends in the N input ends are low level signals, the N P-type second-class field effect transistors are all conducted, the N-type first-class field effect transistors are all disconnected, and the output signals of the output ends are high level signals.

10. A logic gate circuit according to any of claims 6 to 9, characterised in that the logic gate circuit further comprises an inverting circuit, wherein:

The input end of the inverter circuit is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

11. An integrated circuit comprising a logic gate circuit as claimed in any one of claims 1 to 10.

Technical Field

The embodiment of the application relates to the field of electronic circuits, in particular to a logic gate circuit.

Background

A logic gate circuit refers to a circuit capable of performing a basic logical operation such as a nor, nand, or and.

At present, a Complementary Metal Oxide Semiconductor (CMOS) logic gate circuit is usually used to implement basic logic operation, and the CMOS logic gate circuit includes a pull-up circuit and a pull-down circuit, where the pull-up circuit and the pull-down circuit are both composed of Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs). However, since the MOSFET is limited by the boltzmann distribution of carriers at room temperature, the Subthreshold Swing (SS) value of the MOSFET cannot be smaller than 60mV/decade, which results in the MOSFET not being able to operate normally when the power voltage is small, and thus has a problem of large power consumption.

In order to solve the above problem, one solution is to use a Tunneling Field Effect Transistor (TFET) instead of all the MOSFETs in the CMOS logic gate circuit. However, since TFET is a tunneling mechanism, the output curve is linear, which leads to a problem of small driving current, and the small driving current leads to a problem of not being able to rapidly change the level state of the output signal of the logic gate circuit, which leads to a problem of long delay of the logic gate circuit.

how to further solve the problem of long delay on the premise of ensuring that the designed logic gate circuit has low power consumption is a technical problem to be solved urgently at present.

Disclosure of Invention

the technical problem solved by the embodiment of the application is to provide a logic gate circuit, and further solve the problem of long delay on the premise of ensuring low power consumption.

Therefore, the technical scheme for solving the technical problem in the embodiment of the application is as follows:

in a first aspect, there is provided a logic gate circuit comprising: a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N P-type first field effect transistors connected in parallel, wherein the sources of the N P-type first field effect transistors are electrically connected, the sources of the N P-type first field effect transistors are electrically connected with a power supply end, and the drains of the N P-type first field effect transistors are electrically connected; the pull-down circuit comprises N-type second-class field effect transistors which are connected in series, and in two adjacent second-class field effect transistors of the N-type second-class field effect transistors, the source electrode of one second-class field effect transistor is electrically connected with the drain electrode of the other second-class field effect transistor; one end of the two ends of the pull-down circuit, which is a drain electrode, is electrically connected with the drain electrodes of the N P-type first-class field effect transistors, and one end of the two ends of the pull-down circuit, which is a source electrode, is electrically connected with the ground end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1; the gates of the N P-type first-class field effect transistors are electrically connected with the gates of the N-type second-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N P-type first-class field effect transistors serve as output ends of the logic gate circuit.

In the logic gate circuit provided by the first aspect, the nand gate is formed by N TFETs connected in parallel and N MOSFETs or FINFETs connected in series. The TFET has a smaller SS value, and can normally operate when the power supply voltage is smaller, for example, when the power supply voltage is equal to 0.5V, so that the logic gate circuit has smaller power consumption. Meanwhile, the output curve (the relation interval between the output current and the output voltage) of the MOSFET or the FINFET is nonlinear, so that the driving current is large, the pulse signal output by the output end of the logic gate circuit can be quickly pulled from high level to low level, and the problem of long delay of the logic gate circuit is solved. Therefore, the embodiment of the application further solves the problem of long delay on the premise of ensuring low power consumption. Experiments show that the delay of the NAND gate can be reduced by about 85% compared with a logic gate circuit which totally adopts TFET. In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

In one possible design, the electrical connection is a physical connection or an electrical connection.

In one possible design, the pull-up circuit includes a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor are P-type first type field effect transistors; the pull-down circuit comprises a third field effect transistor and a fourth field effect transistor, wherein the third field effect transistor and the fourth field effect transistor are N-type second-class field effect transistors; the source electrode of the first field effect transistor is electrically connected with the source electrode of the second field effect transistor and is electrically connected with the power supply end, the drain electrode of the first field effect transistor is electrically connected with the drain electrode of the second field effect transistor and is electrically connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, and the source electrode of the fourth field effect transistor is electrically connected with the ground end; the grid electrode of the first field effect transistor is electrically connected with the grid electrode of the third field effect transistor and serves as a first input end of the logic gate circuit, the grid electrode of the second field effect transistor is electrically connected with the grid electrode of the fourth field effect transistor and serves as a second input end of the logic gate circuit, and the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor serve as output ends of the logic gate circuit.

the design provides a specific circuit structure of a two-input NAND gate.

In one possible design, the pull-up circuit includes a fifth field effect transistor, a sixth field effect transistor, and a seventh field effect transistor, wherein the fifth field effect transistor, the sixth field effect transistor, and the seventh field effect transistor are P-type first type field effect transistors; the pull-down circuit comprises an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor, wherein the eighth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are N-type second-class field effect transistors; a source electrode of the fifth field effect transistor, a source electrode of the sixth field effect transistor and a source electrode of the seventh field effect transistor are electrically connected and are electrically connected with the power supply terminal, a drain electrode of the fifth field effect transistor, a drain electrode of the sixth field effect transistor and a drain electrode of the seventh field effect transistor are electrically connected and are electrically connected with a drain electrode of the eighth field effect transistor, a source electrode of the eighth field effect transistor is electrically connected with a drain electrode of the ninth field effect transistor, a source electrode of the ninth field effect transistor is electrically connected with a drain electrode of the tenth field effect transistor, and a source electrode of the tenth field effect transistor is electrically connected with a ground terminal; a gate of the fifth field effect transistor is electrically connected with a gate of the eighth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixth field effect transistor is electrically connected with a gate of the ninth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventh field effect transistor is electrically connected with a gate of the tenth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifth field effect transistor, a drain of the sixth field effect transistor and a drain of the seventh field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a three-input NAND gate.

In one possible design, when the input signal of at least one of the N input terminals is a low level signal, at least one of the N P-type first field effect transistors is turned on, at least one of the N-type second field effect transistors is turned off, and the output signal of the output terminal is a high level signal; when the input signals of all the input ends in the N input ends are high level signals, the N P-type first-class field effect transistors are all switched off, the N-type second-class field effect transistors are all switched on, and the output signals of the output ends are low level signals.

In one possible design, the logic gate circuit further includes an inverting circuit, wherein:

the input end of the inverter circuit is electrically connected with the drain electrodes of the N P-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

In one possible design, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, the twenty-first field effect transistor and the twenty-second field effect transistor being either a first type field effect transistor or a second type field effect transistor; the source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

This design provides a specific structure for the and gate.

in a second aspect, there is provided a logic gate circuit comprising: a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N P-type second-class field effect transistors which are connected in series, and in two adjacent second-class field effect transistors of the N P-type second-class field effect transistors, the source electrode of one second-class field effect transistor is electrically connected with the drain electrode of the other second-class field effect transistor; the pull-down circuit comprises N-type first field effect transistors connected in parallel, wherein the sources of the N-type first field effect transistors are electrically connected, the sources of the N-type first field effect transistors are electrically connected with a ground end, and the drains of the N-type first field effect transistors are electrically connected; one end of the pull-up circuit, which is a drain electrode, in the two ends is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and one end of the pull-up circuit, which is a source electrode, in the two ends is electrically connected with a power supply end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1; the gates of the N-type first-class field effect transistors are electrically connected with the gates of the N P-type second-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N-type first-class field effect transistors serve as output ends of the logic gate circuit.

The second aspect provides a logic gate circuit in which N TFETs connected in parallel and N MOSFETs or FINFETs connected in series are used to form a nor gate. The TFET has a smaller SS value, and can normally operate when the power supply voltage is smaller, for example, when the power supply voltage is equal to 0.5V, so that the logic gate circuit has smaller power consumption. Meanwhile, the output curve (the relation interval between the output current and the output voltage) of the MOSFET or the FINFET is nonlinear, so that the driving current is large, the pulse signal output by the output end of the logic gate circuit can be quickly pulled from low level to high level, and the problem of long delay of the logic gate circuit is solved. Therefore, the embodiment of the application further solves the problem of long delay on the premise of ensuring low power consumption. Experiments show that the delay of the NOR gate can be reduced by about 75% compared with a logic gate circuit which totally adopts TFET. In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

In one possible design, the pull-down circuit includes an eleventh field effect transistor and a twelfth field effect transistor, wherein the eleventh field effect transistor and the twelfth field effect transistor are N-type first type field effect transistors; the pull-up circuit comprises a thirteenth field effect transistor and a fourteenth field effect transistor, wherein the thirteenth field effect transistor and the fourteenth field effect transistor are P-type second-type field effect transistors; a source electrode of the eleventh field effect transistor is electrically connected with a source electrode of the twelfth field effect transistor and is electrically connected with the ground terminal, a drain electrode of the eleventh field effect transistor is electrically connected with a drain electrode of the twelfth field effect transistor and is electrically connected with a drain electrode of the thirteenth field effect transistor, a source electrode of the thirteenth field effect transistor is electrically connected with a drain electrode of the fourteenth field effect transistor, and a source electrode of the fourteenth field effect transistor is electrically connected with the power supply terminal; a gate of the eleventh field effect transistor is electrically connected with a gate of the thirteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the twelfth field effect transistor is electrically connected with a gate of the fourteenth field effect transistor and serves as a second input end of the logic gate circuit, and a drain of the eleventh field effect transistor and a drain of the twelfth field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a two-input NOR gate.

In one possible design, the pull-down circuit includes a fifteenth field effect transistor, a sixteenth field effect transistor, and a seventeenth field effect transistor, wherein the fifteenth field effect transistor, the sixteenth field effect transistor, and the seventeenth field effect transistor are N-type first type field effect transistors; the pull-up circuit comprises an eighteenth field effect transistor, a nineteenth field effect transistor and a twentieth field effect transistor, wherein the eighteenth field effect transistor, the nineteenth field effect transistor and the twentieth field effect transistor are P-type second-class field effect transistors; a source electrode of the fifteenth field effect transistor, a source electrode of the sixteenth field effect transistor, and a source electrode of the seventeenth field effect transistor are electrically connected and electrically connected to the ground terminal, a drain electrode of the fifteenth field effect transistor, a drain electrode of the sixteenth field effect transistor, and a drain electrode of the seventeenth field effect transistor are electrically connected and electrically connected to a drain electrode of the eighteenth field effect transistor, a source electrode of the eighteenth field effect transistor is electrically connected to a drain electrode of the nineteenth field effect transistor, a source electrode of the nineteenth field effect transistor is electrically connected to a drain electrode of the twentieth field effect transistor, and a source electrode of the twentieth field effect transistor is electrically connected to the power source; a gate of the fifteenth field effect transistor is electrically connected with a gate of the eighteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixteenth field effect transistor is electrically connected with a gate of the nineteenth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventeenth field effect transistor is electrically connected with a gate of the twentieth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifteenth field effect transistor, a drain of the sixteenth field effect transistor and a drain of the seventeenth field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a three-input NOR gate.

In one possible design, when the input signal of at least one of the N input terminals is a high level signal, at least one of the N P-type second field effect transistors is turned off, at least one of the N-type first field effect transistors is turned on, and the output signal of the output terminal is a low level signal; when the input signals of all the input ends in the N input ends are low level signals, the N P-type second-class field effect transistors are all conducted, the N-type first-class field effect transistors are all disconnected, and the output signals of the output ends are high level signals.

in one possible design, the logic gate circuit further includes an inverting circuit, wherein: the input end of the inverter circuit is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

In one possible design, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, the twenty-first field effect transistor and the twenty-second field effect transistor being either a first type field effect transistor or a second type field effect transistor; the source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

In a third aspect, there is provided a logic gate circuit comprising: a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N P-type second field effect transistors connected in parallel, wherein the sources of the N P-type second field effect transistors are electrically connected, the sources of the N P-type second field effect transistors are electrically connected with a power supply end, and the drains of the N P-type second field effect transistors are electrically connected; the pull-down circuit comprises N-type first-class field effect transistors which are connected in series, wherein in two adjacent first-class field effect transistors of the N-type first-class field effect transistors, the source electrode of one first-class field effect transistor is electrically connected with the drain electrode of the other first-class field effect transistor; one end of the two ends of the pull-down circuit, which is a drain electrode, is electrically connected with the drain electrodes of the N P-type second field effect transistors, and one end of the two ends of the pull-down circuit, which is a source electrode, is electrically connected with the ground end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1; the gates of the N P-type second field effect transistors are electrically connected with the gates of the N-type first field effect transistors one by one and are used as N input ends of the logic gate circuit, and the drains of the N P-type second field effect transistors are used as the output ends of the logic gate circuit.

the third aspect provides a logic gate circuit, in which N parallel MOSFETs or FINFETs and N series TFETs are used to form a nand gate. The TFET has a smaller SS value, and can normally operate when the power supply voltage is smaller, for example, when the power supply voltage is equal to 0.5V, so that the logic gate circuit has smaller power consumption. In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

in one possible design, the electrical connection is a physical connection or an electrical connection.

in one possible design, the pull-up circuit includes a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor are P-type second type field effect transistors; the pull-down circuit comprises a third field effect transistor and a fourth field effect transistor, wherein the third field effect transistor and the fourth field effect transistor are N-type first-class field effect transistors; the source electrode of the first field effect transistor is electrically connected with the source electrode of the second field effect transistor and is electrically connected with the power supply end, the drain electrode of the first field effect transistor is electrically connected with the drain electrode of the second field effect transistor and is electrically connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, and the source electrode of the fourth field effect transistor is electrically connected with the ground end; the grid electrode of the first field effect transistor is electrically connected with the grid electrode of the third field effect transistor and serves as a first input end of the logic gate circuit, the grid electrode of the second field effect transistor is electrically connected with the grid electrode of the fourth field effect transistor and serves as a second input end of the logic gate circuit, and the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a two-input NAND gate.

in one possible design, the pull-up circuit includes a fifth field effect transistor, a sixth field effect transistor, and a seventh field effect transistor, wherein the fifth field effect transistor, the sixth field effect transistor, and the seventh field effect transistor are P-type second type field effect transistors; the pull-down circuit comprises an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor, wherein the eighth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are N-type first-type field effect transistors; a source electrode of the fifth field effect transistor, a source electrode of the sixth field effect transistor and a source electrode of the seventh field effect transistor are electrically connected and are electrically connected with the power supply terminal, a drain electrode of the fifth field effect transistor, a drain electrode of the sixth field effect transistor and a drain electrode of the seventh field effect transistor are electrically connected and are electrically connected with a drain electrode of the eighth field effect transistor, a source electrode of the eighth field effect transistor is electrically connected with a drain electrode of the ninth field effect transistor, a source electrode of the ninth field effect transistor is electrically connected with a drain electrode of the tenth field effect transistor, and a source electrode of the tenth field effect transistor is electrically connected with a ground terminal; a gate of the fifth field effect transistor is electrically connected with a gate of the eighth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixth field effect transistor is electrically connected with a gate of the ninth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventh field effect transistor is electrically connected with a gate of the tenth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifth field effect transistor, a drain of the sixth field effect transistor and a drain of the seventh field effect transistor serve as output ends of the logic gate circuit.

the design provides a specific circuit structure of a three-input NAND gate.

In one possible design, when the input signal of at least one of the N input terminals is a low level signal, at least one of the N P-type second field effect transistors is turned on, at least one of the N-type first field effect transistors is turned off, and the output signal of the output terminal is a high level signal; when the input signals of all the input ends in the N input ends are high level signals, the N P type second type field effect transistors are all disconnected, the N type first type field effect transistors are all connected, and the output signals of the output ends are low level signals.

In one possible design, the logic gate circuit further includes an inverting circuit, wherein: the input end of the inverter circuit is electrically connected with the drain electrodes of the N P-type second-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

In one possible design, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, the twenty-first field effect transistor and the twenty-second field effect transistor being either a first type field effect transistor or a second type field effect transistor; the source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

This design provides a specific structure for the and gate.

In a fourth aspect, there is provided a logic gate circuit comprising: a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N P-type first field effect transistors which are connected in series, wherein the source electrode of one first field effect transistor is electrically connected with the drain electrode of the other first field effect transistor in two adjacent first field effect transistors of the N P-type first field effect transistors; the pull-down circuit comprises N-type second field effect transistors connected in parallel, wherein the sources of the N-type second field effect transistors are electrically connected and the sources of the N-type second field effect transistors are electrically connected with a ground terminal, and the drains of the N-type second field effect transistors are electrically connected; one end of the pull-up circuit, which is a drain electrode, at the two ends is electrically connected with the drain electrodes of the N-type second-class field effect transistors, and one end of the pull-up circuit, which is a source electrode, at the two ends is electrically connected with a power supply end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1; the gates of the N-type second-class field effect transistors are electrically connected with the gates of the N P-type first-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N-type second-class field effect transistors serve as output ends of the logic gate circuit.

The fourth aspect provides a logic gate circuit in which N TFETs connected in series and N MOSFETs or FINFETs connected in parallel are used to form a nor gate. The TFET has a smaller SS value, and can normally operate when the power supply voltage is smaller, for example, when the power supply voltage is equal to 0.5V, so that the logic gate circuit has smaller power consumption. In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

in one possible design, the pull-down circuit includes an eleventh field effect transistor and a twelfth field effect transistor, wherein the eleventh field effect transistor and the twelfth field effect transistor are N-type second type field effect transistors; the pull-up circuit comprises a thirteenth field effect transistor and a fourteenth field effect transistor, wherein the thirteenth field effect transistor and the fourteenth field effect transistor are P-type first-type field effect transistors; a source electrode of the eleventh field effect transistor is electrically connected with a source electrode of the twelfth field effect transistor and is electrically connected with the ground terminal, a drain electrode of the eleventh field effect transistor is electrically connected with a drain electrode of the twelfth field effect transistor and is electrically connected with a drain electrode of the thirteenth field effect transistor, a source electrode of the thirteenth field effect transistor is electrically connected with a drain electrode of the fourteenth field effect transistor, and a source electrode of the fourteenth field effect transistor is electrically connected with the power supply terminal; a gate of the eleventh field effect transistor is electrically connected with a gate of the thirteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the twelfth field effect transistor is electrically connected with a gate of the fourteenth field effect transistor and serves as a second input end of the logic gate circuit, and a drain of the eleventh field effect transistor and a drain of the twelfth field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a two-input NOR gate.

In one possible design, the pull-down circuit includes a fifteenth field effect transistor, a sixteenth field effect transistor, and a seventeenth field effect transistor, wherein the fifteenth field effect transistor, the sixteenth field effect transistor, and the seventeenth field effect transistor are N-type second type field effect transistors; the pull-up circuit comprises an eighteenth field effect transistor, a nineteenth field effect transistor and a twentieth field effect transistor, wherein the eighteenth field effect transistor, the nineteenth field effect transistor and the twentieth field effect transistor are P-type first-type field effect transistors; a source electrode of the fifteenth field effect transistor, a source electrode of the sixteenth field effect transistor, and a source electrode of the seventeenth field effect transistor are electrically connected and electrically connected to the ground terminal, a drain electrode of the fifteenth field effect transistor, a drain electrode of the sixteenth field effect transistor, and a drain electrode of the seventeenth field effect transistor are electrically connected and electrically connected to a drain electrode of the eighteenth field effect transistor, a source electrode of the eighteenth field effect transistor is electrically connected to a drain electrode of the nineteenth field effect transistor, a source electrode of the nineteenth field effect transistor is electrically connected to a drain electrode of the twentieth field effect transistor, and a source electrode of the twentieth field effect transistor is electrically connected to the power source; a gate of the fifteenth field effect transistor is electrically connected with a gate of the eighteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixteenth field effect transistor is electrically connected with a gate of the nineteenth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventeenth field effect transistor is electrically connected with a gate of the twentieth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifteenth field effect transistor, a drain of the sixteenth field effect transistor and a drain of the seventeenth field effect transistor serve as output ends of the logic gate circuit.

The design provides a specific circuit structure of a three-input NOR gate.

In one possible design, when the input signal of at least one of the N input terminals is a high level signal, at least one of the N P-type first field effect transistors is turned off, at least one of the N-type second field effect transistors is turned on, and the output signal of the output terminal is a low level signal; when the input signals of all the input ends in the N input ends are low level signals, the N P-type first-class field effect transistors are all conducted, the N-type second-class field effect transistors are all disconnected, and the output signals of the output ends are high level signals.

In one possible design, the logic gate circuit further includes an inverting circuit, wherein: the input end of the inverter circuit is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

in one possible design, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, the twenty-first field effect transistor and the twenty-second field effect transistor being either a first type field effect transistor or a second type field effect transistor; the source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

In a fifth aspect, there is provided an integrated circuit comprising any one of the logic gates provided in the first, second, third and fourth aspects.

In a sixth aspect, a logical operation method is provided, which is used in any one of the logical gate circuits provided in the first, second, third and fourth aspects; the method comprises the following steps: inputting N pulse signals to N input ends of the logic gate circuit respectively; and obtaining the operation result of the N pulse signals output by the output end of the logic gate circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a logic gate circuit according to the present application;

FIG. 2 is a schematic structural diagram of another embodiment of a logic gate circuit according to the present disclosure;

fig. 3 is a schematic structural diagram of an embodiment of a nand gate provided in the present application;

FIG. 4 is a schematic diagram of an embodiment of a two-input NAND gate according to the present disclosure;

FIG. 5 is a schematic diagram of an embodiment of a three-input NAND gate according to the present disclosure;

fig. 6 is a schematic structural diagram of an embodiment of an and gate according to the present application;

Fig. 7 is a schematic structural diagram of an embodiment of a nor gate provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of an embodiment of a two-input nor gate provided in an embodiment of the present application;

Fig. 9 is a schematic structural diagram of an embodiment of a three-input nor gate provided in an embodiment of the present application;

FIG. 10 is a schematic structural diagram of an embodiment of an OR gate according to an embodiment of the present disclosure;

FIG. 11 is a schematic flow chart diagram illustrating one embodiment of a method provided by an embodiment of the present application;

FIG. 12 is a schematic diagram of an embodiment of an integrated circuit according to the present disclosure;

Fig. 13 is a schematic structural diagram of another embodiment of an integrated circuit according to the present application.

Detailed Description

The function of the logic gate circuit can be realized by using the TFET instead of all the MOSFETs in the CMOS logic gate circuit. However, since TFET is a tunneling mechanism, the output curve is linear, which leads to a problem of small driving current, and the small driving current leads to a problem of not being able to rapidly change the level state of the output signal of the logic gate circuit, which leads to a problem of long delay of the logic gate circuit. It is found through experiments that there is a long delay when the nand gate is switched from high level to low level, and there is a long delay when the nand gate is switched from low level to high level. In addition, the logic gate circuit has a problem that the overshoot voltage and the undershoot voltage are large because the capacitance value of the parasitic capacitance of the TFET is large.

the embodiment of the application provides a logic gate circuit and a logic operation method, and the problem of long delay is further solved on the premise of ensuring low power consumption. And further the problem of large overshoot voltage and undershoot voltage can be solved.

referring to FIG. 1, an embodiment of a logic gate circuit is provided. In this embodiment, the logic gate circuit includes a pull-up circuit 101 and a pull-down circuit 102. The logic gate may specifically be a nand gate.

The pull-up circuit 101 includes N P-type first field effect transistors connected in parallel, and the pull-down circuit 102 includes N-type second field effect transistors connected in series, where N is greater than 1. The first type of Field Effect Transistor comprises a TFET, and the second type of Field Effect Transistor comprises a MOSFET or a Fin Field Effect Transistor (FINFET).

Wherein the sources of the N P-type first field effect transistors are electrically connected and the drains of the N P-type first field effect transistors are electrically connected. The N-type second-class field effect transistors are connected in series in a forward direction, namely in two adjacent second-class field effect transistors of the N-type second-class field effect transistors, the source electrode of one second-class field effect transistor is electrically connected with the drain electrode of the other second-class field effect transistor.

The pull-up circuit 101 and the pull-down circuit 102 are sequentially connected in series between a power end and a Ground (GND), that is, the sources of the N P-type first-class field effect transistors in the pull-up circuit 101 are electrically connected to the power end, the drains of the N P-type first-class field effect transistors are electrically connected to one of the two ends of the pull-down circuit 102, which is the drain, and one of the two ends of the pull-down circuit 102, which is the source, is electrically connected to the Ground.

The power supply voltage input by the power supply terminal may be equal to or greater than the normal operating voltage of the first type field effect transistor and less than the normal operating voltage of the second type field effect transistor, for example, the normal operating voltages of the first type field effect transistor are all 0.5V, the normal operating voltage of the first type field effect transistor is 0.7V, and the power supply voltage input by the power supply terminal is 0.5V.

In the embodiments of the present application, the electrical connection may refer to both physical connection, i.e. physical contact connection, and electrical connection, for example, electrical connection implemented by any kind of field effect transistor, or other electronic components.

The logic gate circuit comprises N input ends and 1 output end, the N input ends are respectively and electrically connected with the grids of the N P-type first-class field effect transistors one by one, and the N input ends are respectively and electrically connected with the grids of the N-type second-class field effect transistors one by one, for example, the 1 st input end of the logic gate circuit is electrically connected with the grid of the 1 st first-class field effect transistor and the grid of the 1 st second-class field effect transistor, the 2 nd input end of the logic gate circuit is electrically connected with the grid of the 2 nd first-class field effect transistor and the grid of the 2 nd second-class field effect transistor, and so on, the N input end of the logic gate circuit is electrically connected with the grid of the N first-class field effect transistor and the grid of the N second-class field effect transistor. And the drains of the N first-type field effect transistors are used as the output end of the logic gate circuit.

Correspondingly, the embodiment of the application also provides a nor gate, which is specifically described below.

Referring to FIG. 2, an embodiment of a logic gate circuit is provided. In this embodiment, the logic gate circuit includes a pull-up circuit 201 and a pull-down circuit 202. The logic gate circuit may be specifically a nor gate.

The pull-up circuit 201 includes N P-type second field effect transistors connected in series, and the pull-down circuit 202 includes N-type first field effect transistors connected in parallel, where N is greater than 1. The first type of field effect transistor comprises a TFET and the second type of field effect transistor comprises a MOSFET or a FINFET.

The N P-type second field effect transistors are connected in series in the forward direction, namely in two adjacent second field effect transistors of the N P-type second field effect transistors, the source electrode of one second field effect transistor is electrically connected with the drain electrode of the other second field effect transistor. The sources of the N-type first-type field effect transistors are electrically connected and the drains of the N-type first-type field effect transistors are electrically connected.

The pull-up circuit 201 and the pull-down circuit 202 are sequentially connected in series between a power end and a Ground (GND), that is, one of two ends of the pull-up circuit 201, which is a source, is electrically connected to the power end, one of two ends of the pull-up circuit 202, which is a drain, is electrically connected to drains of the N-type first-type field effect transistors, and the sources of the N-type first-type field effect transistors are electrically connected to the Ground.

The power supply voltage input by the power supply terminal may be equal to or greater than the normal operating voltage of the first type field effect transistor and less than the normal operating voltage of the second type field effect transistor, for example, the normal operating voltages of the first type field effect transistor are all 0.5V, the normal operating voltage of the first type field effect transistor is 0.7V, and the power supply voltage input by the power supply terminal is 0.5V.

The logic gate circuit comprises N input ends and 1 output end, the N input ends are respectively and electrically connected with the grids of N-type first-class field effect transistors one by one, and the N input ends are respectively and electrically connected with the grids of N P-type second-class field effect transistors one by one, for example, the 1 st input end of the logic gate circuit is electrically connected with the grid of the 1 st first-class field effect transistor and the grid of the 1 st second-class field effect transistor, the 2 nd input end of the logic gate circuit is electrically connected with the grid of the 2 nd first-class field effect transistor and the grid of the 2 nd second-class field effect transistor, and so on, the N input end of the logic gate circuit is electrically connected with the grid of the N-th first-class field effect transistor and the grid of the N-second-class field effect transistor. And the drains of the N first-type field effect transistors are used as the output end of the logic gate circuit.

The operation of the logic gate circuit shown in fig. 1 and 2 is as follows: n input ends of the logic gate circuit respectively receive the N pulse signals, and an output end of the logic gate circuit outputs the operation results of the N pulse signals. Taking N as an example, a first input end of the logic gate circuit receives the first pulse signal, a second input end of the logic gate circuit receives the second pulse signal, an output end of the logic gate circuit outputs an operation result of the first pulse signal and the second pulse signal, when the logic gate circuit is a nand gate, the operation result is specifically a pulse signal obtained by performing a nand operation on the first pulse signal and the second pulse signal, and when the logic gate circuit is a nor gate, the operation result is specifically a pulse signal obtained by performing a nor operation on the first pulse signal and the second pulse signal.

according to the technical scheme, in the embodiment of the application, N parallel first-type field effect transistors (namely TFETs) and N series second-type field effect transistors (namely MOSFETs or FINFETs) are adopted to form the logic gate circuit. The TFET has a smaller SS value, and can normally operate when the power supply voltage is smaller, for example, when the power supply voltage is equal to 0.5V, so that the logic gate circuit has smaller power consumption. Meanwhile, the output curve (the relation interval between the output current and the output voltage) of the MOSFET or the FINFET is nonlinear, so that the driving current is large, and therefore, the pulse signal output from the output terminal of the logic gate circuit can be quickly pulled from a low level to a high level or quickly pulled from the high level to the low level, thereby solving the problem of long delay of the logic gate circuit, and specifically, reducing the delay compared with the logic gate circuit which totally adopts the TFET. Therefore, the embodiment of the application further solves the problem of long delay on the premise of ensuring low power consumption.

In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

the following describes specific structures of the nand gate and the nor gate and specific operation modes corresponding to the two structures.

in the first case, the logic gate is embodied as a nand gate.

as shown in fig. 3, the pull-up circuit 101 includes N P-type TFETs connected in parallel, and the pull-down circuit 102 includes N-type MOSFETs connected in series.

The sources of the N P-type TFETs are electrically connected and serve as a first end of the pull-up circuit 101, and the drains of the N P-type TFETs are electrically connected and serve as a second end of the pull-up circuit 101; one of the two ends of the pull-down circuit 102, which is a drain, is a first end of the pull-down circuit 102, and one of the two ends of the pull-down circuit 102, which is a source, is a second end of the pull-down circuit 102; a first terminal of the pull-up circuit 101 is electrically connected to a power source terminal, a second terminal of the pull-up circuit 101 is electrically connected to a first terminal of the pull-down circuit 102, and a second terminal of the pull-down circuit 102 is electrically connected to a ground terminal. The gates of the N-type TFETs are electrically connected to the gates of the N P-type MOSFETs one to one, and serve as N input terminals of the logic gate circuit, and the second terminal of the pull-up circuit 101 serves as an output terminal of the logic gate circuit.

When the power supply voltage inputted from the power supply terminal is greater than 0, the operation mode of the logic gate circuit shown in fig. 3 is as follows:

When an input signal of at least one input end of the N input ends of the logic gate circuit is a low-level signal, at least one TFET of the N P-type TFETs is conducted, at least one MOSFET of the N-type MOSFETs is disconnected, and an output signal of the output end is a high-level signal. For example, the input signal of M input terminals of the N input terminals of the logic gate circuit is a low level signal, wherein 1 ≦ M ≦ N, and since the M input terminals are electrically connected to the gates of the M P-type TFETs and to the gates of the M N-type MOSFETs, the M P-type TFETs are turned on and the M N-type MOSFETs are turned off, the output signal of the output terminal of the logic gate circuit is a high level signal.

when the input signals of all the input ends in the N input ends of the logic gate circuit are high-level signals, the N input ends are electrically connected with the grids of the N P-type TFETs and the grids of the N-type MOSFETs, so that the N P-type TFETs are all disconnected, the N-type MOSFETs are all conducted, the N-type MOSFETs can quickly pull the high level to the low level, and the output signals of the output ends of the logic gate circuit are low-level signals.

therefore, the logic gate circuit outputs a high level signal when the input signal of at least one input end is a low level signal, and outputs a low level signal when the input signals of all the input ends of the N input ends are high level signals, so that the NAND operation function is realized.

Since in the structure shown in fig. 3, N P-type TFETs are electrically connected to the power supply terminal, and the TFETs can normally operate when the power supply voltage input from the power supply terminal is small, for example, equal to 0.5V, the power consumption is small. Moreover, since the output curve of the TFET is linear and the output curve of the MOSFET is non-linear, which means that the MOSFET has a large driving capability, the pulse signal output from the logic gate circuit can be quickly pulled from a high level to a low level, so that the delay of the logic gate circuit is short. It has been found through experiments that the delay of the nand gate shown in fig. 3 can be reduced by about 85% compared with a logic gate circuit using TFET as a whole.

In addition, since the capacitance value of the parasitic capacitance of the MOSFET is small, the overshoot voltage and the undershoot voltage of the logic gate circuit are small. Moreover, the TFET is compatible with a CMOS manufacturing process, so that the manufacturing cost of the logic gate circuit is low and the manufacturing period is short.

The specific structures of the two-input nand gate and the three-input nand gate are described below.

as shown in fig. 4, when N is 2, the pull-up circuit 101 includes a first field effect transistor T1 and a second field effect transistor T2, wherein T1 and T2 are both P-type TFETs, and the pull-down circuit 102 includes a third field effect transistor M1 and a fourth field effect transistor M2, wherein M1 and M2 are both N-type MOSFETs.

The source of T1 and the source of T2 are electrically connected and connected to a power supply terminal, the drain of T1 and the drain of T2 are electrically connected and connected to the drain of M1, the source of M1 is electrically connected to the drain of M2, and the source of M2 is electrically connected to a ground terminal. The gate of T1 and the gate of M1 are electrically connected and serve as the input terminal ina of the logic gate circuit, the gate of T2 and the gate of M2 are electrically connected and serve as the input terminal inb of the logic gate circuit, and the connection end of the drain of T1 and the drain of M1 serves as the output terminal out of the logic gate circuit.

The working mode of the logic gate circuit is as follows:

When the input terminal ina inputs a low level signal and the input terminal inb inputs a low level signal, T1 and T2 are turned on, M1 and M2 are turned off, and thus the pull-up circuit 101 is turned on, the pull-down circuit 102 is turned off, and the output terminal out outputs a high level signal.

when the input terminal ina inputs a low level signal and the input terminal inb inputs a high level signal, T1 and M2 are turned on, T2 and M1 are turned off, and thus the pull-up circuit 101 is turned on, the pull-down circuit 102 is turned off, and the output terminal out outputs a high level signal.

When the input terminal ina inputs a high level signal and the input terminal inb inputs a low level signal, T2 and M1 are turned on, T1 and M2 are turned off, and thus the pull-up circuit 101 is turned on, the pull-down circuit 102 is turned off, and the output terminal out outputs a high level signal.

When the input terminal ina inputs a high level signal and the input terminal inb inputs a high level signal, M1 and M2 are turned on, T1 and T2 are turned off, so that the pull-up circuit 101 is turned off, the pull-down circuit 102 is turned on, M1 and M2 can rapidly pull the high level to the low level, and the output terminal out outputs a low level signal. It can be seen that the delays can be effectively reduced when the output of the logic gate circuit is switched from high to low by M1 and M2.

Therefore, the logic gate circuit shown in fig. 4 can realize the nand operation function.

As shown in fig. 5, when N is 3, the pull-up circuit 101 includes a fifth field effect transistor T3, a sixth field effect transistor T4, and a seventh field effect transistor T5, where T3, T4, and T5 are P-type TFETs; the pull-down circuit 102 includes an eighth field effect transistor M3, a ninth field effect transistor M4, and a tenth field effect transistor M5, wherein M3, M4, and M5 are N-type MOSFETs.

the source of T3, the source of T4 and the source of T5 are electrically connected and connected with a power supply terminal, the drain of T3, the drain of T4 and the drain of T5 are electrically connected and connected with the drain of M3, the source of M3 is electrically connected with the drain of M4, the source of M4 is electrically connected with the drain of M5, and the source of M5 is electrically connected with a ground terminal.

The gate of T3 and the gate of M3 are electrically connected and serve as the input terminal ina of the logic gate circuit, the gate of T4 and the gate of M4 are electrically connected and serve as the input terminal inb of the logic gate circuit, the gate of T5 and the gate of M5 are electrically connected and serve as the input terminal inc of the logic gate circuit, and the connection end of the drain of T3 and the drain of M3 serves as the output terminal out of the logic gate circuit.

The logic gate circuit shown in fig. 5 can implement the nand operation function, and the specific operation mode may refer to the operation modes of the logic gate circuit shown in fig. 3 and fig. 4, which are not described herein again.

The logic gate circuits shown in fig. 3, 4 and 5 may be electrically connected to an inverter circuit, respectively, to form an and gate. For example, as shown in fig. 6, the inverter circuit includes an input terminal and an output terminal, the input terminal of the inverter circuit is electrically connected to the drains of the N TFETs, and the output terminal of the inverter circuit serves as the output terminal of the logic gate circuit. The inverter circuit may include a twenty-first field effect transistor and a twenty-second field effect transistor as shown in fig. 6. The source electrode of the twenty-first field effect transistor is electrically connected with a power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with a ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit. Wherein the twenty-first and twenty-second field effect transistors may be TFETs, MOSFETs or FINFETs. .

In the second case, the logic gate circuit is embodied as a nor gate.

As shown in fig. 7, the pull-down circuit 202 includes N-type TFETs connected in parallel, and the pull-up circuit 201 includes N P-type MOSFETs connected in series.

the sources of the N-type TFETs are electrically connected and serve as a first end of the pull-down circuit 202, and the drains of the N-type TFETs are electrically connected and serve as a second end of the pull-down circuit 202; one of the two ends of the pull-up circuit 201, which is a drain, is a first end of the pull-up circuit 201, and one of the two ends of the pull-up circuit 201, which is a source, is a second end of the pull-up circuit 201; a first terminal of the pull-down circuit 202 is electrically connected to a ground terminal, a second terminal of the pull-down circuit 202 is electrically connected to a first terminal of the pull-up circuit 201, and a second terminal of the pull-up circuit 201 is electrically connected to a power supply terminal.

When the power supply voltage inputted from the power supply terminal is greater than 0, the operation mode of the logic gate circuit shown in fig. 7 is as follows:

When the input signal of at least one input end of the N input ends of the logic gate circuit is a high-level signal, at least one MOSFET of the N P-type MOSFETs is disconnected, at least one TFET of the N-type TFETs is connected, and the output signal of the output end is a low-level signal. For example, the input signal of M input terminals of the N input terminals of the logic gate circuit is a high level signal, where 1 ≦ M ≦ N, and since the M input terminals are electrically connected to the gates of the M P-type MOSFETs and the gates of the M N-type TFETs, the M P-type MOSFETs are turned off, the M N-type TFETs are turned on, and the output signal of the output terminal of the logic gate circuit is a low level signal.

When the input signals of all the input ends in the N input ends are low-level signals, the N input ends are electrically connected with the grids of the N P-type MOSFETs and the grids of the N-type TFETs, so that the N P-type MOSFETs are all turned on, the N-type TFETs are all turned off, the N P-type MOSFETs can quickly pull the low level to the high level, and the output signals of the output ends of the logic gate circuit are high-level signals.

Therefore, the logic gate circuit outputs a low-level signal when the input signal of at least one input end is a high-level signal, and outputs a high-level signal when the input signals of all the input ends of the N input ends are low-level signals, so that the function of NOR operation is realized.

Since the TFET can normally operate when the power supply voltage input at the power supply terminal is small, for example, equal to 0.5V in the structure shown in fig. 7, power consumption is small. Moreover, since the output curve of the TFET is linear and the output curve of the MOSFET is non-linear, which means that the MOSFET has a large driving capability, the pulse signal output from the logic gate circuit can be pulled quickly from the low level to the high level, so that the logic gate circuit delay is short. It has been found through experiments that the nor gate shown in fig. 7 can reduce the delay by about 75% compared with a logic gate circuit using TFET as a whole.

In addition, since the capacitance value of the parasitic capacitance of the MOSFET is low, the overshoot voltage and the undershoot voltage of the logic gate circuit are small. Moreover, the TFET is compatible with a CMOS manufacturing process, so that the manufacturing cost of the logic gate circuit is low and the manufacturing period is short.

The specific structures of the two-input nor gate and the three-input nor gate are described below, respectively.

As shown in fig. 8, when N is 2, the pull-down circuit 202 includes an eleventh field effect transistor T6 and a twelfth field effect transistor T7, wherein T6 and T7 are both N-type TFETs, and the pull-up circuit 201 includes a thirteenth field effect transistor M6 and a fourteenth field effect transistor M7, wherein M6 and M7 are both P-type MOSFETs.

the source of T6 and the source of T7 are electrically connected and connected to ground, the drain of T6 and the drain of T7 are electrically connected and connected to the drain of M6, the source of M6 is electrically connected to the drain of M7, and the source of M7 is electrically connected to a power supply terminal. The gate of T6 and the gate of M6 are electrically connected and serve as the input terminal ina of the logic gate circuit, the gate of T7 and the gate of M7 are electrically connected and serve as the input terminal inb of the logic gate circuit, and the connection end of the drain of T6 and the drain of M6 serves as the output terminal of the logic gate circuit.

The working mode of the logic gate circuit is as follows:

When the input terminal ina inputs a high level signal and the input terminal inb inputs a high level signal, T6 and T7 are turned on, M6 and M7 are turned off, so that the pull-down circuit 202 is turned on, the pull-up circuit 201 is turned off, and the output terminal outputs a low level signal.

When the input terminal ina inputs a low level signal and the input terminal inb inputs a high level signal, T7 and M6 are turned on, T6 and M7 are turned off, so that the pull-down circuit 202 is turned on, the pull-up circuit 201 is turned off, and the output terminal outputs a low level signal.

when the input terminal ina inputs a high level signal and the input terminal inb inputs a low level signal, T6 and M7 are turned on, T7 and M6 are turned off, so that the pull-down circuit 202 is turned on, the pull-up circuit 201 is turned off, and the output terminal outputs a low level signal.

When the input terminal ina inputs a low-level signal and the input terminal inb inputs a low-level signal, M6 and M7 are turned on, T6 and T7 are turned off, so that the pull-down circuit 202 is turned off, the pull-up circuit 201 is turned on, M6 and M7 can quickly pull the low level to the high level, and the output terminal outputs a high-level signal. It can be seen that the delays can be effectively reduced when the output of the logic gate circuit is switched from low to high by M6 and M7.

Therefore, the logic gate circuit shown in fig. 8 can realize the nor operation function.

As shown in fig. 9, when N is 3, the pull-down circuit 202 includes a fifteenth field effect transistor T8, a sixteenth field effect transistor T9 and a seventeenth field effect transistor T10, wherein T8, T9 and T10 are N-type TFETs; the pull-up circuit 201 includes eighteenth, nineteenth, and twentieth field effect transistors M8, M9, and M10, wherein M8, M9, and M10 are P-type MOSFETs.

the source of T8, the source of T9 and the source of T10 are electrically connected and are electrically connected to ground, the drain of T8, the drain of T9 and the drain of T10 are electrically connected and are electrically connected to the drain of M8, the source of M8 is electrically connected to the drain of M9, the source of M9 is electrically connected to the drain of M10, and the source of M10 is electrically connected to a power supply terminal.

The grid of T8 and the grid of M8 are electrically connected and are used as the input terminal ina of the logic gate circuit, the grid of T9 and the grid of M9 are electrically connected and are used as the input terminal inb of the logic gate circuit, the grid of T10 and the grid of M10 are electrically connected and are used as the input terminal inc of the logic gate circuit, and the connection end of the drain of T8 and the drain of M8 is used as the output terminal of the logic gate circuit.

The logic gate circuit shown in fig. 9 can implement the nor operation function, and the specific operation mode may refer to the operation modes of the logic gate circuits shown in fig. 7 and fig. 8, which are not described herein again.

the logic gate circuits shown in fig. 7, 8 and 9 may be electrically connected to an inverter circuit to form an or gate. For example, as shown in fig. 10, the inverter circuit includes an input terminal and an output terminal, the input terminal of the inverter circuit is electrically connected to the drains of the N TFETs, and the output terminal of the inverter circuit serves as the output terminal of the logic gate circuit. Among them, the inverter circuit may include a twenty-first field effect transistor and a twenty-second field effect transistor as shown in fig. 10. The source electrode of the twenty-first field effect transistor is electrically connected with a power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with a ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit. Wherein the twenty-first and twenty-second field effect transistors may be TFETs, MOSFETs or FINFETs.

In fig. 3 to 10, a symbol M indicates a MOSFET, and a symbol T indicates a TFET.

The above-described embodiment of the logic gate circuit includes N first type field effect transistors connected in parallel and N second type field effect transistors connected in series. In addition, the logic gate circuit may also adopt a symmetrical structure with the above-mentioned embodiment, that is, the logic gate circuit includes N series-connected first field effect transistors and N parallel-connected second field effect transistors, which will be described in detail below.

In the embodiments of the present application, another embodiment of a logic gate circuit is provided. The logic gate circuit of this embodiment may be a nand gate. The logic gate circuit includes: a pull-up circuit and a pull-down circuit;

The pull-up circuit comprises N P-type second field effect transistors connected in parallel, wherein the sources of the N P-type second field effect transistors are electrically connected, the sources of the N P-type second field effect transistors are electrically connected with a power supply end, and the drains of the N P-type second field effect transistors are electrically connected; the pull-down circuit comprises N-type first-class field effect transistors which are connected in series, wherein in two adjacent first-class field effect transistors of the N-type first-class field effect transistors, the source electrode of one first-class field effect transistor is electrically connected with the drain electrode of the other first-class field effect transistor; one end of the two ends of the pull-down circuit, which is a drain electrode, is electrically connected with the drain electrodes of the N P-type second field effect transistors, and one end of the two ends of the pull-down circuit, which is a source electrode, is electrically connected with the ground end; the first type of field effect transistor comprises a TFET and the second type of field effect transistor comprises a MOSFET or a FINFET; n is greater than 1;

The gates of the N P-type second field effect transistors are electrically connected with the gates of the N-type first field effect transistors one by one and are used as N input ends of the logic gate circuit, and the drains of the N P-type second field effect transistors are used as the output ends of the logic gate circuit.

The circuit structure of the logic gate circuit in this embodiment is symmetrical to the circuit structure of the logic gate circuit shown in fig. 1, and therefore, the relevant content of the logic gate circuit is described with reference to the corresponding embodiment in fig. 1, and is not described herein again.

According to the technical scheme, in the embodiment of the application, N TFETs connected in series and N MOSFETs or FINFETs connected in parallel are adopted to form a logic gate circuit. The SS value of the TFET is small, and the TFET can normally run when the power supply voltage is small, so that the power consumption is small, and the power consumption of the logic gate circuit is small.

In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

optionally, when the input signal of at least one of the N input terminals is a low level signal, at least one of the N P-type second field effect transistors is turned on, at least one of the N-type first field effect transistors is turned off, and the output signal of the output terminal is a high level signal;

When the input signals of all the input ends in the N input ends are high level signals, the N P type second type field effect transistors are all disconnected, the N type first type field effect transistors are all connected, and the output signals of the output ends are low level signals.

The circuit structure of the nand gate may be symmetrical to that of the nand gate shown in fig. 3, and therefore, the related content of the nand gate is described with reference to the corresponding embodiment of fig. 3, and is not described herein again.

Alternatively, the logic gate circuit may be a two-input nand gate. The pull-up circuit comprises a first field effect transistor and a second field effect transistor, wherein the first field effect transistor and the second field effect transistor are P-type second-class field effect transistors; the pull-down circuit comprises a third field effect transistor and a fourth field effect transistor, wherein the third field effect transistor and the fourth field effect transistor are N-type first-class field effect transistors;

The source electrode of the first field effect transistor is electrically connected with the source electrode of the second field effect transistor and is electrically connected with the power supply end, the drain electrode of the first field effect transistor is electrically connected with the drain electrode of the second field effect transistor and is electrically connected with the drain electrode of the third field effect transistor, the source electrode of the third field effect transistor is electrically connected with the drain electrode of the fourth field effect transistor, and the source electrode of the fourth field effect transistor is electrically connected with the ground end;

The grid electrode of the first field effect transistor is electrically connected with the grid electrode of the third field effect transistor and serves as a first input end of the logic gate circuit, the grid electrode of the second field effect transistor is electrically connected with the grid electrode of the fourth field effect transistor and serves as a second input end of the logic gate circuit, and the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor serve as output ends of the logic gate circuit.

The circuit structure of the two-input nand gate is symmetrical to that of the nand gate shown in fig. 4, and therefore, the related content of the two-input nand gate is described with reference to the corresponding embodiment of fig. 4, and is not described herein again.

Alternatively, the logic gate circuit may be a three-input nand gate. The pull-up circuit comprises a fifth field effect transistor, a sixth field effect transistor and a seventh field effect transistor, wherein the fifth field effect transistor, the sixth field effect transistor and the seventh field effect transistor are P-type second-class field effect transistors; the pull-down circuit comprises an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor, wherein the eighth field effect transistor, the ninth field effect transistor and the tenth field effect transistor are N-type first-type field effect transistors;

A source electrode of the fifth field effect transistor, a source electrode of the sixth field effect transistor and a source electrode of the seventh field effect transistor are electrically connected and are electrically connected with the power supply terminal, a drain electrode of the fifth field effect transistor, a drain electrode of the sixth field effect transistor and a drain electrode of the seventh field effect transistor are electrically connected and are electrically connected with a drain electrode of the eighth field effect transistor, a source electrode of the eighth field effect transistor is electrically connected with a drain electrode of the ninth field effect transistor, a source electrode of the ninth field effect transistor is electrically connected with a drain electrode of the tenth field effect transistor, and a source electrode of the tenth field effect transistor is electrically connected with a ground terminal;

A gate of the fifth field effect transistor is electrically connected with a gate of the eighth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixth field effect transistor is electrically connected with a gate of the ninth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventh field effect transistor is electrically connected with a gate of the tenth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifth field effect transistor, a drain of the sixth field effect transistor and a drain of the seventh field effect transistor serve as output ends of the logic gate circuit.

The circuit structure of the three-input nand gate is symmetrical to that of the nand gate shown in fig. 5, and therefore, the related content of the three-input nand gate is described with reference to the corresponding embodiment of fig. 5, and is not described herein again.

Optionally, the logic gate circuit further includes an inverting circuit, wherein:

The input end of the inverter circuit is electrically connected with the drain electrodes of the N P-type second-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

Optionally, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, and the twenty-first field effect transistor and the twenty-second field effect transistor are first field effect transistors or second field effect transistors;

The source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

For the related content of the inverter circuit, please refer to the related description of the corresponding embodiment in fig. 6, which is not repeated herein.

Correspondingly, the embodiment of the application also provides an embodiment of the NOR gate.

the embodiment of the present application provides another apparatus embodiment of a logic gate circuit, and the logic gate circuit of this embodiment may be a nor gate. The logic gate circuit includes: a pull-up circuit and a pull-down circuit;

The pull-up circuit comprises N P-type first field effect transistors which are connected in series, wherein the source electrode of one first field effect transistor is electrically connected with the drain electrode of the other first field effect transistor in two adjacent first field effect transistors of the N P-type first field effect transistors; the pull-down circuit comprises N-type second field effect transistors connected in parallel, wherein the sources of the N-type second field effect transistors are electrically connected and the sources of the N-type second field effect transistors are electrically connected with a ground terminal, and the drains of the N-type second field effect transistors are electrically connected; one end of the pull-up circuit, which is a drain electrode, at the two ends is electrically connected with the drain electrodes of the N-type second-class field effect transistors, and one end of the pull-up circuit, which is a source electrode, at the two ends is electrically connected with a power supply end; the first type field effect transistor comprises a tunneling field effect transistor, and the second type field effect transistor comprises a metal-oxide-semiconductor field effect transistor or a fin type field effect transistor; n is greater than 1;

the gates of the N-type second-class field effect transistors are electrically connected with the gates of the N P-type first-class field effect transistors one by one and serve as N input ends of the logic gate circuit, and the drains of the N-type second-class field effect transistors serve as output ends of the logic gate circuit.

According to the technical scheme, in the embodiment of the application, N TFETs connected in series and N MOSFETs or FINFETs connected in parallel are adopted to form a logic gate circuit. The SS value of the TFET is small, and the TFET can normally run when the power supply voltage is small, so that the power consumption is small, and the power consumption of the logic gate circuit is small.

In addition, because the parasitic capacitance of the MOSFET or FINFET has a smaller capacitance value, the overshoot voltage and the undershoot voltage are smaller than those of a logic gate circuit that entirely employs a TFET.

Optionally, when the input signal of at least one of the N input terminals is a high level signal, at least one of the N P-type first field effect transistors is turned off, at least one of the N-type second field effect transistors is turned on, and the output signal of the output terminal is a low level signal;

when the input signals of all the input ends in the N input ends are low level signals, the N P-type first-class field effect transistors are all conducted, the N-type second-class field effect transistors are all disconnected, and the output signals of the output ends are high level signals.

the circuit structure of the nor gate is symmetrical to that of the nor gate shown in fig. 7, and therefore, the related content of the nor gate is described with reference to the corresponding embodiment of fig. 7, which is not repeated herein.

Alternatively, the logic gate circuit may be a two-input nor gate. The pull-down circuit comprises an eleventh field effect transistor and a twelfth field effect transistor, wherein the eleventh field effect transistor and the twelfth field effect transistor are N-type second-class field effect transistors; the pull-up circuit comprises a thirteenth field effect transistor and a fourteenth field effect transistor, wherein the thirteenth field effect transistor and the fourteenth field effect transistor are P-type first-type field effect transistors;

A source electrode of the eleventh field effect transistor is electrically connected with a source electrode of the twelfth field effect transistor and is electrically connected with the ground terminal, a drain electrode of the eleventh field effect transistor is electrically connected with a drain electrode of the twelfth field effect transistor and is electrically connected with a drain electrode of the thirteenth field effect transistor, a source electrode of the thirteenth field effect transistor is electrically connected with a drain electrode of the fourteenth field effect transistor, and a source electrode of the fourteenth field effect transistor is electrically connected with the power supply terminal;

A gate of the eleventh field effect transistor is electrically connected with a gate of the thirteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the twelfth field effect transistor is electrically connected with a gate of the fourteenth field effect transistor and serves as a second input end of the logic gate circuit, and a drain of the eleventh field effect transistor and a drain of the twelfth field effect transistor serve as output ends of the logic gate circuit.

The circuit structure of the two-input nor gate is symmetrical to the circuit structure of the nor gate shown in fig. 8, and therefore, the related content of the two-input nor gate is described with reference to the corresponding embodiment of fig. 8, and is not repeated here.

Alternatively, the logic gate circuit may be a three-input nor gate. The pull-down circuit comprises a fifteenth field effect transistor, a sixteenth field effect transistor and a seventeenth field effect transistor, wherein the fifteenth field effect transistor, the sixteenth field effect transistor and the seventeenth field effect transistor are N-type second-class field effect transistors; the pull-up circuit comprises an eighteenth field effect transistor, a nineteenth field effect transistor and a twentieth field effect transistor, wherein the eighteenth field effect transistor, the nineteenth field effect transistor and the twentieth field effect transistor are P-type first-type field effect transistors;

a source electrode of the fifteenth field effect transistor, a source electrode of the sixteenth field effect transistor, and a source electrode of the seventeenth field effect transistor are electrically connected and electrically connected to the ground terminal, a drain electrode of the fifteenth field effect transistor, a drain electrode of the sixteenth field effect transistor, and a drain electrode of the seventeenth field effect transistor are electrically connected and electrically connected to a drain electrode of the eighteenth field effect transistor, a source electrode of the eighteenth field effect transistor is electrically connected to a drain electrode of the nineteenth field effect transistor, a source electrode of the nineteenth field effect transistor is electrically connected to a drain electrode of the twentieth field effect transistor, and a source electrode of the twentieth field effect transistor is electrically connected to the power source;

A gate of the fifteenth field effect transistor is electrically connected with a gate of the eighteenth field effect transistor and serves as a first input end of the logic gate circuit, a gate of the sixteenth field effect transistor is electrically connected with a gate of the nineteenth field effect transistor and serves as a second input end of the logic gate circuit, a gate of the seventeenth field effect transistor is electrically connected with a gate of the twentieth field effect transistor and serves as a third input end of the logic gate circuit, and a drain of the fifteenth field effect transistor, a drain of the sixteenth field effect transistor and a drain of the seventeenth field effect transistor serve as output ends of the logic gate circuit.

The circuit structure of the three-input nor gate is symmetrical to that of the nor gate shown in fig. 9, and therefore, the relevant content of the three-input nor gate is described with reference to the corresponding embodiment of fig. 9, and is not described herein again.

Optionally, the logic gate circuit further includes an inverting circuit, wherein:

The input end of the inverter circuit is electrically connected with the drain electrodes of the N-type first-class field effect transistors, and the output end of the inverter circuit is used as the output end of the logic gate circuit.

In one possible design, the inverter circuit includes a twenty-first field effect transistor and a twenty-second field effect transistor, the twenty-first field effect transistor and the twenty-second field effect transistor being either a first type field effect transistor or a second type field effect transistor;

the source electrode of the twenty-first field effect transistor is electrically connected with the power supply end, the drain electrode of the twenty-first field effect transistor is electrically connected with the source electrode of the twenty-second field effect transistor, and the drain electrode of the twenty-second field effect transistor is electrically connected with the ground end; and the grid electrode of the twenty-first field effect transistor and the grid electrode of the twenty-second field effect transistor are electrically connected and used as the input end of the inverter circuit, and the drain electrode of the twenty-first field effect transistor is used as the output end of the inverter circuit.

For the related content of the inverter circuit, please refer to the related description of the corresponding embodiment in fig. 10, which is not repeated herein.

referring to fig. 11, an embodiment of a logic operation method is further provided in the present application. The method of this embodiment is used in the logic gate circuit in any of the embodiments described above.

The method comprises the following steps:

1101: n pulse signals are respectively input to N input ends of the logic gate circuit.

1102: and obtaining the operation result of the N pulse signals output by the output end of the logic gate circuit.

The logic gate circuit can be a nand gate circuit, a nor gate circuit, an and gate circuit or a not gate circuit, so that the operation result of the nand operation, the nor operation, the and gate operation or the not gate operation of the N pulse signals output by the output end of the logic gate circuit.

For the structure and operation of the logic gate circuit, please refer to the related description of any of the above embodiments, which is not repeated herein.

The embodiment of the application also provides an embodiment of the integrated circuit. The integrated circuit 1201 includes the logic gates of any of the embodiments described above. The integrated circuit can be obtained by integrating the pull-up circuit and the pull-down circuit through any semiconductor process. For example, the integrated circuit shown in fig. 12 includes a pull-up circuit 101 and a pull-down circuit 102, and the integrated circuit shown in fig. 13 includes a pull-up circuit 201 and a pull-down circuit 202.

For the structure and the working process of the logic gate circuit, reference is made to the related description of any of the above embodiments, and details are not repeated here.

the terms "first," "second," "third," or "fourth," and the like in the description and in the claims of the present application and in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

it is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

in addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.