阅读说明：本技术 多芯片定时对准共同参考信号 (Multi-chip timing alignment common reference signal ) 是由 迈克尔·迪恩·沃梅克 简·迈克尔·史蒂文森 理查德·威廉·埃泽尔 于 2019-06-03 设计创作，主要内容包括：本主题技术通过使输出上升边缘与输入上升边缘同时发生来除去锁相环(PLL)中的延迟源。本主题技术使用与输入参考信号路径中相同的电路配置和偏置电路尽可能接近地将沿着输入参考信号路径经历的延迟量复制到PLL。例如,包含复制电路的定时对准电路将补偿延迟添加到负反馈环路信号,以使反馈环路延迟与参考路径延迟相匹配。估计参考信号路径的延迟并将其添加到复制电路中。这两条路径的延迟特性彼此抵消,使得输入参考信号和反馈环路信号的相位在PLL的输入处变为锁相。(The subject technology removes a delay source in a phase-locked loop (PLL) by having an output rising edge occur simultaneously with an input rising edge. The subject technology replicates the amount of delay experienced along the input reference signal path to the PLL as closely as possible using the same circuit configuration and bias circuitry as in the input reference signal path. For example, a timing alignment circuit including a replica circuit adds a compensation delay to the negative feedback loop signal to match the feedback loop delay to the reference path delay. The delay of the reference signal path is estimated and added to the replica circuit. The delay characteristics of the two paths cancel each other out so that the phases of the input reference signal and the feedback loop signal become phase locked at the input of the PLL.)