阅读说明：本技术 多芯片定时对准共同参考信号 (Multi-chip timing alignment common reference signal ) 是由 迈克尔·迪恩·沃梅克 简·迈克尔·史蒂文森 理查德·威廉·埃泽尔 于 2019-06-03 设计创作，主要内容包括：本主题技术通过使输出上升边缘与输入上升边缘同时发生来除去锁相环(PLL)中的延迟源。本主题技术使用与输入参考信号路径中相同的电路配置和偏置电路尽可能接近地将沿着输入参考信号路径经历的延迟量复制到PLL。例如,包含复制电路的定时对准电路将补偿延迟添加到负反馈环路信号,以使反馈环路延迟与参考路径延迟相匹配。估计参考信号路径的延迟并将其添加到复制电路中。这两条路径的延迟特性彼此抵消,使得输入参考信号和反馈环路信号的相位在PLL的输入处变为锁相。(The subject technology removes a delay source in a phase-locked loop (PLL) by having an output rising edge occur simultaneously with an input rising edge. The subject technology replicates the amount of delay experienced along the input reference signal path to the PLL as closely as possible using the same circuit configuration and bias circuitry as in the input reference signal path. For example, a timing alignment circuit including a replica circuit adds a compensation delay to the negative feedback loop signal to match the feedback loop delay to the reference path delay. The delay of the reference signal path is estimated and added to the replica circuit. The delay characteristics of the two paths cancel each other out so that the phases of the input reference signal and the feedback loop signal become phase locked at the input of the PLL.)

1. An apparatus for timing alignment of a common reference signal, the apparatus comprising:

a reference divider circuit coupled to an input terminal and configured to receive a reference frequency signal and to generate a divided reference signal along a reference signal path from the input terminal;

A phase-locked loop (PLL) circuit configured to receive the divided reference signal and generate a divided feedback signal along a feedback signal path to an input of the PLL and output an oscillation signal to an output terminal; and

A timing alignment circuit coupled to the PLL circuit and configured to adjust a phase of the divided feedback signal by a predetermined delay amount proportional to a path delay amount of a reference signal path through the reference divider circuit for aligning the divided reference signal with the divided feedback signal having the adjusted phase, the timing alignment circuit including one or more delay components that replicate the path delay amount of the reference signal path through the reference divider circuit.

2. the apparatus of claim 1, wherein the PLL circuit comprises:

An error detector circuit configured to receive the divided reference signal and the divided feedback signal to provide an error signal;

A Voltage Controlled Oscillator (VCO) circuit configured to receive the error signal and generate an output oscillation signal based on the error signal; and

A feedback divider circuit configured to receive the output oscillator signal from the VCO circuit and to generate a divided feedback signal along the feedback signal path to the error detector circuit,

wherein the timing alignment circuit is coupled to an input of the error detector circuit.

3. The apparatus of claim 2, further comprising:

An output frequency divider circuit coupled to an output of the VCO circuit and configured to generate a frequency divided output timing signal based on an output oscillation signal from the VCO circuit,

wherein a path delay from the output of the VCO circuit through the output frequency divider circuit corresponds to a path delay from the output of the VCO circuit through a feedback signal path of the feedback frequency divider circuit.

4. The apparatus of claim 3, wherein:

The reference divider circuit coupled to the input terminal and a first input of the error detector circuit, the reference divider circuit providing a reference signal path between the input terminal and the first input of the error detector circuit,

the feedback divider circuit coupled to an output of the VCO circuit and an input of the timing alignment circuit, the feedback divider circuit providing a divided feedback signal through a feedback signal path between the output of the VCO circuit and the input of the timing alignment circuit,

the output frequency divider circuit is coupled to the output terminal and provides an output oscillation signal through an output frequency divider signal path between the output of the VCO circuit and the output terminal, an

The timing alignment circuit compensates for delays of the reference signal path and timing differences between the feedback signal path and the output divider signal path.

5. The apparatus of claim 4, wherein the timing alignment circuit is coupled between the input terminal and a first input of the error detector circuit.

6. The apparatus of claim 4, wherein the timing alignment circuit is coupled between an output of the VCO circuit and a second input of the error detector circuit.

7. The apparatus of claim 6, wherein the timing alignment circuit is coupled to an output of the feedback divider circuit and a second input of the error detector circuit.

8. The apparatus of claim 6, wherein the timing alignment circuit is coupled to an output of the VCO circuit and an input of the feedback divider circuit.

9. The apparatus of claim 2, wherein the PLL circuit comprises:

a multiplexer coupled to the feedback divider circuit and the timing alignment circuit, wherein the multiplexer is configured to bypass the delay compensated output signal from the timing alignment circuit and pass the divided feedback signal to the error detector circuit based on a received selection signal.

10. the apparatus of claim 1, wherein each of the one or more delay components in the timing alignment circuit corresponds to one of a plurality of delay components along the reference signal path.

11. The apparatus of claim 1, further comprising:

A bias circuit coupled to the reference divider circuit and the timing alignment circuit and configured to drive the same bias signal to the reference divider circuit and the timing alignment circuit.

12. The apparatus of claim 11, wherein the bias circuit is configured to drive the bias signals to respective control terminals of one or more delay components of the timing alignment circuit, wherein each bias signal is driven by a first bias voltage corresponding to a second bias voltage sent to a respective delay component on the reference signal path.

13. A clock generation system, comprising:

a reference divider circuit coupled to the input terminal and configured to receive a reference frequency signal and to generate a divided reference signal;

A phase-locked loop (PLL) circuit configured to receive the divided reference signal and generate a divided feedback signal along a feedback signal path to an input of the PLL and output an oscillation signal to an output terminal;

A plurality of output frequency dividers configured to receive an output oscillation signal and to generate respective divided output timing signals that are a function of the frequency of the reference frequency signal; and

A timing alignment circuit coupled to the PLL circuit and configured to adjust a phase of the divided feedback signal by a predetermined delay amount proportional to a path delay amount of a reference signal path through the reference divider circuit for aligning the divided reference signal with the divided feedback signal having the adjusted phase, the timing alignment circuit including one or more delay components that replicate the path delay amount of the reference signal path through the reference divider circuit.

14. The clock generation system of claim 13, wherein the PLL circuit comprises:

An error detector circuit configured to receive the divided reference signal and the divided feedback signal to provide an error signal;

a Voltage Controlled Oscillator (VCO) circuit configured to receive the error signal and generate an output oscillation signal; and

A feedback divider circuit configured to receive the output oscillation signal from the VCO circuit and to generate a divided feedback signal along a negative feedback path to the error detector circuit,

Wherein the timing alignment circuit is coupled to an input of the error detector circuit.

15. The clock generation system of claim 14 wherein the respective path delay from the output of the VCO circuitry through each of the plurality of output dividers corresponds to the path delay from the output of the VCO circuitry through the feedback divider circuitry.

16. the clock generation system of claim 14, wherein the timing alignment circuit is coupled between the input terminal and the first input of the error detector circuit.

17. The clock generation system of claim 14 wherein the timing alignment circuit is coupled between the output of the VCO circuitry and the second input of the error detector circuit.

18. The clock generation system of claim 17, wherein the timing alignment circuit is coupled to an output of the feedback divider circuit and a second input of the error detector circuit.

19. The clock generation system of claim 17 wherein the timing alignment circuit is coupled to an output of the VCO circuitry and an input of the feedback divider circuitry.

20. An apparatus for timing alignment of a common reference signal, the apparatus comprising:

Means for receiving a reference frequency signal at an input terminal and providing a divided reference signal along a reference signal path from the input terminal;

Means for receiving the divided frequency reference signal and generating a divided frequency feedback signal along a feedback signal path, and outputting an oscillation signal to an output terminal; and

means for replicating a path delay amount from the input terminal through a reference signal path having one or more delay elements arranged along a feedback signal path, adjusting a phase of the divided feedback signal by a predetermined delay amount that is proportional to the path delay amount through the reference signal path and aligning the divided reference signal with the divided feedback signal having the adjusted phase such that a transition edge of the divided feedback signal is aligned with a transition edge of the divided reference signal.

21. an apparatus for timing alignment of a common reference signal, the apparatus comprising:

Means for receiving a reference frequency signal at an input terminal along a reference signal path from the input terminal;

means for providing a frequency divided feedback signal along a feedback signal path based on a received reference frequency signal and providing an output oscillation signal to an output terminal; and

Means for replicating a path delay amount along a feedback signal path having one or more delay elements arranged along a reference signal path, adjusting a phase of the reference frequency signal by a predetermined delay amount proportional to the path delay amount through the feedback signal path, and aligning the reference frequency signal with a divided feedback signal having the adjusted phase such that a transition edge of the reference frequency signal is aligned with a transition edge of the divided feedback signal.

22. The apparatus of claim 21, further comprising:

means for providing a divided reference signal along the reference signal path based on a received reference frequency signal, wherein the means for providing a divided feedback signal is based on the divided reference signal.

23. The apparatus of claim 21, wherein the reference frequency signal is communicated to an input of a phase locked loop through the reference signal path at a same frequency as a frequency received at the input terminal.

Technical Field

This description relates generally to clock generation systems and, more particularly, to multi-chip timing alignment of common reference signals.

Background

Synchronization of the timing signals is desirable, for example, when aligning data sampling events in an analog-to-digital converter driven by a clock signal. Similarly, synchronization of the desired timing signals phase-aligns the different carrier radio waves to implement constructive interference. There are many systems that desire-either because of the number of clock signals they use or the spatial separation between the clock devices therein-to align multiple clock devices to a common time or phase.

Summary of The Invention

the subject technology provides for removing timing misalignment in a Phase Locked Loop (PLL) using clock distribution. Removing the misalignment allows the output rising edge to occur simultaneously with the input rising edge. In this regard, any offset between the input rising edge and the output rising edge may be reduced by adding a delay to the feedback loop of the PLL, such that the increased delay pushes/pulls the output rising edge to align with the input rising edge. The subject technology replicates the amount of delay experienced along the input reference signal path to the PLL as closely as possible using the same circuit configuration and bias circuitry as in the input reference signal path. For example, a timing alignment circuit including a replica circuit adds a compensation delay to the negative feedback loop signal to match the feedback loop delay to the reference path delay. The delay of the reference signal path is estimated and added to the replica circuit. The delay characteristics of the two paths cancel each other out so that the phases of the input reference signal and the feedback loop signal become phase locked at the input of the PLL.

In accordance with an embodiment of the present disclosure, an apparatus for timing aligning a common reference signal is provided. The apparatus includes a reference divider circuit coupled to an input terminal and configured to receive a reference frequency signal and to generate a divided reference signal along a reference signal path from the input terminal. The apparatus includes a phase-locked loop (PLL) circuit configured to receive the divided reference signal and generate a divided feedback signal along a feedback signal path to an input of the PLL, and output an oscillation signal to an output terminal. The apparatus includes a timing alignment circuit coupled to the PLL circuit and configured to adjust a phase of the divided feedback signal by a predetermined delay amount proportional to a path delay amount of a reference signal path through the reference divider circuit for aligning the divided reference signal with the divided feedback signal having the adjusted phase. In some aspects, a timing alignment circuit includes one or more delay components that replicate an amount of path delay through a reference signal path of the reference divider circuit.

According to an embodiment of the present disclosure, a clock generation system includes a reference divider circuit coupled to an input terminal and configured to receive a reference frequency signal and to generate a divided reference signal. The clock generation system includes a phase-locked loop (PLL) circuit configured to receive the frequency-divided reference signal and generate a frequency-divided feedback signal along a feedback signal path to an input of the PLL, and output an oscillation signal to an output terminal. The clock generation system includes a plurality of output frequency dividers configured to receive the output oscillator signal and to respectively generate a divided output timing signal that is a function of the frequency of the reference frequency signal. The clock generation system includes a timing alignment circuit coupled to the PLL circuit and configured to adjust a phase of the divided feedback signal by a predetermined delay amount proportional to a path delay amount of a reference signal path through the reference divider circuit for aligning the divided reference signal with the divided feedback signal having the adjusted phase. In some aspects, the timing alignment circuit includes one or more delay components that replicate an amount of path delay through a reference signal path of the reference divider circuit.

in accordance with an embodiment of the present disclosure, an apparatus for timing aligning a common reference signal is provided. The apparatus includes means for receiving a reference frequency signal at an input terminal and providing a divided reference signal along a reference signal path from the input terminal. The apparatus includes means for receiving the divided reference signal and generating a divided feedback signal along a feedback signal path, and outputting an oscillation signal to an output terminal. The apparatus includes means for replicating a path delay amount from the input terminal through a reference signal path having one or more delay elements arranged along a feedback signal path, adjusting a phase of the divided feedback signal by a predetermined delay amount that is proportional to the path delay amount through the reference signal path and aligning the divided reference signal with the divided feedback signal having the adjusted phase such that a transition edge of the divided feedback signal is aligned with a transition edge of the divided reference signal.