阅读说明：本技术 一种星载fpga单粒子功能中断率的快速预估方法 (Rapid estimation method for single-particle function interruption rate of satellite-borne FPGA ) 是由 赵海涛 郑玉展 贾蒙杨 熊笑 郑晋军 张翼 胡雪梅 曹锦� 于 2019-08-07 设计创作，主要内容包括：本发明提供一种星载FPGA单粒子功能中断率的快速预估方法,包括如下步骤：计算目标FPGA和已在轨运行的相似FPGA在任务轨道环境条件下、考虑资源使用情况后的单粒子翻转率P<Sub>M1</Sub>和P<Sub>M2</Sub>,计算结构复杂度系数；利用在轨相似FPGA数据,计算未采取防护措施情况下,目标FPGA在轨由于单粒子软错误导致功能异常的概率P<Sub>F1</Sub>；确定目标FPGA采取防护措施后的防护系数β<Sub>p</Sub>,计算目标FPGA功能中断率；在目标FPGA功能中断率不满足设计要求时,进行改进,直至目标FPGA功能中断率满足设计要求。本发明对评价航天器系统级功能中断率、快速发现单粒子防护薄弱环节并快速改进设计具有重要意义。(The invention provides a method for quickly estimating the interruption rate of a single event function of a satellite-borne FPGA (field programmable gate array), which comprises the following steps of: calculating the single event turnover rate P of a target FPGA and an on-orbit running similar FPGA under the condition of a task track environment and after considering the resource use condition M1 And P M2 Calculating a structural complexity coefficient; calculating the probability P of abnormal function of the target FPGA on-orbit due to single event soft error under the condition of not taking protective measures by using on-orbit similar FPGA data F1 (ii) a Determining a protection coefficient beta of a target FPGA after taking a protection measure p Calculating the function interruption rate of the target FPGA; and when the target FPGA function interruption rate does not meet the design requirement, improving until the target FPGA function interruption rate meets the design requirement. The invention evaluates the system-level function interruption rate of the spacecraft and quickly discovers single event protectionIt is of great significance to protect weak links and quickly improve design.)

1. A method for rapidly estimating the interruption rate of a single event function of a satellite-borne FPGA is characterized by comprising the following steps:

calculating the single event turnover rate P of a target FPGA and an on-orbit running similar FPGA under the condition of a task track environment and after considering the resource use condition_M1And P_M2Calculating the structural complexity coefficient beta_C＝P_M1/P_M2；

Calculating the probability P of abnormal function of similar FPGA due to single event soft error under the condition of no protection of the similar FPGA on-orbit by using the similar FPGA data which operates on-orbit_F2；

Calculating the probability P of abnormal function of the target FPGA on-orbit due to single-event soft error under the condition of not taking protective measures_F1；

P_F1＝P_F2β_C

Determining a protection coefficient beta of a target FPGA after adopting a protection measure_pCalculating the function interruption rate of the target FPGA as follows:

P_O＝P_F1β_P

And when the target FPGA function interruption rate does not meet the design requirement, improving the protection measure until the target FPGA function interruption rate meets the design requirement.

2. The method for rapidly estimating the single-event functional interrupt rate of the satellite-borne FPGA according to claim 1, wherein the single-event turnover rate of the target FPGA and the similar FPGA which is operated in an on-orbit mode is calculated by adopting the following method:

1) Obtaining the single event turnover rate P of the configuration area of the FPGA device_bS1Single event upset ratio P of storage area_bR1；

2) Determining the resource occupancy rate A of the storage area according to the current design state of the FPGA and the resource occupancy conditions of the storage area and the configuration area respectively_S1% and resource occupancy rate of configuration area A_R1％；

3) Calculating the single event turnover rate of the FPGA device after the resource use condition is considered;

P_M1＝P_bS1A_S1％+P_bR1A_R1％。

3. The method for rapidly estimating the single event function interruption rate of the satellite-borne FPGA according to claim 2, wherein when the single event upset rates of the storage areas and the configuration areas of the target FPGA and the similar FPGA which is operated on the orbit can be obtained by adopting the following modes:

And adding ground irradiation test examination to obtain a sigma-LET curve of the FPGA device, fitting to obtain a saturation cross section and an LET threshold, and calculating to obtain the single-particle turnover rate of the FPGA by combining an LET energy spectrum of a target orbit condition.

Technical Field

The invention relates to a rapid estimation method for a single event function interruption rate of a satellite-borne FPGA, belonging to the technical field of spacecraft design.

Background

The FPGA is widely applied to spacecrafts such as satellites and the like and is responsible for completing various key functions. For example, the navigation satellite navigation processor uses a large-capacity FPGA to implement navigation signal processing, and plays a decisive role in navigation downlink signal service. A transponder of a remote sensing and communication satellite realizes measurement and control data processing by applying a large-capacity FPGA, and is a core part for realizing the functions of measuring and controlling uplink and downlink. However, the spacecraft inevitably suffers from the bombardment of high-energy protons and heavy ions of earth radiation zone, galaxy space line and solar space line, which causes the single event effect of the FPGA, resulting in single event soft errors such as logic disorder, instruction error, functional interruption and logic abnormity, thereby affecting the normal function and service of the spacecraft.

In order to reflect the capability of the FPGA for resisting single-particle soft errors, indexes such as single-particle turnover rate and the like are generally adopted as technical indexes of the FPGA device for space navigation, the indexes are collectively called inherent indexes, and the inherent indexes are only related to the inherent design and manufacturing process of the device. The indexes can be provided by FPGA manufacturers or obtained by an application party through methods such as tests and the like. When the FPGA is applied to a spacecraft, the probability of the actual occurrence of an abnormality of the FPGA varies from product to product due to the difference in conditions such as the orbit environment, resource usage, working state, completed tasks and functions, peripheral system design, and the like in which the FPGA is located. In some important applications, the satellite-borne FPGA usually adopts various single event protection measures such as triple modular redundancy, timing refresh, and the like, and the probability of the function abnormality caused by the single event is further reduced. Therefore, the capability of evaluating the actual single-particle soft error resistance of the FPGA must consider the on-orbit application condition and the protection design condition. The functional interruption rate is used as a measurement index and is defined as the probability of the FPGA that the device has abnormal functions (data errors, functional interruption and the like) due to single-event soft errors (single-event upset, single-event transient and the like). The index reflects the actual single event resistance of the satellite-borne FPGA under the on-orbit application condition and is also a necessary input condition in the calculation of the function interruption probability of the spacecraft system level.

Currently, there are two basic approaches of testing and simulating to obtain the probability of single event functional interruption of the FPGA. The method for testing is to carry out the irradiation test of the heavy ion accelerator, and has the defects of limited time of the heavy ion accelerator, complex test system, higher test cost and certain destructiveness, and the heavy ion test method is not suitable for complex subsystems and whole satellite systems. The simulation method is to establish an analysis model by analyzing the circuit netlist, and the method has the defects that the model is complex in calculation and cannot quickly predict the single event functional interruption.

Due to the limitations of the current technology and the consideration of factors such as progress and cost, the single event function interruption rate obtained by means of testing and simulation is not applied to the spacecraft engineering development in a large range, and particularly at the product design stage, an effective technical means is not available to quickly estimate the single event function interruption rate of an FPGA device, so that the conformity of device and system design cannot be judged in time and design iteration cannot be carried out.

Disclosure of Invention

The technical problem solved by the invention is as follows: the method utilizes similar device data, takes basic data such as FPGA intrinsic single event upset rate and the like as input, and utilizes factors such as resource occupation coefficient, structure complexity coefficient, protection coefficient and the like to establish a single event function interruption rate calculation model, thereby realizing the rapid estimation of the FPGA single event function interruption rate, and having important significance for evaluating the spacecraft system-level function interruption rate, rapidly finding single event protection weak links and rapidly improving the design.

The technical solution of the invention is as follows:

A method for rapidly estimating the interruption rate of a single event function of a satellite-borne FPGA comprises the following steps:

Calculating the single event turnover rate P of a target FPGA and an on-orbit running similar FPGA under the condition of a task track environment and after considering the resource use condition_M1And P_M2calculating the structural complexity coefficient beta_C＝P_M1P_M2；

Calculating the probability P of abnormal function of similar FPGA due to single event soft error under the condition of no protection of the similar FPGA on-orbit by using the similar FPGA data which operates on-orbit_F2；

calculating the probability P of abnormal function of the target FPGA on-orbit due to single-event soft error under the condition of not taking protective measures_F1；

P_F1＝P_F2β_C

Determining a protection coefficient beta of a target FPGA after adopting a protection measure_pCalculating the function interruption rate of the target FPGA as follows:

P_O＝P_F1β_P

And when the target FPGA function interruption rate does not meet the design requirement, improving the protection measure until the target FPGA function interruption rate meets the design requirement.

Further, the single event upset probability of the target FPGA and the similar FPGA which operates on the orbit is calculated by adopting the following method:

1) Obtaining the single event turnover rate P of the configuration area of the FPGA device_bS1Single event upset ratio P of storage area_bR1；

2) Determining the resource occupancy rate A of the storage area according to the current design state of the FPGA and the resource occupancy conditions of the storage area and the configuration area respectively_S1% 1 and resource occupancy rate of configuration area A_R1％；

3) Calculating the single event turnover rate of the FPGA device after the resource use condition is considered;

P_M1＝P_bS1A_S1％+P_bR1A_R1％。

Further, the single-event upset rate of the storage area and the registration area of the target FPGA and the similar FPGA which operates in the on-orbit can be obtained by adopting the following method:

And adding ground irradiation test examination to obtain a sigma-LET curve of the FPGA device, fitting to obtain a saturation cross section and an LET threshold, and calculating to obtain the single-particle turnover rate of the FPGA by combining an LET energy spectrum of a target orbit condition.

advantageous effects

(1) the method not only considers the effect of taking single-particle protection measures on the inherent design and application design of the FPGA device, but also considers the possibility of the propagation of single-particle soft errors to final function abnormality of the FPGA under the actual application condition, and objectively accords with the on-orbit application scene of the FPGA device.

(2) The inventive method requires little design cost. The method provided by the invention does not need software and hardware support, and can obtain the result by using the existing on-orbit statistical data and ground irradiation test data of similar FPGA through simple comparison analysis and a simple calculation formula.

(3) The method can quickly obtain the estimated value. The method does not need to carry out test preparation and implementation test, does not need programming and a large amount of simulation, and can obtain relatively accurate results only through simple analysis and mathematical calculation, thereby having important significance for quickly judging the single-particle protection design conformity of the spacecraft in the design stage and carrying out design iteration.

Through the single-particle function interruption rate calculation model, the rapid evaluation of the probability of device function interruption caused by single-particle soft errors after the FPGA takes single-particle protection measures is realized.

Drawings

FIG. 1 is a block flow diagram of the method of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

The invention relates to a method for rapidly estimating the single event function interruption rate of a satellite-borne FPGA (field programmable gate array). the method takes similar device data and basic data of the FPGA as input, and obtains factors such as a resource occupation coefficient, a structure complexity coefficient, a protection coefficient and the like through analysis, thereby realizing rapid estimation of the single event function interruption rate of the FPGA and supporting rapid verification of the design conformity and improvement of a system.

As shown in fig. 1, a flow chart of the method of the present invention is shown, and the specific implementation steps are as follows:

1) obtaining basic technical indexes of a target FPGA device, including a single event upset rate index P in a target track environment_b1Or the single-event turnover rate P of the configuration area_bS1Single event upset ratio P of storage area_bR1。

imported aerospace-grade FPGA devices typically give a single event upset threshold and a single event upset rate (usually expressed in times/day) under specific spatial environmental conditions. When the single-particle upset threshold value and the single-particle upset rate are absent, ground irradiation test examination can be added to obtain a sigma-LET curve of the FPGA device, parameter values such as a saturation section and an LET threshold value are obtained through fitting, and the LET energy spectrum of the target track condition is combined to further calculate and obtain the single-particle upset rate prediction of the FPGA.

2) determining a storage area resource occupation coefficient beta according to the current design state of the target FPGA and the resource occupation conditions (without protection design resources) of the storage area and the configuration area respectively_RR1And a resource occupation coefficient beta of the configuration area_RS1Or determining the resource occupation coefficient beta according to the whole resource occupation condition (without protection design resources)_R1。

assuming that the resource occupancy rate of the FPGA configuration area is A_S1percent (no protection design resource) and the occupancy rate of the storage area resource is A_R1Percent (no protection design resource), the resource occupation coefficient beta of the configuration area_RS1＝A _S1Percent, storage area resource occupation coefficient beta_RR1＝A_R1％。

4) Calculating the single event turnover rate P of the target FPGA device after the resource occupancy rate correction_M1。

P_M1＝P_bS1A_S1％+P_bR1A_R1％

5) Investigating the on-orbit flight data to obtain phasesProbability P of function interruption caused by single-particle soft error under on-orbit non-protection condition of FPGA-like device_F2。

Under the on-orbit non-protection condition, the FPGA device does not take special single-particle soft error protection measures in application design, and the measures comprise but are not limited to triple modular redundancy, timing refreshing and the like.

If a similar FPGA device is abnormal for y times due to single-event soft error within x years, the function is abnormal

The similar FPGA in the invention refers to an FPGA with basically consistent device design method and manufacturing process and similar application scene and function, and generally represents the situation that the same series of FPGAs produced by the same manufacturer are applied to the same type of satellite.

6) Obtaining basic technical indexes of similar FPGA devices, and calculating to obtain the single event turnover rate P after the correction of the similar FPGA devices according to the methods of the steps 2), 3) and 4)_M2。

P_M2＝P_bS2A_S2％+P_bR2A_R2％

7) comparing the structural complexity of the target FPGA and the similar FPGA to determine a structural complexity coefficient beta_C。β_CCalculated by the following formula

Assuming that the single-particle turnover rate of the corrected target FPGA obtained by calculation according to the steps 1) to 4) is r₁The single event turnover rate after the correction of the similar FPGA is r every day₂The times/day, then

8) calculating the probability P of abnormal function of the target FPGA due to single-event soft error under the condition of not taking protective measures by using similar FPGA data_F1。

P_F1＝P_F2β_C

9) Obtaining effect comparison data before and after the same type of FPGA takes the same single particle protection measure, and determining a protection coefficient beta_P. The protection coefficient is defined as the ratio of the probability of single-particle soft errors after single-particle soft error protection measures such as triple modular redundancy, timing refreshing and the like are adopted when the FPGA is applied to a satellite-borne product to the probability of single-particle soft errors without the single-particle soft error protection measures. Beta is a_PThe smaller the size, the better the protection. The data can refer to ground irradiation test data of FPGA devices of the same model, and also can refer to simulation data obtained by the FPGA devices of the same model through fault injection and the like. Without confidence, beta_PConservative values of available data should be taken.

10) Introducing a protection coefficient on the basis of 8) to obtain the interruption rate P of the single event function of the FPGA_OIs composed of

P_O＝P_F1β_P

11) Interrupting the single event function of the FPGA by a ratio P_OIf the estimated value is higher than the required value (namely, the technical requirement is not met), further single event protection design measures need to be taken and estimation is carried out again.