阅读说明：本技术 减少用于训练的资源的存储器器件 (Memory device with reduced resources for training ) 是由 文炳模 吉汎涌 金知慧 于 2021-03-11 设计创作，主要内容包括：公开了一种存储器器件,包括：第一电源引脚,在第一电源区域中并且配置为接收第一电源电压；数据引脚,配置为发送或接收数据信号,所述数据引脚被布置在均包括所述第一电源区域的第一区中和第二区中；控制引脚,配置为发送或接收控制信号,在所述第一区中和在所述第二区中；第二电源引脚,在所述第一区和所述第二区之间的第二电源区域中,并且配置为接收与所述第一电源电压不同的第二电源电压；以及地引脚,在所述第二电源区域中并且配置为接收地电压。(Disclosed is a memory device including: a first power supply pin in a first power supply region and configured to receive a first power supply voltage; a data pin configured to transmit or receive a data signal, the data pin being disposed in a first region and a second region each including the first power supply region; a control pin configured to transmit or receive a control signal in the first zone and in the second zone; a second power supply pin in a second power supply region between the first region and the second region and configured to receive a second power supply voltage different from the first power supply voltage; and a ground pin in the second power supply region and configured to receive a ground voltage.)

1. A memory device, comprising:

a first power supply pin in a first power supply region and configured to receive a first power supply voltage;

a data pin configured to transmit or receive a data signal, the data pin being in a first region and a second region, the first region and the second region each including a portion of the first power supply region;

a control pin configured to transmit or receive a control signal, the control pin being in the first region and the second region;

a second power supply pin configured to receive a second power supply voltage different from the first power supply voltage in a second power supply region between the first region and the second region; and

a ground pin in the second power supply region and configured to receive a ground voltage,

wherein the data pins and the control pins are divided into a plurality of pin groups, and

the training values corresponding to each of the plurality of pin groups are based on training for at least one of the pins of each of the plurality of pin groups.

2. The memory device of claim 1, wherein the control pin of a first pin group of the plurality of pin groups comprises: a pin configured to receive a write data strobe signal, an

The control pins of a second pin group of the plurality of pin groups do not include: a pin configured to receive the write data strobe signal.

3. The memory device of claim 2, wherein the memory device is configured to: samples of the data signal and the control signal are received based on the write data strobe signal.

4. The memory device of claim 2, wherein the memory device is configured to: the data signal and the control signal are received based on the write data strobe signal.

5. The memory device of claim 2, further comprising:

a plurality of repeater circuits configured to transmit the write data strobe signal to a region where the second pin group is located.

6. The memory device of claim 5, wherein a first repeater circuit and a second repeater circuit of the plurality of repeater circuits are arranged to be symmetrical with respect to the first power supply area.

7. The memory device of claim 2, wherein the control pins of the second pin group comprise pins configured to transmit or receive at least one of: an error correction code signal, a data parity signal, a data bus invert signal, an error severity signal, and a data error signal.

8. The memory device of claim 1, wherein the first supply voltage is less than the second supply voltage.

9. The memory device of claim 1, wherein the pins of each of the plurality of pin groups are arranged symmetrically about the first power region.

10. The memory device of claim 1, wherein each of the plurality of pin groups comprises at least eight pins.

11. A memory device, comprising:

a first pin group including a first data pin configured to transmit or receive a first data signal and a first control pin configured to transmit or receive a first control signal;

a second pin group including a second data pin configured to transmit or receive a second data signal and a second control pin configured to transmit or receive a second control signal;

a first power supply region provided in each of a first area in which the first pin group is located and a second area in which the second pin group is located, wherein a pin configured to receive a first power supply voltage is located in the first power supply region, an

A second power supply region between the first region and the second region, a pin configured to receive a second power supply voltage different from the first power supply voltage and a pin configured to receive a ground voltage being located in the second power supply region,

wherein a first training value corresponding to the first pin group is based on training for one of the first data pin and the first control pin, and a second training value corresponding to the second pin group is based on training for one of the second data pin and the second control pin.

12. The memory device of claim 11, wherein the pins of the first pin group and the pins of the second pin group are arranged symmetrically about the second power region.

13. The memory device of claim 11, further comprising: a third control pin configured to receive a write data strobe signal,

wherein each of the first pin group and the second pin group does not include: a pin configured to receive the write data strobe signal.

14. The memory device of claim 13, further comprising:

a first receiver group configured to receive the first data signal and the first control signal transmitted through the first pin group;

a second receiver group configured to receive the second data signal and the second control signal transmitted through the second pin group; and

a write data strobe tree configured to perform a first transmission of a first internal write data strobe signal to the first receiver group through a repeater circuit on a first path and a second transmission of a second internal write data strobe signal to the second receiver group through a repeater circuit on a second path, the first and second transmissions being based on the write data strobe signal transmitted through the third control pin,

wherein the first receiver group is configured to sample the first data signal and the first control signal based on a transition timing of the first internal write data strobe signal, and

the second receiver group is configured to sample the second data signal and the second control signal based on a transition timing of the second internal write data strobe signal.

15. The memory device according to claim 14, wherein the repeater circuit on the first area among the repeater circuits on the first path and the repeater circuit on the second area among the repeater circuits on the second path are arranged symmetrically with respect to the second power supply area.

16. The memory device of claim 11, wherein a circuit layout on the first region is the same as a circuit layout.

17. A memory device, comprising:

a write data strobe pin configured to receive a write data strobe signal;

a first pin group configured to receive a first data signal sampled based on the write data strobe signal; and

a second pin group configured to receive a second data signal sampled based on the write data strobe signal,

wherein a first training value corresponding to the first pin group is based on training for a first pin of the first pin group, and

a second training value corresponding to the second pin group is based on training for a second pin of the second pin group.

18. The memory device of claim 17, further comprising:

a first receiver pin set configured to receive the first data signal transmitted over the first pin set;

a second set of receiver pins configured to receive the second data signal transmitted over the second set of pins; and

a write data strobe tree circuit configured to perform a first transmission of a first internal write data strobe signal to the first set of receiver pins through a repeater circuit on a first path and a second transmission of a second internal write data strobe signal to the second set of receiver pins through a repeater circuit on a second path, the first transmission and the second transmission being based on the write data strobe signal transmitted through the write data strobe pins,

wherein the first set of receiver pins is configured to sample the first data signal based on a transition timing of the first internal write data strobe signal, and

the second set of receiver pins is configured to sample the second data signal based on a transition timing of the second internal write data strobe signal.

19. The memory device of claim 18, wherein the receivers of the first group of receiver pins are arranged at a same distance from a last one of the repeater circuits located on the first path.

20. The memory device of claim 18, wherein signal lines that transmit the first data signal from the first pin set to the first receiver pin set are the same length.

Technical Field

Some example embodiments relate to semiconductor devices, and more particularly, to memory devices that reduce resources used for training.

Background

Electronic devices such as smart phones, graphics accelerators, and/or AI accelerators process data using memory devices such as Dynamic Random Access Memory (DRAM). As the amount of data to be processed by electronic devices increases, high capacity and high bandwidth memory devices are required. In particular, in order to process data at high speed, the use of a memory device providing wide input/output of a multi-channel interface method, such as a High Bandwidth Memory (HBM), has increased.

The memory device may exchange data with an external device (e.g., a host device or a memory controller) through a plurality of data pins to provide high bandwidth. Since the number of data pins of the memory device increases, the external device can process data at high speed. However, when training is performed for each pin, resources for training may increase as the number of data pins increases.

Disclosure of Invention

Some example embodiments provide a memory device capable of performing training on a plurality of data pins per group to reduce training resources for the plurality of data pins.

According to some example embodiments, a memory device includes: a first power supply pin in a first power supply region and configured to receive a first power supply voltage; a data pin configured to transmit or receive a data signal, the data pin being in a first region and a second region, the first region and the second region each including a portion of the first power supply region; a control pin configured to transmit or receive a control signal, the control pin being in the first region and the second region; a second power supply pin configured to receive a second power supply voltage different from the first power supply voltage in a second power supply region between the first region and the second region; and a ground pin in the second power supply region and configured to receive a ground voltage, the data pin and the control pin are divided into a plurality of pin groups, and a training value corresponding to each of the plurality of pin groups is based on training performed for at least one of the pins of each of the plurality of pin groups.

According to some example embodiments, a memory device includes: a first pin group including a first data pin configured to transmit or receive a first data signal and a first control pin configured to transmit or receive a first control signal; a second pin group including a second data pin configured to transmit or receive a second data signal and a second control pin configured to transmit or receive a second control signal; and a first power supply region provided in each of a first area where the first pin group is located and a second area where the second pin group is located. A pin configured to receive a first power supply voltage is located in the first power supply region; a second power supply region located among the first region and the second region, a pin configured to receive a second power supply voltage different from the first power supply voltage and a pin configured to receive a ground voltage, and a first training value corresponding to the first pin group is based on training performed for one of the first data pin and the first control pin, and a second training value corresponding to the second pin group is based on training performed for one of the second data pin and the second control pin.

According to some example embodiments, a memory device includes: a write data strobe pin configured to receive a write data strobe signal; a first pin group configured to receive a first data signal sampled based on the write data strobe signal; and a second pin group configured to receive a second data signal sampled based on the write data strobe signal. A first training value corresponding to the first pin group is based on training for a first pin in the first pin group, and a second training value corresponding to the second pin group is based on training for a second pin of the second pin group.

According to some example embodiments, a memory system includes: a memory device configured to: receiving a write data strobe signal through a write data strobe pin, receiving a first data signal through a pin of a first pin group corresponding to the write data strobe pin, and receiving a second data signal through a pin of a second pin group corresponding to the write data strobe pin; and a memory controller circuit configured to perform a first transmission of the first data signal to the memory device based on a first transmission timing determined by training for one pin of the first pin group and a second transmission of the second data signal to the memory device based on a second transmission timing determined by training for one pin of the second pin group, the first transmission and the second transmission being performed while the write data strobe signal is transmitted to the memory device.

According to some example embodiments, a memory system includes: a memory device configured to: receiving a write data strobe signal through a write data strobe pin, transmitting a first data signal through a first pin group corresponding to the write data strobe pin, and transmitting a second data signal through a second pin group corresponding to the write data strobe pin; and memory controller circuitry configured to: the method includes transmitting the write data strobe signal to the memory device, sampling the first data signal received from the memory device based on a first reception timing determined by training for one pin of the first pin group, and sampling the second data signal received from the memory device based on a second reception timing determined by training for one pin of the second pin group.

According to some example embodiments, a memory system includes: an interlayer substrate; a system-on-chip stacked on the interposer substrate and including at least one processor; and a memory device stacked on the interposer substrate and including (a) a buffer die configured to communicate a first signal with the system-on-chip through a first bump group and communicate a second signal with the system-on-chip through a second bump group, and (b) a plurality of core dies stacked on the buffer die through silicon-through electrodes and each including a memory cell. The system-on-chip is configured to generate the first signal with the buffer die based on a first training result determined by training for a first bump of the first bump group, and is configured to generate the second signal with the buffer die based on a second training result determined by training for a second bump of the second bump group.

According to some example embodiments, a Dynamic Random Access Memory (DRAM) device includes: a clock terminal configured to receive a clock signal; a data clock terminal configured to receive a data clock signal; and m cell blocks coupled to the data clock signal, each of the m cell blocks being on the monolithic silicon substrate and in shifted and/or mirrored relation to the other cell blocks, and each cell block including n data terminals configured to receive n data signals, respectively, m and n being integers greater than or equal to three. Each of the m cell blocks is configured to perform data bus training affecting a timing window between the data clock signal and a representative data signal, and the representative data signal is a representative data signal of n data signals in the cell block on which the data bus training is performed.

Drawings

Some example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram illustrating a memory system according to some example embodiments of the inventive concepts;

FIG. 2 is a flow chart illustrating example operations of the memory system of FIG. 1;

FIG. 3 is a diagram illustrating an example of a read training operation and a write training operation of the memory system of FIG. 1;

FIG. 4 is an example block diagram of the memory device of FIG. 3;

FIG. 5 is a flow chart illustrating an example of a read training operation of the memory controller of FIG. 3;

FIG. 6 is a flow chart illustrating an example of a write training operation of the memory controller of FIG. 3;

FIG. 7 is a block diagram schematically illustrating the memory system of FIG. 3;

FIG. 8 is a timing diagram illustrating an example of sampling data signals by the memory device of FIG. 7;

fig. 9 is a diagram showing an example configuration of the memory device of fig. 7;

FIG. 10 is a block diagram schematically illustrating the memory system of FIG. 3;

FIG. 11 is a timing diagram illustrating an example of the memory device of FIG. 10 sending data signals;

fig. 12 is a diagram showing an example configuration of the memory device of fig. 10;

fig. 13 is a block diagram illustrating a stacked memory device according to some example embodiments of the inventive concepts;

FIG. 14 is a block diagram illustrating an embodiment of the buffer die of FIG. 13;

FIG. 15 illustrates an example pin diagram of pins included in the stacked memory device of FIG. 13;

FIG. 16 illustrates an example configuration of a WDQS tree corresponding to the pin diagram of FIG. 15;

fig. 17 is a diagram illustrating a semiconductor package according to some example embodiments of the inventive concepts;

fig. 18 is a diagram illustrating a semiconductor package according to some example embodiments of the inventive concepts; and

fig. 19 is a block diagram illustrating a computing system according to some example embodiments of the inventive concepts.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention.

Fig. 1 is a block diagram illustrating a memory system according to some example embodiments of the inventive concepts. Referring to fig. 1, a memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control the overall operation of the memory device 200. For example, the memory controller 100 may control the memory device 200 to output data from the memory device 200 and/or to store data in the memory device 200. For example, memory controller 100 may be implemented as part of a system on a chip (SoC), although example embodiments are not limited thereto.

Memory controller 100 may include host interface circuitry 110, training controller 120, and registers 130. The host interface circuit 110 may generate a clock signal CK and transmit the clock signal CK to the memory device 200. The clock signal CK may be a signal periodically switching between a high level and a low level. The host interface circuit 110 can transmit a command/address signal CA including a command CMD and/or an address ADD to the memory device 200 based on the transition timing of the clock signal CK. The command/address signals CA may be transmitted to the memory device 200 through a plurality of signal lines.

The host interface circuit 110 may generate and transmit a write data strobe signal WDQS to the memory device 200. The write data strobe signal WDQS may be or correspond to a signal that periodically transitions between at least two levels (e.g., between a high level and a low level). The host interface circuit 110 may transmit a DATA signal DQ including DATA DATA to the memory device 200 based on the transition timing of the write DATA strobe signal WDQS. The data signal DQ may be transmitted to the memory device 200 through a plurality of signal lines.

The host interface circuit 110 may receive a read data strobe signal RDQS from the memory device 200. The read data strobe signal RDQS may be or correspond to a signal that periodically transitions between at least two levels (e.g., a high level and a low level). The host interface circuit 110 may receive the data signal DQ and the sampled data signal DQ from the memory device 200 based on the transition timing of the read data strobe signal RDQS. Thus, the host interface circuit 110 may obtain DATA from the DATA signal DQ.

The training controller 120 may control training operations for the memory device 200. The training controller 120 may determine the training value through training. For example, the training controller 120 may determine a transmission timing of each of the data signals DQ transmitted by the host interface circuit 110, and may determine a reception timing of each of the data signals DQ received by the host interface circuit 110. Accordingly, transmission timing information and reception timing information about the data signal DQ can be generated. Here, the transmission timing is/corresponds to a timing at which the host interface circuit 110 transmits the DATA signal DQ including the DATA to the memory device 200, and a time (or timing) at which the DATA is transmitted to the memory device 200 may vary according to the transmission timing. The reception timing is/corresponds to timing at which the host interface circuit 110 samples the data signals DQ received from the memory device 200, and the time (or timing) at which each of the data signals DQ is sampled may vary according to the reception timing.

The training controller 120 may be implemented in hardware including analog circuitry and/or digital circuitry, and/or may be implemented in software including a plurality of instructions executed by a Central Processing Unit (CPU) within the memory controller 100.

The register 130 may store a training value generated by the training controller 120. For example, the register 130 may store transmission timing information and reception timing information generated through training.

In some example embodiments, after training, the host interface circuit 110 may transmit the data signal DQ based on the transmission timing information stored in the register 130 and may receive the data signal DQ based on the reception timing information stored in the register 130. Specifically, the host interface circuit 110 may adjust the transmission and/or reception time of the data signal DQ according to the transmission timing information and/or the reception timing information. For example, the host interface circuit 110 may delay the transmission time of each of the data signals DQ according to transmission timing information about the data signals DQ. In this case, the time to transmit the DATA included in the DATA signal DQ to the memory device 200 may be delayed. The host interface circuit 110 may delay the reception time of the data signal DQ according to the reception timing information. In this case, the time of the DATA included in the DATA signal DQ obtained from the memory controller 100 may be delayed.

The memory device 200 may, for example, operate partially or completely under the control of the memory controller 100. For example, the memory device 200 may output stored data and/or may store data provided from the memory controller 100 under the control of the memory controller 100.

Memory device 200 may include memory interface circuitry 210 and memory banks 220. The memory interface circuit 210 may receive a clock signal CK from the memory controller 100. The memory interface circuit 210 may receive command/address signals CA from the memory controller 100. The memory interface circuit 210 may sample the command/address signal CA based on the transition timing (e.g., rising edge and/or falling edge) of the clock signal CK. Thus, the memory interface circuit 210 can obtain the command CMD and/or the address ADD included in the command/address signal CA.

Fig. 1 illustrates a command CMD and an address ADD being transmitted from the memory controller 100 to the memory device 200 through the same channel (e.g., a command/address signal CA), but the present invention is not limited thereto. For example, commands CMD and addresses ADD may be sent from the memory controller 100 to the memory device 200 using different channels.

The memory interface circuit 210 may receive a write data strobe signal WDQS from the memory controller 100. The memory interface circuit 210 may receive data signals DQ from the memory controller 100. The memory interface circuit 210 may sample the data signal DQ based on the transition timing (e.g., rising and/or falling edges) of the write data strobe signal WDQS. Thus, the memory interface circuit 210 may obtain DATA from the DATA signal DQ.

The memory interface circuit 210 may generate the read data strobe signal RDQS and may transmit the read data strobe signal RDQS to the memory controller 100. The read data strobe signal RDQS may be a signal that periodically transitions between a high level and a low level. In some example embodiments, the memory interface circuit 210 may generate the read data strobe signal RDQS based on a write data strobe signal WDQS received from the memory controller 100. The memory interface circuit 210 may transmit the data signal DQ to the memory controller 100 based on the transition timing of the write data strobe signal WDQS. Thus, the data signal DQ may be timing aligned with an edge of the read data strobe signal RDQS and transmitted to the memory controller 100. However, example embodiments are not limited thereto, and the memory interface circuit 210 may generate the read data strobe signal RDQS based on the clock signal CK and transmit the data signal DQ to the memory controller 100.

In some example embodiments, the frequency of each of the write data strobe signal WDQS and the read data strobe signal RDQS may be twice (double) the frequency of the clock signal CK. For example, the frequency of the clock signal CK may be 1.6GHz, and the frequency of each of the write data strobe signal WDQS and the read data strobe signal RDQS may be 3.2 GHz. However, example embodiments are not limited thereto, and the frequency of each of the write data strobe signal WDQS and the read data strobe signal RDQS may be N times the frequency of the clock signal CK (N is a natural number greater than or equal to two).

The memory interface circuit 210 may generate a control signal iCTRL based on a command CMD and an address ADD received from the memory controller 100, and may provide the control signal iCTRL to the memory bank 220. For example, the control signal iCTRL may include a row address and/or a column address.

The bank 220 may include a plurality of memory cells connected to word lines and bit lines. For example, each of the plurality of memory cells may be or correspond to a Dynamic Random Access Memory (DRAM) cell, e.g., a one transistor/one capacitor DRAM cell. In this case, host interface circuit 110 and memory interface circuit 210 may transmit input/output signals based on at least one standard such as Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), wide I/O, High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), and the like. However, example embodiments are not limited thereto, and each of the plurality of memory cells may be various types of memory cells such as a resistive ram (rram) cell.

The bank 220 may write DATA to or read DATA from the memory cells in response to the control signal iCTRL. Although not shown in fig. 1, the memory bank 220 may further include a row decoder, a column decoder, and sense amplifiers for write operations and/or read operations.

As described above, the memory controller 100 and the memory device 200 may transmit and receive the data signal DQ based on the transmission timing and the reception timing determined by training. However, example embodiments are not limited thereto. For example, in addition to passing through the training data signal DQ, the training controller 120 may determine the transmit timing and/or receive timing of each input/output signal transmitted or received based on the clock signal CK, the write data strobe signal WDQS, and/or the read data strobe signal RDQS. For example, the training controller 120 may determine a transmission timing and/or a reception timing of command/address signals CA and various control signals (not shown) (e.g., Data Bus Inversion (DBI), Data Parity (DPAR), etc.) transmitted and/or received between the memory controller 100 and the memory device 200. Hereinafter, some example embodiments will be described in detail based on the data signal DQ for convenience of description, but example embodiments are not limited thereto, and the embodiments described below may be applied to respective input/output signals including the command/address signal CA.

FIG. 2 is a flow chart illustrating example operations of the memory system of FIG. 1. Referring to fig. 1 and 2, the memory system 10 may perform initialization in operation S11. For example, when memory system 10 is powered up, memory controller 100 and memory device 200 may perform initialization according to a variable (or alternatively, predetermined) method. During initialization, the memory controller 100 may supply a power supply voltage to the memory device 200, perform various initial setting operations, and read necessary information from the memory device 200.

In operation S12, the memory system 10 may perform a read training operation. For example, in order to optimize or improve signal integrity or a DATA eye pattern of the DATA received from the memory device 200, the memory controller 100 may determine a reception timing of the DATA signal DQ and generate the reception timing information.

In operation S13, the memory system 10 may perform a write training operation. For example, in order to optimize or improve the signal integrity or data eye pattern of data DAT transmitted to the memory device 200, the memory controller 100 may determine the transmission timing of the data signal DQ and generate the transmission timing information.

After performing the initialization or training operations of operations S11 through S13 described above, the memory system 10 may perform a normal operation in operation S14. For example, the memory controller 100 may obtain the DATA by sampling the DATA signal DQ received from the memory device 200 based on the reception timing determined according to the read training operation. The memory controller 100 may transmit the data signal DQ to the memory device 200 based on the transmission timing determined according to the write training operation.

In some example embodiments, the memory system 10 may determine the transmission timing of the command/address signal CA by performing training on the command/address signal CA before operation S12. In some example embodiments, prior to operation S12, memory system 10 performs training on the write data strobe signal WDQS such that the transition timing of clock signal CK and the transition timing of write data strobe signal WDQS are aligned.

FIG. 3 is a diagram illustrating an example of a read training operation and a write training operation of the memory system of FIG. 1. Referring to fig. 3, the memory device 200 may include a write data strobe pin W _ P, a read data strobe pin R _ P, and a data pin D _ P. The memory controller 100 may transmit a write data strobe signal WDQS to the memory device 200 through a write data strobe pin W _ P and receive a read data strobe signal RDQS from the memory device 200 through a read data strobe pin R _ P. The memory controller 100 may transmit a data signal DQ to the memory device 200 through the data pin D _ P and/or may receive the data signal DQ from the memory device 200.

The data pin D _ P of the memory device 200 may be divided into a first pin group PG1 and a second pin group PG 2. Each of the first and second pin groups PG1 and PG2 may include at least two data pins (e.g., at least or exactly eight data pins). For example, the first pin group PG1 may include a first data pin D _ P1 and a second data pin D _ P2, and the second pin group PG2 may include a third data pin D _ P3 and a fourth data pin D _ P4. For example, the first data pin D _ P1 and the second data pin D _ P2 may be disposed adjacent to each other, and the third data pin D _ P3 and the fourth data pin D _ P4 may be disposed adjacent to each other. The memory controller 100 may transmit first to fourth data signals DQ1 to DQ4 to the memory device 200 or receive first to fourth data signals DQ1 to DQ4 from the memory device 200 through the first to fourth data pins D _ P1 to D _ P4.

Memory controller 100 may store group information related to pins of memory device 200. For example, the memory controller 100 may store information on the data pins D _ P included in the first and second pin groups PG1 and PG 2. For example, the group information associated with the pins may be variable and/or predetermined by a standard. For example, group information related to the pins may be stored in the register 130 of FIG. 1.

The memory controller 100 may perform training for each pin group. For example, the memory controller 100 may determine the first transmission timing TT1 corresponding to the first pin group PG1 by performing a write training operation on the first pin group PG1, and determine the second transmission timing TT2 corresponding to the second pin group PG2 by performing a write training operation on the second pin group PG 2. The determined transmission timings TT1 and TT2 may be stored in the registers 130 corresponding to the first pin group PG1 and the second pin group PG2, respectively. For example, the transmission timing of the data pins D _ P included in one pin group may be determined identically or in the same manner and/or at the same time. For example, the memory controller 100 may determine the first reception timing RT1 corresponding to the first pin group PG1 by performing a read training operation on the first pin group PG1, and determine the second reception timing RT2 corresponding to the second pin group PG2 by performing a read training operation on the second pin group PG 2. The determined reception timings RT1 and RT2 may be stored in the registers 130 corresponding to the first pin group PG1 and the second pin group PG2, respectively. For example, the reception timing of the data pins D _ P included in one pin group may be determined identically, e.g., in the same manner and/or at the same time. Thus, the transmission timing and the reception timing can be determined for each pin group.

According to some example embodiments, the training operation for a particular pin of the memory device 200 refers to an operation of determining an expected (e.g., optimal) transmission timing of a signal transmitted to the particular pin and/or an operation of determining an expected (e.g., optimal) reception timing (i.e., expected, e.g., optimal sampling timing) of a signal received through the particular pin.

In a write operation after training, the memory controller 100 may transmit the first data signal DQ1 and the second data signal DQ2 to the memory device 200 based on the first transmission timing TT1 and the write data strobe signal WDQS, and may transmit the third data signal DQ3 and the fourth data signal DQ4 to the memory device 200 based on the second transmission timing TT 2. The memory device 200 may sample the first through fourth data signals DQ 1-DQ 4 based on the write data strobe signal WDQS.

In a read operation after training, the memory device 200 may transmit the first through fourth data signals DQ 1-DQ 4 to the memory controller 100 along with the read data strobe signal RDQS. The memory controller 100 may sample the first data signal DQ1 and the second data signal DQ2 using the read strobe signal RDQS based on the first reception timing RT1, and may sample the third data signal DQ3 and the fourth data signal DQ4 based on the second reception timing RT 2.

Fig. 3 illustrates that the data pin D _ P is divided into two pin groups PG1 and PG2, but example embodiments are not limited thereto. For example, the data pins D _ P may be divided into three or more pin groups.

As described above, according to some example embodiments of the inventive concepts, training may be performed for each set of data pins D _ P. In this case, the memory controller 100 can store the transmission timing and the reception timing for each group without having to store (e.g., separately store) the transmission timing and the reception timing for each of the data pins D _ P. Accordingly, when training is performed for each set of data pins D _ P, the speed can be increased and/or the capacity of the register 130 for storing the transmission timing and the reception timing can be reduced as compared to when training is performed (e.g., separately performed) for each data pin D _ P. Accordingly, resources for training can be reduced.

Fig. 4 is an example block diagram of the memory device of fig. 3. Referring to fig. 3 and 4, the memory device 200 may include a first pin group PG1, a second pin group PG2, and a write data strobe pin W _ P, and may further include a first circuit block 201 and a second circuit block 202. The first circuit block 201 may receive the first data signal DQ _1 through the first pin group PG1 and may receive the write data strobe signal WDQS through the write data strobe pin W _ P. The second circuit block 202 may receive the second data signal DQ _2 through the second pin group PG2 and may receive the write data strobe signal WDQS through the write data strobe pin W _ P. For example, the first and second circuit blocks 201 and 202 may operate based on one write data strobe signal WDQS.

The first circuit block 201 may sample the first data signal DQ _1 based on the write data strobe signal WDQS. In this case, the first data signal DQ _1 may be transmitted by the memory controller 100 based on a training value (e.g., the first transmission timing TT 1). The second circuit block 202 may sample the second data signal DQ _2 based on the write data strobe signal WDQS. In this case, the second data signal DQ _2 may be transmitted by the memory controller 100 based on a training value (e.g., the second transmission timing TT 2).

In some example embodiments, each of the first circuit block 201 and the second circuit block 202 may include a phase comparator. Each of the first and second circuit blocks 201 and 202 may compare phases of the write data strobe signal WDQS and the data signal received through the data pin through a phase comparator during training for the data pin. For example, the phase comparison result may be generated by a phase comparator by sampling the data signal based on the write data strobe signal WDQS. The memory controller 100 may determine a training value for the data pin based on the result of the phase comparison. For example, the memory controller 100 may transmit data signals to the memory device 200 based on various timings. The memory controller 100 may receive phase comparison results corresponding to the respective timings from the memory device 200. The memory controller 100 may determine the training values such that the timing window between the write data strobe signal WDQS and the data signal in the phase comparison result is increased/maximized.

In some example embodiments, the first pin group PG1 and the first circuit block 201, and the second pin group PG2 and the second circuit block 202 may be disposed on a monolithic silicon substrate. In some example embodiments, the first pin group PG1 and the first circuit block 201 and the second pin group PG2 and the second circuit block 202 are offset and/or mirrored.

FIG. 5 is a flow chart illustrating an example of a read training operation of the memory controller of FIG. 3. Referring to fig. 3 and 5, in operation S101, the memory controller 100 may select one data pin from a specific (or alternatively, predetermined) pin group. For example, the memory controller 100 may select the first data pin D _ P1 from the first pin group PG1 and the third data pin D _ P3 from the second pin group PG 2.

In operation S102, the memory controller 100 may perform read training on the selected data pin. The memory controller 100 may perform read training to determine the reception timing of the data signal received from the memory device 200 through the selected data pin. For example, the memory controller 100 may determine the reception timing of the first data signal DQ1 as the first reception timing RT1 by performing read training on the first data pin D _ P1.

In operation S103, the memory controller 100 may determine a reception timing determined according to the read training as a reception timing corresponding to the pin group. The memory controller 100 may store the determined reception timing corresponding to the pin group. For example, the memory controller 100 may determine a first reception timing RT1 determined according to the read training of the first data pin D _ P1 as a reception timing corresponding to the first pin group PG 1.

FIG. 6 is a flow chart illustrating an example of a write training operation of the memory controller of FIG. 3. Referring to fig. 3 and 6, in operation S111, the memory controller 100 may select one data pin from a specific (or alternatively, predetermined) pin group. For example, the memory controller 100 may select the first data pin D _ P1 from the first pin group PG1 and the third data pin D _ P3 from the second pin group PG 2. However, example embodiments are not limited thereto.

In operation S112, the memory controller 100 may perform write training on the selected data pin. The memory controller 100 may perform write training to determine the transmission timing of data signals transmitted to the memory device 200 through the selected data pin. For example, the memory controller 100 may determine the transmission timing of the first data signal DQ1 as the first transmission timing TT1 by performing write training on the first data pin D _ P1. In this case, the write training may be performed such that the timing window between the write data strobe signal WDQS and the first data signal DQ1 is increased/maximized.

In operation S113, the memory controller 100 may determine a transmission timing determined according to the write training as a transmission timing corresponding to the pin group. The memory controller 100 may store the determined transmit timing corresponding to the pin group. For example, the memory controller 100 may determine the first transmission timing TT1 determined according to the write training to the first data pin D _ P1 as the transmission timing corresponding to the first pin group PG 1.

In an example embodiment, unlike that shown in fig. 5 and 6, the memory controller 100 may perform training on each pin of one of a plurality of pin groups and then determine a training value corresponding to the pin group based on the training result for the pin. In an example embodiment, the determined training values corresponding to one pin group may be used to determine training values for another pin group. In this case, training for each pin of another pin group may be omitted.

As described above, when the read training is performed for each group of data pins D _ P, the memory controller 100 may sample the data signal received from the memory device 200 through one pin group at the same (e.g., substantially the same) timing. When the data signals are sampled at the same timing, this may correspond to the sampling timing offset for the data signals being reduced or minimized. In this case, in order to improve/optimize the data error bit rate of the sampled data signal, the data signal transmitted from the memory device 200 through one pin group should or must be transmitted to the memory controller 100 at the same timing. When the data signals are transmitted at the same timing, this may reduce or minimize a data offset corresponding to the transmitted data signals.

As described above, when the write training is performed for each group of data pins D _ P, the memory controller 100 can transmit the data signal corresponding to one pin group to the memory device 200 at the same timing. When the data signals are transmitted at the same timing, this may reduce or minimize a data offset corresponding to the transmitted data signals. The memory device 200 may sample a data signal sent from the memory controller 100 over a group of pins. In this case, the data signals should be sampled at the same timing to improve/optimize the data bit error rate of the sampled data signals. In other words, the sample timing offset of the data signal should be reduced or minimized.

Hereinafter, the memory system 10 that reduces/minimizes the data offset of the data signal transmitted from the memory device 200 to the memory controller 100 through one pin group and reduces/minimizes the sampling timing offset of the data signal transmitted to the memory device 200 through one pin group will be described in detail.

Fig. 7 is a block diagram schematically illustrating the memory system of fig. 3. For convenience of explanation, a configuration of the memory system 10 for performing a write operation according to the write training result (i.e., the first transmission timing TT1 and the second transmission timing TT2) described with reference to fig. 3 is described, but the example embodiments are not limited thereto.

Referring to fig. 7, the memory controller 100 may include a write data strobe pin W _ P ', a first pin group PG1 ', and a second pin group PG2 '. The write data strobe pin W _ P ', the first pin group PG1 ', and the second pin group PG2 ' may correspond to the write data strobe pin W _ P, the first pin group PG1, and the second pin group PG2 of the memory device 200. The memory controller 100 may include a phase locked loop 111, a phase controller 112, a delay circuit 113, a first transmitter group 114, and a second transmitter group 115. For example, the phase locked loop 111, the phase controller 112, the delay circuit 113, the first transmitter group 114, and the second transmitter group 115 may be included in the host interface circuit 110 of fig. 1.

The phase-locked loop 111 may generate the write data strobe signal WDQS with a particular (or alternatively, predetermined) phase transition. The write data strobe signal WDQS may be provided to the phase controller 112 and may be transmitted to the memory device 200 through the write data strobe pin W _ P'. In an example embodiment, although not shown in fig. 7, the write data strobe signal WDQS may be transmitted to the memory device 200 through a separate transmitter (or buffer) disposed between the phase locked loop 111 and the write data strobe pin W _ P'.

The phase controller 112 may generate a write data strobe signal pWDQS, the phase of which is adjusted by adjusting the phase of the write data strobe signal WDQS. For example, the phase controller 112 may adjust the phase of the write data strobe signal WDQS such that the phase difference between the write data strobe signal WDQS and the phase-adjusted write data strobe signal pWDQS is 90 degrees.

The delay circuit 113 may delay a write data strobe signal pWDQS, the phase of which is adjusted according to the write training result. The delay circuit 113 may delay the write data strobe signal wdqs, whose phase is adjusted according to the first transmission timing TT1 corresponding to the first pin group PG1, to generate the first write delay signal WDS 1. The delay circuit 113 may delay the write data strobe signal wdqs, whose phase is adjusted according to the second transmission timing TT2 corresponding to the second pin group PG2, to generate the second write delayed signal WDS 2. The first write latency signal WDS1 may be provided to the first transmitter group 114 and the second write latency signal WDS2 may be provided to the second transmitter group 115. In this case, the first write delay signal WDS1 may have transition timing corresponding to the first transmission timing TT1, and the second write delay signal WDS2 may have transition timing corresponding to the second transmission timing TT 2.

The first transmitter group 114 may transmit a data signal including data to the memory device 200 through the first pin group PG 1' based on transition timing of the first write delay signal WDS 1. For example, the first transmitter group 114 may transmit the first DATA signal DQ1 including the first DATA1 to the memory device 200 through the first DATA pin D _ P1' based on the transition timing of the first write delay signal WDS 1. The first transmitter group 114 may transmit a second DATA signal DQ2 including second DATA2 to the memory device 200 through the second DATA pin D _ P2' based on the transition timing of the first write latency signal WDS 1. Therefore, the first transmitter group 114 can transmit each of the data signals to the memory device 200 at the same transmission timing (i.e., the first transmission timing TT 1).

The second transmitter group 115 may transmit a data signal including data to the memory device 200 through the second pin group PG 2' based on transition timing of the second write delay signal WDS 2. For example, the second transmitter group 115 may transmit the third DATA signal DQ3 including the third DATA3 to the memory device 200 through the third DATA pin D _ P3' based on the transition timing of the second write delay signal WDS 2. The second transmitter group 115 may transmit a fourth DATA signal DQ4 including fourth DATA4 to the memory device 200 through the fourth DATA pin D _ P4' based on the transition timing of the second write delay signal WDS 2. Therefore, the second transmitter group 115 can transmit each of the data signals to the memory device 200 at the same transmission timing (i.e., the second transmission timing TT 2).

The data signal output through the first pin group PG 1' may be transmitted to the first pin group PG1 through a corresponding signal line. In this case, the signal line may be configured to reduce/minimize a data offset of the data signal transmitted to the first pin group PG 1. For example, the lengths and/or resistances of the signal lines connecting the data pins of the first pin group PG 1' and the data pins of the first pin group PG1 may be the same or substantially the same. As described above, since the data offset of the data signal output through the first pin group PG 1' can be reduced or minimized, when the lengths of the signal lines transmitting the data signal are the same (assuming that the physical properties of the signal lines are also the same), the state in which the data offset is reduced/minimized can be maintained until the data signal reaches the first pin group PG 1. For example, when the length of the first signal line DL1 transmitting the first data signal DQ1 and the length of the second signal line DL2 transmitting the second data signal DQ2 are the same, data skew of the first data signal DQ1 and the second data signal DQ2 received by the memory device 200 through the first data pin D _ P1 and the second data pin D _ P2 may be reduced/minimized. For example, the data signals transmitted from the first transmitter group 114 may be transmitted to the memory device 200 at the same timing.

Also, the signal lines may be configured to reduce/minimize a data offset of the data signals transmitted to the second pin group PG 2. For example, the lengths of signal lines connecting the data pin of the second pin group PG 2' and the data pin PG2 of the second pin group may be the same. For example, when the length of the third signal line DL3 transmitting the third data signal DQ3 and the length of the fourth signal line DL4 transmitting the fourth data signal DQ4 are the same, data skew of the third data signal DQ3 and the fourth data signal DQ4 received by the memory device 200 through the third data pin D _ P3 and the fourth data pin D _ P4 may be reduced/minimized. For example, the data signals transmitted by the second transmitter group 115 may be transmitted to the memory device 200 at the same timing.

The memory device 200 may include a write data strobe (WDQS) tree 211, a first receiver group 212, and a second receiver group 213. For example, a write data strobe signal (WDQS) tree 211, a first receiver group 212, and a second receiver group 213 may be included in the memory interface circuit 210 of FIG. 1. For example, the write data strobe signal (WDQS) tree 211, the first receiver group 212, and the second receiver group 213 may correspond to the first circuit block 201 and the second circuit block 202 of fig. 4. The WDQS tree 211 may transmit a first internal write data strobe signal dWDQS1 toggled based on a write data strobe signal WDQS received through a write data strobe pin W _ P to the first receiver group 212 and a toggled second internal write data strobe signal dWDQS2 to the second receiver group 213. In an example embodiment, the WDQS tree 211 may include a plurality of repeaters, and the first and second internal write data strobe signals dWDQS1 and dWDQS2 may be transmitted through the repeaters.

In an example embodiment, the first and second internal write data strobe signals wddqs 1 and WDQS2 may be/correspond to signals generated by delaying the write data strobe signal WDQS by the WDQS tree 211. In this case, transition timings of the write data strobe signal WDQS and the first internal write data strobe signal wddqs 1 may be different from each other, and transition timings of the write data strobe signal WDQS and the second internal write data strobe signal wddqs 2 may be different from each other. For example, the transition timing offsets may be generated by the WDQS tree 211. The transmit timing determined by training in the memory controller 100 may compensate for the transition timing offset caused by the WDQS tree 211. Accordingly, an offset between the write data strobe signal WDQS and the first internal write data strobe signal wddqs 1 may be compensated by the first transmission timing TT1, and an offset between the write data strobe signal WDQS and the second internal write data strobe signal wddqs 2 may be compensated by the second transmission timing TT 2.

FIG. 7 illustrates an example of generating the first and second internal write data strobe signals WDQS1 and WDQS2 by delaying the write data strobe signal WDQS by the WDQS tree 211, but example embodiments are not limited thereto. In some example embodiments, the first and second internal write data strobe signals wddqs 1 and WDQS2 may be signals generated by delaying the divided write data strobe signal by the WDQS tree 211. In this case, the write data strobe signal divided in frequency from the write data strobe signal WDQS may be generated by a frequency divider located between the write data strobe pin W _ P and the WDQS tree 211.

The first receiver group 212 may sample the data signals received through the first pin group PG1 based on the transition timing of the first internal write data strobe signal wddqs 1. Thus, the first receiver group 212 may obtain data from the data signal received through the first pin group PG 1. For example, the first receiver group 212 may sample the first DATA signal DQ1 received through the first DATA pin D _ P1 to obtain first DATA1 and sample the second DATA signal DQ2 received through the second DATA pin D _ P2 to obtain second DATA2 based on the transition timing of the first internal write DATA strobe signal wddqs 1.

The second receiver group 213 may sample the data signals received through the second pin group PG2 based on the transition timing of the second internal write data strobe signal wddqs 2. Accordingly, the second receiver group 213 may obtain data from the data signal received through the second pin group PG 2. For example, the second receiver group 213 may obtain the third DATA3 by sampling the third DATA signal DQ3 received through the third DATA pin D _ P3 based on the transition timing of the second internal write DATA strobe signal wddqs 2, and obtain the fourth DATA4 by sampling the fourth DATA signal DQ4 received through the fourth DATA pin D _ P4.

In this manner, when sampling the data signal received through one pin group based on one transition timing (e.g., a transition timing of the first internal write data strobe signal wddqs 1 or a transition timing of the second internal write data strobe signal wddqs 2), a sampling timing offset of the data signal may be reduced/minimized.

As described above, with the memory system 10 according to some example embodiments of the inventive concepts, the memory controller 100 may transmit data signals to the memory device 200 through one pin group with the same transmission timing. The memory device 200 can sample the data signal transmitted through one pin group with the same sampling timing. Therefore, even if write training is performed for each pin group, the data bit error rate of the data signal transmitted in the write operation can be improved/optimized.

Fig. 8 is a timing diagram illustrating an example of sampling a data signal by the memory device of fig. 7. Referring to fig. 7 and 8, the write data strobe signal WDQS received by the memory device 200 through the write data strobe pin W _ P may have a transition timing at a first time point t 1. The first internal write data strobe signal wddqs 1 transmitted by the WDQS tree 211 to the first receiver group 212 may have a transition timing at the second time point t2, and the second internal write data strobe signal wddqs 2 transmitted by the WDQS tree 211 to the second receiver group 213 may have a transition timing at the third time point t 3. Accordingly, a first offset SK1 may be generated between the first internal write data strobe signal dWDQS1 and the write data strobe signal WDQS, and a second offset SK2 may be generated between the second internal write data strobe signal dWDQS2 and the write data strobe signal WDQS.

The first DATA signal DQ1 including the first DATA1 and the second DATA signal DQ2 including the second DATA2 may be transmitted to the first receiver group 212 according to the first transmission timing TT1 to compensate for the first offset SK 1. The first data signal DQ1 and the second data signal DQ2 transmitted to the first receiver group 212 may be sampled based on the transition timing of the first internal write data strobe signal wddqs 1. In this case, the sampling margins of the first DATA1 and the second DATA2 are increased/secured, so that the DATA bit error rate can be increased/optimized.

The third DATA signal DQ3 including the third DATA3 and the fourth DATA signal DQ4 including the fourth DATA4 may be transmitted to the second receiver group 213 in accordance with the second transmission timing TT2 to compensate for the second skew SK 2. The third and fourth data signals DQ3 and DQ4 of the second receiver group 213 may be sampled based on the transition timing of the second internal write data strobe signal wddqs 2. In this case, the sampling margins of the third DATA3 and the fourth DATA4 are increased/secured, so that the DATA bit error rate can be increased/optimized.

As described above, the sampling timing offset of the data signal transmitted through one pin group of the memory device 200 can be minimized. Hereinafter, a detailed configuration of a memory device for minimizing a sampling timing offset of a data signal transmitted through one pin group will be described with reference to fig. 9.

Fig. 9 is a diagram showing an example configuration of the memory device of fig. 7. Referring to fig. 7 and 9, the memory device 200 may include a plurality of repeaters 211a to 211e and a plurality of receivers 212a, 212b, 213a, and 213 b. Repeaters 211a through 211e may be included in the WDQS tree 211. The receivers 212a and 212b may be included in a first receiver group 212, and the receivers 213a and 213b may be included in a second receiver group 213.

The write data strobe signal WDQS, received through the write data strobe pin W _ P, may be transmitted through the repeaters 211a, 211b, 211c and 211d on the first path as a first internal write data strobe signal dWDQS1 to the receivers 212a and 212b, respectively. The write data strobe signal WDQS may be transmitted to the receivers 213a and 213b through the repeaters 211a, 211b, 211c and 211e on the second path as a second internal write data strobe signal dWDQS 2. For example, when the length and/or resistance of the first signal line SL1 connecting the repeater 211c and the repeater 211d on the first path is different from the length/resistance of the second signal line SL2 connecting the repeater 211c and the repeater 211e on the second path, as shown with reference to fig. 8, the transition timing of the first internal write data strobe signal wdqs1 and the transition timing of the second internal write data strobe signal wdqs2 may be different. For example, each of the repeaters 211a to 211e may be implemented with at least one buffer or at least one inverter.

The receiver 212a may sample the first DATA signal DQ1 received through the first DATA pin D _ P1 based on the transition timing of the first internal write DATA strobe signal wddqs 1 and output a first DATA 1. The receiver 212b may sample the second DATA signal DQ2 received through the second DATA pin D _ P2 based on the transition timing of the first internal write DATA strobe signal wddqs 1 and output a second DATA 2. In some example embodiments, in order for the receivers 212a and 212b to sample the data signals DQ1 and DQ2 at the same transition timing (i.e., in order for the first internal write data strobe signal wddqs 1 to reach the same timing for the receivers 212a and 212 b), the receivers 212a and 212b may be disposed at the same distance as the repeater 211 d. In some example embodiments, in order for the receivers 212a and 212b to sample the data signals DQ1 and DQ2 at the same transition timing, the length of the third signal line SL3 for transmitting the first internal write data strobe signal wdqs1 from the repeater 211d to the receiver 212a and the length of the fourth signal line SL4 for transmitting the first internal write data strobe signal wdqs1 from the repeater 211d to the receiver 212b may be the same.

The receiver 212a may receive the first data signal DQ1 from the first data pin D _ P1 through a fifth signal line SL5, and the receiver 212b may receive the second data signal DQ2 from the second data pin D _ P2 through a sixth signal line SL 6. In some example embodiments, in order to allow the data signals DQ1 and DQ2 to be transmitted from the first and second data pins D _ P1 and D _ P2 to the receivers 212a and 212b at the same timing, the lengths of the fifth and sixth signal lines SL5 and SL6 may be the same.

The receiver 213a may perform on the third DATA signal DQ3 received through the third DATA pin D _ P3 based on the transition timing of the second internal write DATA strobe signal wddqs 2 and output the third DATA 3. The receiver 213b may perform on the fourth DATA signal DQ4 received through the fourth DATA pin D _ P4 based on the transition timing of the second internal write DATA strobe signal wddqs 2 and output the fourth DATA 4. In some example embodiments, in order for the receivers 213a and 213b to sample the data signals DQ3 and DQ4 at the same transition timing (e.g., in order for the second internal write data strobe signal wddqs 2 to reach the same timing for the receivers 213a and 213 b), the receivers 213a and 213b may be arranged to have the same distance as the repeater 211 e. As an example, the length of the seventh signal line SL7 for transmitting the second internal write data strobe signal wddqs 2 from the repeater 211e to the receiver 213a and the length of the eighth signal line SL8 for transmitting the second internal write data strobe signal wddqs 2 from the repeater 211e to the receiver 213b may be the same.

The receiver 213a may receive the third data signal DQ3 from the third data pin D _ P3 through a ninth signal line SL9, and the receiver 213b may receive the fourth data signal DQ4 from the fourth data pin D _ P4 through a tenth signal line SL 10. In an example embodiment, in order to allow the data signals DQ3 and DQ4 to be transmitted from the third data pin D _ P3 and the fourth data pin D _ P4 to the sinks 213a and 213b at the same timing, the length of the ninth signal line SL9 and the length of the tenth signal line SL10 may be the same.

When the memory device 200 is configured as described above, the internal write data strobe signal can be transmitted to the receiver corresponding to one pin group at the same timing. Accordingly, the sampling timing offset of the data signal received through one pin group can be reduced/minimized.

Fig. 10 is a block diagram schematically illustrating the memory system of fig. 3. For convenience of explanation, a configuration of the memory system 10 for performing a read operation according to the read training result (e.g., the first reception timing RT1 and the second reception timing RT2) described with reference to fig. 3 is described, but the present invention is not limited thereto.

Referring to fig. 10, the memory controller 100 may include a write data strobe pin W _ P ', a read data strobe pin R _ P', a first pin group PG1 ', and a second pin group PG 2'. The write data strobe pin W _ P ', the read data strobe pin R _ P', the first pin group PG1 ', and the second pin group PG 2' may correspond to the write data strobe pin W _ P, the read data strobe pin R _ P, the first pin group PG1, and the second pin group PG2 of the memory device 200.

The memory device 200 may include a WDQS tree 211, a transmitter 214, a first transmitter group 215, and a second transmitter group 216. For example, the phase locked loop 211, the phase controller 214, the delay circuit 215, the first transmitter group 216, and the second transmitter group 115 may be included in the host interface circuit 210 of fig. 1. The WDQS tree 211 may send a third internal write data strobe signal dWDQS3 to the transmitter 214 that transitions based on the write data strobe signal WDQS received through the write data strobe pin W _ P. The WDQS tree 211 may transmit a fourth internal write data strobe signal wddqs 4 toggled based on the write data strobe signal WDQS to the first transmitter group 215 and a toggled fifth internal write data strobe signal wddqs 5 to the second transmitter group 216. For example, the transition timing of the fourth internal write data strobe signal wddqs 4 may be the same as the transition timing of the first internal write data strobe signal wddqs 1 of fig. 7, and the transition timing of the fifth internal write data strobe signal wddqs 5 may be the same as the second internal write data strobe signal wdqs2 of fig. 7. In some example embodiments, the WDQS tree 211 may include a plurality of repeaters, and the third to fifth internal write data strobe signals WDQS3 to WDQS5 may be transmitted through the repeaters.

The transmitter 214 may transmit the read data strobe signal RDQS to the memory controller 100 through the read data strobe pin R _ P based on the transition timing of the third internal write data strobe signal dWDQS 3.

In some example embodiments, the third to fifth internal write data strobe signals wddqs 3 to wddqs 5 may be signals generated by delaying the write data strobe signal WDQS by the WDQS tree 211. In this case, transition timings of the read data strobe signals RDQS generated based on the third and fourth internal write data strobe signals wddqs 3 and wdqs4 may be different from each other, and transition timings of the read data strobe signals RDQS and the fifth internal write data strobe signal wdqs5 may be different from each other. That is, the transition timing offsets may be generated by the WDQS tree 211. The receive timing determined by training in the memory controller 100 may compensate for the transition timing offset caused by the WDQS tree 211. Accordingly, a shift between the read data strobe signal RDQS and the fourth internal write data strobe signal wddqs 4 may be compensated by the first reception timing RT1, and a shift between the read data strobe signal RDQS and the fifth internal write data strobe signal wdqs5 may be compensated by the second reception timing RT 2.

The first transmitter group 215 may transmit a data signal including data to the memory controller 100 through the first pin group PG1 based on a transition timing of the fourth internal write data strobe signal wddqs 4. For example, the first transmitter group 215 may transmit a first DATA signal DQ1 including first DATA1 to the memory controller 100 through the first DATA pin D _ P1 based on the transition timing of the fourth internal write DATA strobe signal wddqs 4. The first transmitter group 215 may transmit a second DATA signal DQ2 including second DATA2 to the memory controller 100 through the second DATA pin D _ P2 based on the transition timing of the fourth internal write DATA strobe signal wddqs 4. Accordingly, the first transmitter group 215 can transmit each of the data signals to the memory controller 100 at the same timing.

The second transmitter group 216 may transmit a data signal including data to the memory controller 100 through the second pin group PG2 based on a transition timing of the fifth internal write data strobe signal wddqs 5. For example, the second transmitter group 216 may transmit a third DATA signal DQ3 including third DATA3 to the memory controller 100 through the third DATA pin D _ P3 based on the transition timing of the fifth internal write DATA strobe signal wddqs 5. The second transmitter group 216 may transmit a fourth DATA signal DQ4 including fourth DATA4 to the memory controller 100 through the fourth DATA pin D _ P4 based on the transition timing of the fifth internal write DATA strobe signal wddqs 5. Therefore, the second transmitter group 216 can transmit each of the data signals to the memory controller 100 at the same timing.

In this way, when each of the data signals is output at the same timing through one pin group, the data skew of the output data signal can be reduced/minimized.

As described with reference to fig. 7, the lengths of signal lines connecting the first pin group PG1 'and the first pin group PG1 may be the same, and the lengths of signal lines connecting the second pin group PG 2' and the second pin group PG2 may be the same. As described above, since the data skew of the data signal output through one pin group can be reduced/minimized, when the lengths of the signal lines transmitting the data signal are the same, the state of the data skew reduction/minimization can be maintained until the data signal is transmitted to the memory controller 100. That is, the data signals transmitted from the first transmitter group 215 may be transmitted to the memory controller 100 at the same timing, and the data signals transmitted from the second transmitter group 216 may be transmitted to the memory controller 100 at the same timing.

The memory controller 100 may include a phase locked loop 111, a phase controller 112, a delay circuit 113, a first receiver group 116, and a second receiver group 117. For example, the phase locked loop 111, the phase controller 112, the delay circuit 113, the first receiver group 116, and the second receiver group 117 may be included in the host interface circuit 110 of fig. 1.

The phase-locked loop 111 may generate the write data strobe signal WDQS with a predetermined phase transition. The write data strobe signal WDQS may be transmitted to the memory device 200 through the write data strobe pin W _ P'.

The phase controller 112 may receive the read data strobe signal RDQS transmitted by the memory device 200 through the read data strobe pin R _ P'. The phase controller 112 may generate a read data strobe signal pRDQS whose phase is adjusted by adjusting the phase of the read data strobe signal RDQS. For example, the phase controller 112 may adjust the phase of the read data strobe signal RDQS such that the phase difference between the phases of the read data strobe signal RDQS and the adjusted read data strobe signal pRDQS is 90 degrees.

The delay circuit 113 may delay the read data strobe signal pRDQS, the phase of which is adjusted according to the read training result. The delay circuit 113 delays the read data strobe signal pRDQS, whose phase is adjusted according to the first reception timing RT1 corresponding to the first pin group PG1, to generate the first read delay signal RDS 1. The delay circuit 113 delays the read data strobe signal pRDQS, whose phase is adjusted according to the second reception timing RT2 corresponding to the second pin group PG2, to generate the second read delay signal RDS 2. The first read delay signal RDS1 may be provided to the first receiver group 116 and the second read delay signal RDS2 may be provided to the second receiver group 117. In this case, the first read delay signal RDS1 may have a conversion timing corresponding to the first reception timing RT1, and the second read delay signal RDS2 may have a conversion timing corresponding to the second reception timing RT 2.

The first receiver group 116 may obtain data by sampling the data signal received by the first pin group PG1 based on the conversion timing RDS1 of the first read delay signal. For example, the first receiver group 116 may obtain the first DATA1 by sampling the first DATA signal DQ1 based on the conversion timing RDS1 of the first read latency signal. The first receiver group 116 may obtain the second DATA2 by sampling the second DATA signal DQ2 based on the conversion timing RDS1 of the first read latency signal. Accordingly, the first receiver group 116 can sample each of the data signals according to the same reception timing (e.g., the first reception timing RT 1).

The second receiver group 117 may obtain data by sampling the data signal received by the second pin group PG 2' based on the conversion timing RDS2 of the second read delay signal. For example, the second receiver group 117 may obtain the third DATA3 by sampling the third DATA signal DQ3 based on the conversion timing RDS2 of the second read delay signal. The second receiver group 117 may obtain the fourth DATA4 by sampling the fourth DATA signal DQ4 based on the conversion timing RDS2 of the second read delay signal. Therefore, the second receiver group 117 can sample each of the data signals according to the same reception timing (e.g., the second reception timing RT 2).

As described above, with the memory system 10 according to some example embodiments of the inventive concepts, the memory device 200 may transmit data signals to the memory controller 100 through one pin group at the same timing. The memory controller 100 can sample the data signal received through one pin group at the same timing. Therefore, even if the read training is performed for each pin group, the data bit error rate of the data signal transmitted in the read operation can be optimized.

Fig. 11 is a timing diagram illustrating an example in which the memory device of fig. 10 transmits a data signal. Referring to fig. 10 and 11, the write data strobe signal WDQS received through the write data strobe pin W _ P may have a transition timing at a first time point t 1. The third internal write data strobe signal dWDQS3 and the read data strobe signal RDQS transmitted to the transmitter 214 by the WDQS tree 211 may have transition timings at a second time point t 2. The fourth internal write data strobe signal wddqs 4 transmitted to the first transmitter group 215 may have a transition timing at a third time point t3, and the fifth internal write data strobe signal wddqs 5 transmitted by the WDQS tree 211 to the second transmitter group 216 may have a transition timing at a fourth time point t 4. Accordingly, a first offset SK1 may be generated between the fourth internal write data strobe signal dWDQS4 and the read data strobe signal RDQS, and a second offset SK2 may be generated between the fifth internal write data strobe signal dWDQS5 and the read data strobe signal RDQS.

The first DATA signal DQ1 including the first DATA1 and the second DATA signal DQ2 including the second DATA2 may be transmitted to the memory controller 100 at the transition timing of the fourth internal write DATA strobe signal wddqs 4. Accordingly, the first DATA1 and the second DATA2 may be transmitted to the memory controller 100 at the same timing. The first data signal DQ1 and the second data signal DQ2 transmitted to the first receiver group 116 may be sampled based on the first reception timing RT1 to compensate for the first offset SK 1. In this case, the sampling margins of the first DATA1 and the second DATA2 are ensured so that the DATA bit error rate can be optimized.

The third DATA signal DQ3 including the third DATA3 and the fourth DATA signal DQ4 including the fourth DATA4 may be transmitted to the memory controller 100 at the transition timing of the fifth internal write DATA strobe signal wddqs 5. Therefore, the third DATA3 and the fourth DATA4 may be transmitted to the memory controller 100 at the same timing. The third data signal DQ3 and the fourth data signal DQ4 transmitted to the second receiver group 117 may be sampled based on the second reception timing RT2 to compensate for the second offset SK 2. In this case, the sampling margins of the third DATA3 and the fourth DATA4 are ensured so that the DATA bit error rate can be optimized.

As described above, the data skew of the data signal output from one pin group of the memory device 200 can be reduced or minimized. Hereinafter, a detailed configuration of a memory device that reduces/minimizes data skew of a data signal output from one pin group will be described with reference to fig. 12.

Fig. 12 is a diagram showing an example configuration of the memory device of fig. 10. Referring to fig. 10 and 12, the memory device 200 may include a plurality of repeaters 211a to 211f and a plurality of transmitters 214, 215a, 215b, 216a, and 216 b. Repeaters 211a through 211f may be included in the WDQS tree 211. The transmitters 215a and 215b may be included in a first transmitter group 215, and the transmitters 216a and 216b may be included in a second transmitter group 216.

The write data strobe signal WDQS, received through the write data strobe pin W _ P, may be transmitted through the repeaters 211a, 211b, 211c and 211d on the first path as a fourth internal write data strobe signal dWDQS4 to the transmitters 215a and 215b, respectively. The write data strobe signal WDQS may be transmitted to the transmitters 216a and 216b through the repeaters 211a, 211b, 211c and 211e on the second path as a fifth internal write data strobe signal dWDQS 5. The write data strobe signal WDQS may be transmitted to the transmitter 214 through the repeaters 211a, 211b, 211c, and 211f on the third path as a third internal write data strobe signal dWDQS 3. For example, when the length of the first signal line ML1 connecting the repeater 211c and the repeater 211d on the first path, the length of the second signal line ML2 connecting the repeater 211c and the repeater 211e on the second path, and the length of the third signal line ML3 connecting the repeater 211c and the repeater 211f on the third path are different from each other, as described with reference to fig. 11, the transition timing of the third internal write data strobe signal wdqs3 to the fifth internal write data strobe signal wdqs5 may be different from each other.

The transmitter 214 may generate the read data strobe signal RDQS based on the transition timing of the third internal write data strobe signal dWDQS 3. The transmitter 215a may transmit a first DATA signal DQ1 including first DATA1 to the memory controller 100 through the first DATA pin D _ P1 based on the transition timing of the fourth internal write DATA strobe signal wddqs 4. The transmitter 215b may transmit a second DATA signal DQ2 including second DATA2 to the memory controller 100 through the second DATA pin D _ P2 based on the transition timing of the fourth internal write DATA strobe signal wddqs 4.

In an example embodiment, in order for the transmitters 215a and 215b to transmit the data signals DQ1 and DQ2 at the same transition timing (i.e., in order for the fourth internal write data strobe signal wddqs 4 to reach the same timing for the transmitters 215a and 215 b), the transmitters 215a and 215b may be disposed at the same distance from the repeater 211 d. As an example, in order for the transmitters 215a and 215b to transmit the data signals DQ1 and DQ2 at the same transition timing, the length of the fourth signal line ML4 for transmitting the fourth internal write data strobe signal wddqs 4 from the repeater 211d to the transmitter 215a and the length of the fifth signal line ML5 for transmitting the fourth internal write data strobe signal wdqs4 from the repeater 211d to the transmitter 215b may be the same.

The first data signal DQ1 may be output through a first data pin D _ P1 connected to the sixth signal line ML6, and the second data signal DQ2 may be output through a second data pin D _ P2 connected to the seventh signal line ML 7. In an example embodiment, in order to make the data signals DQ1 and DQ2 output from the data pins D _ P1 and D _ P2 at the same timing, the length of the sixth signal line ML6 and the length of the seventh signal line ML7 may be the same.

The transmitter 216a may transmit a third DATA signal DQ3 including third DATA3 to the memory controller 100 through the third DATA pin D _ P3 based on the transition timing of the fifth internal write DATA strobe signal wddqs 5. The transmitter 216b may transmit a fourth DATA signal DQ4 including fourth DATA4 to the memory controller 100 through the fourth DATA pin D _ P4 based on the transition timing of the fifth internal write DATA strobe signal wddqs 5.

In an example embodiment, in order for the transmitters 216a and 216b to transmit the data signals DQ3 and DQ4 at the same transition timing (i.e., in order for the fifth internal write data strobe signal dWDQS5 to reach the same timing for the transmitters 216a and 216 b), the transmitters 216a and 216b may be disposed at the same distance from the repeater 211 e. As an example, in order for the transmitters 216a and 216a to transmit the data signals DQ3 and DQ4 at the same transition timing, the length of the eighth signal line ML8 for transmitting the fifth internal write data strobe signal wdqs5 from the repeater 211e to the transmitter 216a and the length of the ninth signal line ML9 for transmitting the fifth internal write data strobe signal wdqs5 from the repeater 211e to the transmitter 216b may be the same.

The third data signal DQ3 may be output through a third data pin D _ P3 connected to the tenth signal line ML10, and the fourth data signal DQ4 may be output through a fourth data pin D _ P4 connected to the eleventh signal line ML 11. In an example embodiment, in order to make the data signals DQ3 and DQ4 output from the data pins D _ P3 and D _ P4 at the same timing, the length of the tenth signal line ML10 and the length of the eleventh signal line ML11 may be the same.

When the memory device 200 is configured as described above, the transition timing offset of the internal write data strobe signal transmitted to the transmitter corresponding to one pin group can be reduced/minimized, and the data offset of the data signal output from the transmitter through one pin group can be reduced/minimized.

Fig. 13 is a block diagram illustrating a stacked memory device according to some example embodiments of the inventive concepts. Referring to fig. 13, a stacked memory device 300 may include a buffer die 310 and a plurality of core dies 320 through 350. For example, the cache die 310 may also be referred to as an interface die, a base die, a logic die, a master die, etc., and each of the core dies 320 through 350 may also be referred to as a memory die, a slave die, etc. Fig. 13 shows that stacked memory device 300 includes four core dies 320-350, but the number of core dies may vary. For example, stacked memory device 300 may include 8, 12, or 16 core dies.

The buffer die 310 and the core dies 320 to 350 are stacked by Through Silicon Vias (TSVs), and may be electrically connected to each other. Accordingly, the stacked memory device 300 may have a three-dimensional memory structure in which a plurality of dies 310 to 350 are stacked. For example, the stacked memory device 300 may be implemented based on the HBM or HMC standards, although the invention is not limited thereto.

The stacked memory device 300 may support multiple functionally independent channels (or vaults). For example, as shown in fig. 13, the stacked memory device 300 may support at least or exactly eight channels CH0 through CH 7. The stacked memory device 300 may support a 1024 data transmit path when each of the channels CH0-CH 7 supports a 128 data transmit path (i.e., when there are 128 data pins corresponding to each of the channels CH0-CH 7). However, the present invention is not limited thereto, and the stacked memory device 300 may support 1024 or more data transmission paths, and may support 8 or more channels (e.g., 16 channels). For example, when stacked memory device 300 supports 1024 data transmit paths and 16 channels, each of the channels may support 64 data transmit paths.

Each of the core dies 320 to 350 may support at least one channel. For example, as shown in FIG. 13, each of the core dies 320-350 may support two channels CH0-CH2, CH1-CH3, CH4-CH6, or CH5-CH 7. In this case, core dies 320-350 may support different channels. However, the present invention is not limited thereto, and at least two of the core dies 320 to 350 may support the same channel. For example, two of the core dies 320 to 350 may support the first channel CH 0.

Each of the channels may constitute a separate command and data interface. For example, each channel may be independently clocked based on independent timing requirements and may not be synchronized with each other.

Each of the channels may include a plurality of memory banks 301. Each of the banks 301 may include: memory cells connected to word lines and bit lines, row decoders, column decoders, sense amplifiers, and so forth. For example, each of the memory banks 301 may correspond to the memory bank 220 of fig. 1. For example, as shown in fig. 13, each of the channels CH0 through CH7 may include eight memory banks 301. However, the present invention is not limited thereto, and each of the channels CH0 through CH7 may include eight or more memory banks 301. Fig. 13 shows that the memory banks included in one channel are included in one core die, but the memory banks included in one channel may be distributed in a plurality of core dies. For example, when core dies 320 and 340 support first channel CH0, the memory banks included in first channel CH0 may be distributed among core dies 320 and 340.

In an example embodiment, one channel may be divided into two dummy channels that operate independently. For example, the dummy channel may share the command and clock inputs (e.g., clock signal CK and clock enable signal CKE) of the channel, but may decode and execute commands independently. For example, when one channel supports a 128 data transmit path, each of the dummy channels may support a 64 data transmit path. For example, when one channel supports a 64 data transmit path, each of the dummy channels may support a 32 data transmit path.

The buffer die 310 and the core dies 320-350 may include the TSV region 302. TSVs configured to pass through the dies 310-350 may be disposed in the TSV region 302. The buffer die 310 may transmit and receive input/output signals to and from the core dies 320 to 350 through the TSVs. Each of the core dies 320 to 350 may transmit/receive input/output signals to/from the buffer die 310 and the other core dies through the TSVs to/from the buffer die 310 and the other core dies. In example embodiments, input/output signals may be independently transmitted/received through TSVs corresponding to each channel. For example, when a data signal is transmitted through the first channel CH0 to cause an external host device (e.g., the memory controller 100 of fig. 1) to store data in the memory cells of the first channel CH0, the buffer die 310 may transmit the data signal to the first core die 320 through the TSVs corresponding to the first channel CH0 to store data in the memory cells of the first channel CH 0.

Buffer die 310 may include a physical layer (PHY) 311. Physical layer 311 may include interface circuitry for communicating with a host device. In an example embodiment, the physical layer 311 may include an interface circuit corresponding to each of the channels CH0 through CH 7. For example, each interface circuit may correspond to the memory interface circuit 210 described with reference to fig. 1-12. Input/output signals received from a host device through the physical layer 311 may be transmitted to the core dies 320 to 350 through the TSVs.

In an example embodiment, the buffer die 310 may include a channel controller corresponding to each of the channels. The channel controller may manage memory access operations for the corresponding channel and may determine timing requirements for the corresponding channel.

In an example embodiment, the stacked memory device 300 may include a plurality of pins for transmitting/receiving input/output signals to/from a host device. For example, multiple pins may be attached to the buffer die 310. As described with reference to fig. 1 through 12, the physical layer 311 of the buffer die 310 may receive the clock signal CK, the command/address signal CA, the write data strobe signal WDQS, and the data signal DQ from the host device through a plurality of pins and transmit the read data strobe signal RDQS and the data signal DQ to the host device. For example, the stacked memory device 300 may include: two write data strobe pins for receiving a write data strobe signal WDQS and two read data strobe pins for transmitting a read data strobe signal RDQS, corresponding to the 32 data pins for transmitting and receiving the data signal DQ.

In example embodiments, the stacked memory device 300 may further include an Error Correction Code (ECC) circuit for detecting and correcting errors in the data. For example, in a write operation, the ECC circuitry may generate parity bits for data sent from the host device. In a read operation, the ECC circuitry may use the parity bits to detect and correct errors of data sent from one of the core dies 320-350 and send the error corrected data to the host device.

In an example embodiment, as described with reference to fig. 1 to 12, the data pins for transmitting and receiving the data signals DQ may be divided into at least two pin groups, and training may be performed for each pin group by the host device. That is, the host device can determine the transmission timing and the reception timing corresponding to one pin group by training. In this case, the buffer die 310 of the stacked memory device 300 may be configured to support training of the host device. Hereinafter, the configuration of the buffer die 310 for supporting training of the host device will be described with reference to fig. 14.

FIG. 14 is a block diagram illustrating an embodiment of the buffer die of FIG. 13. Referring to FIG. 14, the buffer die 310 may include a command address input/output block AWORD and data input/output blocks DWORD0 and DWORD 1. The command address input/output block AWORD and the data input/output blocks DWORD0 and DWORD1 may be included in an interface circuit corresponding to one of the plurality of channels. In fig. 14, it is described that buffer die 310 includes two data input/output blocks DWORD0 and DWORD1, but buffer die 310 may include a different number of data input/output blocks.

The command address input/output block aware may include a CA receiver 312 and a command decoder 313. The CA receiver 312 may sample the command/address signal CA received from the first pin P1 based on the clock signal CK received from the second pin P2 to obtain the command CMD. The command decoder 313 may generate a control signal CTR based on the command CMD, and transmit the control signal CTR to the data input/output blocks DWORD0 and DWORD1, respectively. The components of data input/output blocks DWORD0 and DWORD1 may operate in response to control signals CTR. The clock signal CK may be sent to each of the data input/output blocks DWORD0 and DWORD 1.

The data input/output block DWORD0 may include a WDQS frequency divider 314, a WDQS tree 315, a first transmitter 316, first and second receivers 317a, 317b, and second and third transmitters 318a, 318 b. The WDQS tree 315 may correspond to the WDQS tree 211 described with reference to fig. 7 and 10, and the first transmitter 316 may correspond to the transmitter 214 of fig. 10. The first and second receivers 317a and 317b correspond to the first receiver group 212 of fig. 7, and the second and third transmitters 318a and 318b may correspond to the first transmitter group 215 of fig. 10. For ease of illustration, the configuration of the buffer die 310 is described based on the data input/output block DWORD0, which may be similarly configured with the data input/output block DWORD0 and the data input/output block DWORD 1.

The WDQS frequency divider 314 may generate an internal write data strobe signal dWDQS based on the write data strobe signal WDQS received from the third pin P3. For example, the WDQS frequency divider 314 may generate the internal write data strobe signal dWDQS at different phase transitions based on the write data strobe signal WDQS. In this case, the frequency of each of the internal write data strobe signals wddqs may be less than the frequency of the write data strobe signals WDQS.

The WDQS tree 315 may transmit the internal write data strobe signal dWDQS through a plurality of repeaters to receivers 317a and 317b and transmitters 316, 318a, 318b of a data input/output block DWORD 0. Thus, each of the internal write data strobe signals dWDQS11, dWDQS21, dWDQS22, dWDQS31 and dWDQS32 provided to the first transmitter 316, the first and second receivers 317a, 317b, and the second and third transmitters 318a, 318b may be the following signals: the internal write data strobe signal dqdqdqdqds delayed through the WDQS tree 315. For example, the internal write data strobe signals dWDQS11 may be provided to the first transmitter 316 through a repeater on a first path, and the internal write data strobe signals dWDQS21, dWDQS22, dWDQS31, and dWDQS32 may be provided to the first and second receivers 317a and 317b, and the second and third transmitters 318a and 318b through a repeater on a second path. In this case, the transition timings of the internal write data strobe signals dWDQS21, dWDQS22, dWDQS31 and dWDQS32 may be the same. That is, transition timing offsets between the internal write data strobe signals dWDQS21, dWDQS22, dWDQS31, and dWDQS32 may be reduced/minimized.

FIG. 14 illustrates the transmission of an internal write data strobe signal dWDQS generated based on the write data strobe signal WDQS by a WDQS tree 315, although the invention is not limited thereto. For example, as described with reference to fig. 1-12, the write data strobe signal WDQS may be transmitted by a WDQS tree 315.

The first transmitter 316 may generate the read data strobe signal RDQS based on the transition timing of the internal write data strobe signal dWDQS 11. The read data strobe signal RDQS may be sent to the host device through the fourth pin P4.

The first receiver 317a may sample the first data signal DQ1 received from the fifth pin P5 of the pin group PG based on the transition timing of the internal write data strobe signal wddqs 21. The second receiver 317b may sample the second data signal DQ2 received from the sixth pin P6 of the pin group PG based on the transition timing of the internal write data strobe signal wddqs 22. For example, when the transition timing of the internal write data strobe signal wddqs 21 and the internal write data strobe signal wddqs 22 are the same, the first and second receivers 317a and 317b may sample the first and second data signals DQ1 and DQ2 at the same timing. As described with reference to fig. 1 to 12, since the first data signal DQ1 and the second data signal DQ2 from the host device are received at the same timing through the fifth pin P5 and the sixth pin P6 according to the training result for the pin group PG, the data bit error rate can be optimized even if the first data signal DQ1 and the second data signal DQ2 are sampled at the same timing.

The second transmitter 318a may transmit the first data signal DQ1 to the host device through the fifth pin P5 of the pin group PG based on the transition timing of the internal write data strobe signal wddqs 31. The third transmitter 318b may transmit the second data signal DQ2 to the host device through the sixth pin P6 of the pin group PG based on the transition timing of the internal write data strobe signal wddqs 33. For example, when the transition timings of the internal write data strobe signal wddqs 31 and the internal write data strobe signal wddqs 32 are the same, the second transmitter 318a and the third transmitter 318b may transmit the first data signal DQ1 and the second data signal DQ2 to the host device at the same timing. Therefore, even if the host device samples the first data signal DQ1 and the second data signal DQ2 at the same timing according to the training result for the pin group PG, the data bit error rate can be optimized.

Fig. 14 shows that the data input/output block DWORD0 transmits and receives data signals through one pin group PG, but the present invention is not limited thereto. For example, the data input/output block DWORD0 may transmit/receive data signals over at least two or more pin sets, as described with reference to FIGS. 3-12.

Fig. 15 illustrates an example pin diagram of pins included in the stacked memory device of fig. 13. Specifically, the pin map PMAP of fig. 15 may correspond to one data input/output block DWORD of one channel.

Referring to fig. 13 and 15, the ground voltage VSS and the power voltages VDDQ and VDDQL may be supplied to the physical layer 311 through pins of the pin map PMAP. In addition, the physical layer 311 may receive or transmit input/output signals from or to the host device through pins in the pin map PMAP, for example, the first to thirty-second data signals DQ1 to DQ32, the first to second error correction code signals ECC1 to ECC2, the data parity signal DPAR, the first and second redundant data signals RD1 and RD2, the write data strobe signals WDQS _ t and WDQS _ c, the first to fourth data bus invert signals DBI1 to DBI4, the first and second error severity signals SEV1 and SEV2, and the data error signal DERR.

Supply voltage VDDQ may be a voltage for overall operation of buffer die 310, and supply voltage VDDQL may be a voltage for transmitting input/output signals from buffer die 310 to core dies 320 through 350 through TSVs. In example embodiments, the supply voltage VDDQ may be greater than the supply voltage VDDQL. For example, the power supply voltage VDDQ may be 1.1V, and the power supply voltage VDDQL may be 0.4V.

Each of the first to thirty-second data signals DQ1 to DQ32 may be a signal for transmitting data. Each of the first error correction code signal ECC1 through the second error correction code signal ECC2 may be a signal for controlling enabling or disabling of an ECC circuit. The data parity signal DPAR may include parity bits associated with data included in the data signals DQ1 through DQ 32. The first redundant data signal RD1 and the second redundant data signal RD2 may be signals for transmitting additional data in addition to data included in the first to thirty-second data signals DQ1 to DQ 32. The write data strobe signals WDQS _ t and WDQS _ c may be received from the host device as a differential pair. The first to fourth data bus inversion signals DBI1 to DBI4 may be signals indicating whether code inversion encoding (code inversion encoding) is applied to the first to thirty-second data signals DQ1 to DQ 32. The first error severity signal SEV1 and the second error severity signal SEV2 may be signals indicating the amount of errors when errors of data are detected based on parity bits. The data error signal DERR may be a signal indicating whether an error is detected according to error detection by the ECC circuit. The input/output signals including the data signals DQ1 through DQ32 may be sampled based on the write data strobe signals WDQS _ t and WDQS _ c transmitted to the host device, as described with reference to fig. 1 through 12.

The pins for transmitting/receiving input/output signals in the pin map PMAP may be divided into a plurality of pin groups. In this case, each of the pin groups may include: pins for transmitting and receiving one or more data signals DQ and one or more control signals (e.g., WDQS, RDQS, DBI, DPAR, ECC, DERR, SEV, etc.). For example, as shown in fig. 15, the pins for transmitting and receiving input/output signals in the pin map PMAP may be divided into first through sixth pin groups PG1 through PG 6.

The first through sixth pin groups PG1 through PG6 may be disposed in the first through sixth zones PGA1 through PGA6, respectively. The first to sixth zones PGA1 to 6 may include a power region PA 1. A pin for receiving the power supply voltage VDDQL may be provided in the power supply area PA 1. In an example embodiment, the pins of each of the first through sixth pin groups PG1 through PG6 may be disposed to be symmetrical with respect to the power region PA 1. For example, the pins DQ1, DQ2, DQ3, and ECC1 and the pins DQ9, DQ10, DQ11, and ECC2 of the first pin group PG1 may be arranged symmetrically with respect to the power supply area PA 1. However, the present invention is not limited thereto.

The power supply area PA2 may be disposed between the first to third section PGAs 1 to 3 and the fourth to sixth section PGAs 4 to 6. Pins for receiving the power supply voltage VDDQ and the ground voltage VSS may be disposed in the power supply area PA 2. That is, the first to third area PGAs 1 to 3 and the fourth to sixth area PGAs 4 to 6 may be symmetrically disposed about the power area PA 2.

Each of the first through sixth pin groups PG1 through PG6 may include: pins for transmitting and receiving one or more data signals DQ and one or more control signals. In this case, the pin arrangement structures of the first through third pin groups PG1 through PG3 may be the same, and the pin arrangement structures of the fourth through sixth pin groups PG4 through PG6 may be the same. Also, the second pin group PG2 includes pins for receiving write data strobe signals WDQS _ t and WDQS _ c, and the remaining pin groups PG1 and PG3 through PG6 may not include pins for receiving the write data strobe signals WDQS _ t and WDQS _ c. Fig. 15 shows that each of the pin groups includes at least or exactly eight pins for transmitting and receiving input/output signals (i.e., data signals DQ and control signals), but the present invention is not limited thereto, and various changes may be made in the number and types of pins included in one pin group.

For each of the first through sixth pin groups PG 1-PG 6, training may be performed for each pin group, as described with reference to fig. 1-12. For example, the transmit timing and/or receive timing corresponding to a group of pins may be determined through training of the group of pins. Therefore, a training value (for example, transmission timing of an input/output signal or reception timing of an input/output signal) corresponding to one pin group can be determined as well.

The data signals DQ transmitted and received through one pin group may be sampled at the same timing or transmitted to the host device at the same timing, as described with reference to fig. 1 to 12. To this end, the internal write data strobe signal WDQS generated based on the write data strobe signals WDQS _ t and WDQS _ c may be transmitted to the transmitter and the receiver for transmitting and receiving the data signal DQ, respectively, according to the same delay time through a WDQS tree (e.g., WDQS tree 315 in fig. 14). For example, the internal write data strobe signal wddqs may be transmitted to the transmitter and receiver for transmitting and receiving data signals DQ1, DQ2, DQ3, DQ9, DQ10, and DQ11, respectively, through the first pin group PG1 according to the same delay time.

Fig. 16 illustrates an example configuration of a WDQS tree corresponding to the pin diagram of fig. 15. Referring to fig. 15 and 16, the WDQS tree WTREE may include a plurality of repeaters RPT1 through RPT 4. A plurality of repeaters RPT1 to RPT4 may be provided on a region where pins of the pin map PMAP are arranged. For example, a plurality of repeaters RPT1 to RPT4 may be disposed on the first to sixth zones PGA1 to 6. For example, the repeaters RPT1 through RPT4 may transmit the write data strobe signal WDQS to circuits (e.g., a transmitter and a receiver) on each zone through an H-tree method.

The first repeater RPT1 may receive an internal write data strobe signal wddqs generated based on the write data strobe signals WDQS _ t and WDQS _ c and transmit the internal write data strobe signal wddqs to the second repeater RPT 2. Each of the second repeaters RPT2 may transmit the internal write data strobe signal wddqs transmitted from the first repeater RPT1 to the third repeater RPT 3. For example, the second repeater RPT2 disposed in the second zone PGA2 transmits the internal write data strobe signal wddqs to the third repeater RPT3 disposed in the first to third zone PGAs 1 to 3.

Each of the third repeaters RPT3 may transmit the internal write data strobe signal wddqs transmitted from the second repeater RPT2 to the fourth repeater RPT 4. For example, the third repeater RPT3 disposed in the first zone PGA1 transmits the internal write data strobe signal wddqs to the fourth repeaters RPT4a and RPT4b disposed in the first zone PGA 1.

Each of the fourth repeaters RPT4 may transmit the internal write data strobe signal wddqs transmitted from the third repeater RPT3 to neighboring transmitters and receivers. For example, the fourth transponder RPT4a may transmit the internal write data strobe signal wddqs to the transmitter and receiver for transmitting and receiving data signals DQ1, DQ2, and DQ 3. The fourth transponder RPT4b may transmit the internal write data strobe signal dWDQS to the transmitter and receiver for transmitting and receiving data signals DQ9, DQ10, and DQ 11. In this case, the fourth repeaters RPT4a and RPT4b may be arranged such that the internal write data strobe signal wddqs is transmitted to the transmitter and the receiver according to the same delay time. For example, the fourth transponders RPT4a and RPT4b may be arranged to have the same distance from the third transponder RPT3 of the first zone PGA 1. Accordingly, the internal write data strobe signal wddqs is transmitted to the transmitter and receiver for transmitting and receiving the data signals DQ1, DQ2, DQ3, DQ9, DQ10, and DQ11 at the same timing through the repeaters on different paths.

In an example embodiment, the repeaters on two of the zone PGAs 1 to 6 may be arranged to be symmetrical with respect to the power supply area PA2 of fig. 15. For example, the third and fourth repeaters RPT3 and RPT4 on the first zone PGA1 may be arranged to be symmetrical with the third and fourth repeaters RPT3 and RPT4 on the fourth zone PGA4 with respect to the power supply region PA 2. In this case, the layouts of the repeaters RPT3 and RPT4 on the first zone PGA1 and the repeaters RPT3 and RPT4 on the fourth zone PGA4 may be the same. In this way, the layouts of the circuits provided on two of the block PGA1 to block PGA6 may be the same.

In an example embodiment, the repeaters on two of the zone PGAs 1 to 6 may be arranged to be symmetrical with respect to the power supply area PA2 of fig. 15. For example, the fourth transponder RPT4 on the first zone PGA1 may be arranged symmetrically with respect to the power supply area PA 1.

As described above, when the internal write data strobe signal wddqs is transmitted based on the plurality of repeaters RPT1 through RPT4, the data signal DQ received through one data pin group may be sampled at the same timing, and the data signal DQ may be transmitted to the host device through one data pin group at the same timing.

Fig. 16 illustrates that the transmission timing of the internal write data strobe signal wddqs is controlled by the same number of repeaters (e.g., four repeaters RPT1 through RPT4), but the present invention is not limited thereto. For example, the transmission timing of the internal write data strobe signal dWDQS may be adjusted by differentially resetting the driving capability of the repeater or by using a separate resistor or circuit element such as a capacitor.

Fig. 17 is a diagram illustrating a semiconductor package according to some example embodiments of the inventive concepts. Referring to fig. 17, a semiconductor package 1000 may include a stacked memory device 1100, a system-on-chip 1200, an interposer 1300, and a package substrate 1400. Stacked memory device 1100 may include a buffer die 1110 and core dies 1120-1150. Buffer die 1110 may correspond to buffer die 310 of fig. 13, and each of core dies 1120-1150 may correspond to each of core dies 320-350 of fig. 13.

Each of core dies 1120-1150 may include a memory unit for storing data. Buffer die 1110 may include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 may be electrically connected to the physical layer 1210 of the system-on-chip 1200 through the interposer 1300. The stacked memory device 1100 may receive input/output signals from the system-on-chip 1200 through the physical layer 1111 or may transmit input/output signals to the system-on-chip 1200. Physical layer 1111 may include the interface circuitry of buffer die 310 described with reference to fig. 14.

The direct access region 1112 may provide an access path for testing the stacked memory device 1100 without going through the system-on-chip 1200. The direct access region 1112 may include conductive portions (e.g., ports or pins) capable of communicating directly with external test equipment. Test signals received through the direct access region 1112 may be transmitted to the core dies 1120 to 1150 through the TSVs. Data read from the core dies 1120 to 1150 for testing the core dies 1120 to 1150 may be transmitted to the test apparatus through the TSV and direct access region 1112. Thus, direct access testing may be performed on core dies 1120-1150.

Buffer die 1110 and core dies 1120-1150 may be electrically connected to each other through TSV1101 and bumps 1102. For example, bumps 1102 may correspond to the pins described with reference to fig. 1-16. Buffer die 1110 may receive input/output signals provided to each channel from system-on-chip 1200 via bumps 1102 assigned to each channel or may send input/output signals to system-on-chip 1200 via bumps 1102. For example, bumps 1102 may be tiny bumps.

The system-on-chip 1200 may execute applications supported by the semiconductor package 1000 using the stacked memory device 1100. For example, the system-on-chip 1200 may include at least one processor of a Central Processing Unit (CPU), an Application Processor (AP), a Graphic Processing Unit (GPU), a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), a Visual Processing Unit (VPU), an Image Signal Processor (ISP), and a Digital Signal Processor (DSP) for performing a dedicated operation.

The system-on-chip 1200 may control the overall operation of the stacked memory device 1100. The system-on-chip 1200 may include a physical layer 1210. The physical layer 1210 may include: an interface circuit for transmitting and receiving input/output signals to and from the physical layer 1111 of the stacked memory device 1100. For example, the system-on-chip 1200 and the physical layer 1210 may correspond to the memory controller 100 and the host interface circuit 110 described with reference to fig. 1 through 12, respectively. The system-on-chip 1200 may provide various input/output signals to the physical layer 1111 through the physical layer 1210. Signals provided to physical layer 1111 may be transmitted to core dies 1120-1150 through interface circuitry of physical layer 1111 and TSV 1101.

Interposer 1300 may connect stacked memory device 1100 and system-on-chip 1200. The interposer 1300 may connect between the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system-on-chip 1200 and provide a physical path formed using a conductive material. Accordingly, the stacked memory device 1100 and the system-on-chip 1200 are stacked on the interposer 1300 to transmit/receive input/output signals.

The bumps 1103 may be attached to an upper portion of the package substrate 1400, and the solder balls 1104 may be attached to a lower portion of the package substrate 1400. For example, the bumps 1103 may be flip-chip bumps. The interposer 1300 may be stacked on the package substrate 1400 by bumps 1103. The semiconductor package 1000 may transmit and receive signals with other external packages or semiconductor devices through the solder balls 1104. For example, the package substrate 1400 may be a Printed Circuit Board (PCB).

In an example embodiment, the system-on-chip 1200 trains the bumps 1102 to transmit the input/output signals to the physical layer 1111 in accordance with each group, as described with reference to fig. 1 to 16. According to training, the output timing of the data signal output from the physical layer 1210 through one bump group of the system-on-chip 1200 may be the same. In order for the output data signals to reach the physical layer 1111 at the same timing, the lengths of signal lines of the interposer 1300 connecting one bump group of the system-on-chip 1200 and the corresponding bump group of the stacked memory device 1100 may be the same.

Fig. 18 is a diagram illustrating a semiconductor package according to some example embodiments of the inventive concepts. Referring to fig. 18, a semiconductor package 2000 may include a plurality of stacked memory devices 2100 and a system-on-chip 2200. The stacked memory device 2100 and the system-on-chip 2200 may be stacked on the interposer 2300, and the interposer 2300 may be stacked on the package substrate 2400. The semiconductor package 2000 may transmit and receive signals to and from other external packages or semiconductor devices through the solder balls 2001 attached at the lower portion of the package substrate 2400.

Each of the stacked memory devices 2100 may be implemented based on the HBM standard. However, the present invention is not limited thereto, and each of the stacked memory devices 2100 may be implemented based on GDDR, HMC, or a wide I/O standard. The stacked memory device 2100 may correspond to the stacked memory devices 300 and 1100 of fig. 13-17, respectively.

The system-on-chip 2200 may include at least one processor (e.g., a CPU, an AP, a GPU, and an NPU) and a plurality of memory controllers for controlling the plurality of stacked memory devices 2100. Each of the memory controllers may correspond to the memory controller 100 of fig. 1. The system-on-chip 2200 may transmit/receive input/output signals to/from the corresponding stacked memory device through the memory controller.

Fig. 19 is a block diagram illustrating a computing system according to some example embodiments of the inventive concepts. Computing system 3000 may be implemented as a single electronic device, or may be distributed and implemented over two or more electronic devices. For example, computing system 3000 may be implemented with at least one of the following electronic devices: desktop computers, laptop computers, tablet computers, smart phones, automotive vehicles, digital cameras, wearable devices, healthcare devices, server systems, data centers, drones, handheld gaming consoles, internet of things (IoT) devices, graphics accelerators, AI accelerators, and the like.

Referring to fig. 19, computing system 3000 may include a host 3100, an accelerator subsystem 3200, and an interconnect 3300. The host 3100 may control the overall operation of the accelerator subsystem 3200, and the accelerator subsystem 3200 may operate under the control of the host 3100. Host 3100 and accelerator subsystem 3200 may be connected through interconnect 3300. Various signals and data may be sent and received between host 3100 and accelerator subsystem 3200 through interconnect 3300.

The host 3100 may include a host processor 3110, a host memory controller 3120, a host memory 3130, and an interface 3140. The main processor 3110 may control overall operation of the computing system 3000. The host processor 3110 may control the host memory 3130 through the host memory controller 3120. Host processor 3110 may control accelerator subsystems 3200 connected through interconnect 3300. For example, host processor 3110 may send commands to accelerator subsystem 3200 to assign tasks to accelerator subsystem 3200.

Host processor 3110 may be a general-purpose processor or a main processor that performs general operations related to various operations of computing system 3000. The main processor 3110 may be a CPU or an AP, for example.

Host memory 3130 may be the main memory of computing system 3000. Host memory 3130 may store data processed by host processor 3110 or may store data received from accelerator subsystems 3200. For example, the host memory 3130 may be implemented with DRAM.

Interface 3140 may be configured to allow host 3100 to communicate with accelerator subsystem 3200. Host processor 3110 may send control signals and data to accelerator subsystem 3200 through interface 3140 and may receive signals and data from accelerator subsystem 3200. In an example embodiment, the host processor 3110, the host memory controller 3120, and the interface 3140 may be implemented as a single chip.

The accelerator subsystem 3200 may perform certain functions under the control of the host 3100. For example, accelerator subsystem 3200 may perform operations specific to a particular application under the control of host 3100. Accelerator subsystem 3200 may be implemented in various forms such as a module, card, package, chip or device, so as to be physically or electrically connected to host 3100, or may be connected to host 3100 either by wire or wirelessly. For example, accelerator subsystem 3200 may be implemented as one of the semiconductor packages described with reference to fig. 17 and 18. For example, accelerator subsystem 3200 may be implemented as a graphics card or an accelerator card. For example, accelerator subsystem 3200 may be implemented based on a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).

In an example embodiment, accelerator subsystem 3200 may be implemented based on one of a variety of packaging techniques. For example, accelerator subsystem 3200 may be implemented using packaging techniques such as: ball Grid Array (BGA), MCP (Multi chip Package), SOP (System in Package), SIP (System in Package), POP (Package on Package), chip level Package (CSP), Wafer Level Package (WLP), or Panel Level Package (PLP). As an example, some or all of the components of accelerator subsystem 3200 may be connected by copper-copper bonding. By way of example, some or all of the components of accelerator subsystem 3200 may be connected by an interposer, such as a silicon interposer, an organic interposer, a glass interposer, or an active interposer. As an example, some or all of the components of accelerator subsystem 3200 may be stacked on a TSV basis. As an example, some or all of the components of accelerator subsystem 3200 may be connected by high-speed connection channels (e.g., silicon bridges).

Accelerator subsystem 3200 may include a special purpose processor 3210, a local memory controller 3220, local memory 3230, and a host interface 3240. The special-purpose processor 3210 may operate under the control of the host processor 3110. For example, the dedicated processor 3210 may read data from the local memory 3230 through the local memory controller 3220 in response to a command of the host processor 3110. The dedicated processor 3210 may process the data by performing operations based on the read data. Dedicated processor 3210 may send the processed data to host processor 3110 or may write the processed data to local memory 3230.

Specialized processor 3210 may perform operations specific to a particular application based on values stored in local memory 3230. For example, the special purpose processor 3210 may perform operations specific to an application such as: artificial intelligence, stream analysis, video transcoding, data indexing, data encoding/decoding, and data encryption. Accordingly, the dedicated processor 3210 may process various types of data such as image data, voice data, motion data, biometrics data, and key values. For example, the special purpose processor 3210 may include at least one of a GPU, NPU, TPU, VPU, ISP, and DSP.

The special purpose processor 3210 may include one processor core, or may include a plurality of processor cores such as dual core, quad core, and quad core. In an example embodiment, the special purpose processor 3210 may include a greater number of cores than the host processor 3110 for parallelizing special purpose operations. For example, the special purpose processor 3210 may include 1000 or more cores.

The local memory controller 3220 may control the overall operation of the local memory 3230. In example embodiments, the local memory controller 3220 may perform Error Correction Code (ECC) encoding and ECC decoding, or perform data verification using a Cyclic Redundancy Check (CRC) method, or may perform data encryption and data decryption.

Local memory 3230 may be exclusively used by dedicated processor 3210. In an example embodiment, the local memory 3230 may be implemented in various forms such as a die, a chip, a package, a module, a card, or a device to be mounted on a board together with the dedicated processor 3210 or connected to the dedicated processor 3210 based on a separate connector.

In an example embodiment, local memory controller 3220 may correspond to memory controller 100 of fig. 1, and local memory 3230 may correspond to memory device 200 of fig. 1 and stacked memory device 300 of fig. 13. Thus, local memory controller 3220 may perform training on each set of pins of local memory 3230, and local memory controller 3220 and local memory 3230 may be configured to support set-specific training.

In an example embodiment, local memory 3230 may include logic circuitry capable of performing some operations. The logic circuits may perform linear operations, comparison operations, compression operations, data translation operations, arithmetic operations, etc., on data read from local store 3230 or data written to local store 3230. Therefore, the size of data processed by the logic circuit can be reduced. As the data size decreases, the bandwidth efficiency between the local memory 3230 and the local memory controller 3220 may increase.

Host interface 3240 may be configured such that accelerator subsystem 3200 communicates with host 3100. The accelerator subsystem 3200 may send signals and data to the host 3100 through the host interface 3240, and may receive control signals and data from the host 3100. In an example embodiment, the dedicated processor 3210, the local memory controller 3220, and the host interface 3240 may be implemented as a single chip.

Interconnect 3300 provides a data transmission path between host 3100 and accelerator subsystem 3200, and may serve as a data bus or data link. The data transmission path may be formed by wire or wirelessly. Interface 3140 and host interface 3240 may communicate over interconnect 3300 based on a predetermined protocol. For example, interfaces 3140 and 3240 may communicate based on one of various standards such as: advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (e-SATA), Small Computer System Interface (SCSI), serial attached SCSI (sas), Peripheral Component Interconnect (PCI), PCI express (pcie), nvm express (nvme), advanced extensible interface (AXI), ARM Microcontroller Bus Architecture (AMBA), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), universal flash memory (UFS), Compact Flash (CF), Gen-Z, and the like. Alternatively, interfaces 3140 and 3240 communicate based on a communication link between devices such as: open Coherent Accelerator Processor Interface (CAPI), cache coherent interconnect for accelerators (CCIX), compute express link (CXL), and NVLINK. Alternatively, interfaces 3140 and 3240 may communicate based on wireless communication techniques such as: LTE, 5G, LTE-M, NB-IoT, LPWAN, Bluetooth, Near Field Communication (NFC), Zigbee, Z-Wave, WLAN, etc.

In an example embodiment, accelerator subsystem 3200 may further comprise: a sensor capable of detecting image data, voice data, motion data, biological data, and ambient environment information. When sensors are included in accelerator subsystem 3200, the sensors may be connected to other components (e.g., dedicated processor 3210 and local memory 3230) based on the packaging techniques described above. Accelerator subsystem 3200 may process data sensed by sensors based on a particular operation.

Fig. 19 illustrates that the dedicated processor 3210 uses a local memory 3230 through a local memory controller 3220, but the present invention is not limited thereto. As an example, the dedicated processor 3210 may use a plurality of local memories through one local memory controller 3220. As another example, the dedicated processor 3210 may use local memory corresponding to each of a plurality of local memory controllers. As another example, the dedicated processor 3210 may use local memory corresponding to each of a plurality of local memory controllers.

Certain elements described herein, for example, "controllers" or "trees" or "repeaters" or "blocks of units" and/or certain elements ending with a "device" may be embodied as hardware or a combination of hardware and software. For example, an element may comprise processing circuitry, such as hardware comprising logic circuitry; a hardware/software combination such as a processor executing software; or a combination of both. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.