阅读说明：本技术 存储器控制器装置与相位校正方法 (Memory controller device and phase correction method ) 是由 郑杰 于 2020-04-29 设计创作，主要内容包括：本申请提供了存储器控制器装置和相位校正方法。存储器控制器装置包含延迟线电路系统、多个数据取样电路、多个相位检测电路以及控制逻辑电路。延迟线电路系统延迟数据选通信号以产生第一至第三时钟信号,其中第二时钟信号用来读取数据信号,且第一至第三时钟信号的相位按序相差一预定值。每一数据取样电路根据第一至第三时钟信号中一对应者对数据信号取样,以产生第一至第三信号中的对应者。多个相位检测电路比较第一信号与第二信号以产生第一检测信号,并比较第三信号与第二信号以产生第二检测信号。控制逻辑电路根据第一检测信号与第二检测信号调整第一至第三时钟信号。(The application provides a memory controller apparatus and a phase correction method. The memory controller device includes a delay line circuitry, a plurality of data sampling circuits, a plurality of phase detection circuits, and a control logic circuit. The delay line circuit system delays the data strobe signal to generate first to third clock signals, wherein the second clock signal is used for reading the data signal, and the phases of the first to third clock signals are sequentially different by a predetermined value. Each data sampling circuit samples a data signal according to a corresponding one of the first to third clock signals to generate a corresponding one of the first to third signals. The plurality of phase detection circuits compare the first signal with the second signal to generate a first detection signal, and compare the third signal with the second signal to generate a second detection signal. The control logic circuit adjusts the first to third clock signals according to the first detection signal and the second detection signal.)

1. A memory controller device, comprising:

a delay line circuit system for delaying a data strobe signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used for reading a data signal, and the phase of the first clock signal, the phase of the second clock signal and the phase of the third clock signal sequentially differ by a predetermined value;

a plurality of data sampling circuits, wherein each of the plurality of data sampling circuits is configured to sample the data signal according to a corresponding one of the first clock signal, the second clock signal, and the third clock signal to generate a corresponding one of a first signal, a second signal, and a third signal;

a plurality of phase detection circuits for comparing the first signal with the second signal to generate a first detection signal and comparing the third signal with the second signal to generate a second detection signal; and

and a control logic circuit for adjusting the first clock signal, the second clock signal and the third clock signal according to the first detection signal and the second detection signal.

2. The memory controller device of claim 1, wherein the delay line circuitry comprises:

a plurality of buffer circuits, wherein the plurality of buffer circuits are sequentially coupled in series and configured to delay the data strobe signal; and

a plurality of multiplexer circuits, wherein each of the plurality of multiplexer circuits is configured to output an output signal of a corresponding one of the plurality of buffer circuits as a corresponding one of the first clock signal, the second clock signal, and the third clock signal according to a corresponding one of a first selection signal, a second selection signal, and a third selection signal,

the control logic circuit is further configured to output the first selection signal, the second selection signal, and the third selection signal in response to the first detection signal and the second detection signal to adjust the first clock signal, the second clock signal, and the third clock signal.

3. The memory controller device of claim 1, wherein the control logic is configured to gradually increase the predetermined value to a predetermined maximum value in response to the first detection signal and the second detection signal if the second signal is the same as each of the first signal and the third signal.

4. The memory controller device of claim 1, wherein the control logic is to maintain the phase of the second clock signal in response to the first detection signal and the second detection signal if the second signal is the same as each of the first signal and the third signal.

5. The memory controller device of claim 1, wherein the control logic is to shift a phase of the second clock signal in response to the first detection signal and the second detection signal if the second signal is the same as one of the first signal and the third signal and different from the other of the first signal and the third signal.

6. The memory controller device of claim 1, wherein the control logic is configured to maintain the predetermined value in response to the first detection signal and the second detection signal if the second signal is the same as one of the first signal and the third signal and different from the other of the first signal and the third signal.

7. The memory controller device of claim 1, wherein the control logic is configured to set the predetermined value to a predetermined minimum value in response to the first detection signal and the second detection signal if the second signal is different from each of the first signal and the third signal, and to determine whether the second signal is the same as the first signal and the third signal according to the first detection signal and the second detection signal received at a next stage.

8. The memory controller device of claim 7, wherein the control logic is further configured to reset a phase of the second clock signal if the control logic determines that the second signal is different from each of the first signal and the third signal.

9. The memory controller device of claim 1, wherein the phase detection circuit comprises:

a first phase detection circuit for outputting the first detection signal having a first logic value when the first signal is the same as the second signal, and outputting the first detection signal having a second logic value when the first signal is different from the second signal; and

a second phase detection circuit for outputting the second detection signal having the first logic value when the third signal is the same as the second signal, and outputting the second detection signal having the second logic value when the third signal is different from the second signal.

10. A method of phase correction, comprising:

delaying a data strobe signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used for reading a data signal, and the phase of the first clock signal, the phase of the second clock signal and the phase of the third clock signal sequentially differ by a predetermined value;

sampling the data signal according to a corresponding one of the first clock signal, the second clock signal and the third clock signal to generate a corresponding one of a first signal, a second signal and a third signal;

comparing the first signal with the second signal to generate a first detection signal, and comparing the third signal with the second signal to generate a second detection signal; and

the first clock signal, the second clock signal and the third clock signal are adjusted according to the first detection signal and the second detection signal.

Technical Field

The present disclosure relates to a memory controller device, and more particularly, to a data reading circuit and a phase calibration method without using an analog phase locked loop.

Background

In some common memories, the read and write operations are performed according to a data strobe (data strobe) signal. In order to correctly read the data stored in the memory, the phase of the data strobe signal needs to be aligned with the data window. However, as operating conditions (e.g., temperature, voltage) change, the phase of the data strobe signal may drift, causing incorrect data to be read.

Disclosure of Invention

In some embodiments, a memory controller device includes a delay line circuitry, a plurality of data sampling circuits, a plurality of phase detection circuits, and control logic. The delay line circuit system is used for delaying a data strobe (data strobe) signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used for reading a data signal, and the phase of the first clock signal, the phase of the second clock signal and the phase of the third clock signal sequentially differ by a preset value. Each of the data sampling circuits is used for sampling the data signal according to a corresponding one of the first clock signal, the second clock signal and the third clock signal to generate a corresponding one of the first signal, the second signal and the third signal. The phase detection circuits are used for comparing the first signal with the second signal to generate a first detection signal and comparing the third signal with the second signal to generate a second detection signal. The control logic circuit is used for adjusting the first clock signal, the second clock signal and the third clock signal according to the first detection signal and the second detection signal.

In some embodiments, the phase correction method comprises the following operations: delaying the data strobe signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used for reading a data signal, and the phase of the first clock signal, the phase of the second clock signal and the phase of the third clock signal sequentially differ by a preset value; sampling the data signal according to a corresponding one of the first clock signal, the second clock signal and the third clock signal to generate a corresponding one of the first signal, the second signal and the third signal; comparing the first signal with the second signal to generate a first detection signal, and comparing the third signal with the second signal to generate a second detection signal; and adjusting the first clock signal, the second clock signal and the third clock signal according to the first detection signal and the second detection signal.

The features, implementations, and technical advantages of the present disclosure will be described in detail with reference to the accompanying drawings.

Drawings

FIG. 1A is a schematic drawing depicting an electronic system according to some embodiments of the present disclosure;

FIG. 1B is a schematic diagram of waveforms of the relevant signals of FIG. 1A, according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of the memory controller device of FIG. 1A, constructed in accordance with some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of the delay line circuitry of FIG. 2, constructed in accordance with some embodiments of the present disclosure;

FIG. 4A is a flow chart of a method of phase correction according to some embodiments of the present disclosure;

FIG. 4B is a flowchart of an operation of FIG. 4A, according to some embodiments of the present disclosure; and

fig. 5 is a schematic illustration of the correlation waveforms of fig. 2 plotted according to some embodiments of the present disclosure.

Description of the symbols

100: electronic system

110: processing circuit

120: memory controller device

130: memory device

CLK 1-CLK 3: clock signal

D0-D3: data of

DQ: data signal

DQS: data strobe signal

N1, N2: negative edge

P1, P2: front edge

S1-S3: signal

And (3) Texp: predetermined time

210: delay line circuit system

220,222,224: data sampling circuit

230,232: phase detection circuit

240: control logic circuit

j _ max: preset maximum value

j _ min: preset minimum value

n _ max: preset maximum value

SEL 1-SEL 3: selection signal

310: buffer circuit

320,330,340: multiplexer circuit

O1-Om: output signal

T: delay time

400: phase correction method

S410, S420, S430, S440, S450: operation of

S1-1 to S1-4, S2-1 to S2-3, S3-1 to S3-3, S4-1 to S4-5: step (ii) of

n: phase position

j: preset value

Detailed Description

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in this disclosure is intended to be exemplary only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to two or more elements operating or acting together. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected by at least one transistor and/or at least one active and passive component in a certain manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first element can be termed a second element herein without departing from the spirit of the present disclosure. For ease of understanding, like elements in the various figures will be designated with the same reference numerals.

Fig. 1A is a schematic diagram of an electronic system 100, according to some embodiments of the present disclosure. In some embodiments, the electronic system 100 can be any type of electronic device (e.g., a computer, a smart phone, etc.) that uses a memory. Electronic system 100 includes processing circuit 110, memory controller device 120, and memory 130.

In some embodiments, the processing circuit 110 may be a central processing unit circuit, a microprocessor circuit, or the like having an operational capability of executing software. In some embodiments, the processing circuit 110 may be various types of data processing chips. The processing circuit 110 may read data signals DQ from the memory 130 via the memory controller device 120. The memory controller device 120 may operate as an interface circuit between the processing circuit 110 and the memory 130, which may be used to generate a clock signal CLK2 (as shown in fig. 1B) according to a data strobe (data strobe) signal DQS from the memory 130. The memory controller device 120 may automatically adjust the phase of the clock signal CLK2 and read the data of the data signal DQ according to the clock signal CLK2 to output the signal S2 to the processing circuit 110. Through the operation of the memory controller device 120, it is ensured that the processing circuit 110 can obtain valid data in the data signal DQ by reading the signal S2.

In some embodiments, the memory 130 may be a Double Data Rate (DDR) synchronous dynamic random access memory. In some embodiments, the memory 130 may be a Single Data Rate (SDR) synchronous dynamic random access memory. The types described above with respect to memory 130 are for example and the disclosure is not so limited. In other embodiments, the memory 130 may be various memories that read/write data using the data strobe signal DQS.

FIG. 1B is a waveform diagram of the relevant signals of FIG. 1A, plotted according to some embodiments of the present disclosure. In this example, the memory 130 is a DDR SDRAM. In read and write operations of the DDR synchronous dynamic random access memory, the data strobe signal DQS is either edge-aligned with the data signal DQ or center-aligned with the data signal DQ.

For example, in a data write operation, the memory device 130 stores one data according to each of the positive and negative edges of the data strobe signal DQS. For example, the memory 130 stores data D0 at a positive edge P1 of the data strobe signal DQS and stores data D1 at a negative edge N1 of the data strobe signal DQS. By analogy, the memory 130 stores the data D2 and the data D3 at the positive edge P2 and the negative edge N2 in sequence.

Alternatively, in a data read operation, the memory 130 sends the data strobe signal DQS and the data signal DQ to the processing circuit 110, and the processing circuit 110 may delay the data strobe signal DQS by a predetermined time Texp through software (or firmware) to generate the clock signal CLK 2. By delaying the predetermined time Texp, the phase of the clock signal CLK2 and the phase of the data signal DQ have a phase difference of about 90 degrees. Thus, the positive and negative edges of the clock signal CLK2 may be aligned with the center of the data D0D 3. The memory controller device 120 may read the data signal DQ according to the positive edge or the negative edge of the clock signal CLK2 to output valid data in the data signal DQ as a signal S2 to the processing circuit 110. In some embodiments, the memory controller device 120 may automatically adjust the phase of the clock signal CLK2 to avoid the phase of the clock signal CLK2 from drifting due to variations in operating conditions (e.g., temperature, voltage, etc.). In this way, it is ensured that the processing circuit 110 can stably read valid data of the data signal DQ.

FIG. 2 is a schematic diagram of the memory controller device 120 of FIG. 1A, according to some embodiments of the present disclosure. In some embodiments, the memory controller device 120 includes a delay line circuitry 210, a plurality of data sampling circuits 220,222, and 224, a plurality of phase detection circuits 230 and 232, and a control logic circuit 240.

The delay line circuitry 210 receives the data strobe signal DQS from the memory 130 and delays the data strobe signal DQS to generate the clock signal CLK1, the clock signal CLK2, and the clock signal CLK 3. The phase of the clock signal CLK1, the phase of the clock signal CLK2, and the phase of the clock signal CLK3 are sequentially different by a predetermined value j. For example, if the phase of the clock signal CLK2 is denoted as n, the phase of the clock signal CLK1 may be denoted as n-j, and the phase of the clock signal CLK3 may be denoted as n + j. In other words, the phase of the clock signal CLK1 lags the phase of the clock signal CLK2 by a predetermined value j, and the phase of the clock signal CL3 leads the phase of the clock signal CLK2 by a predetermined value j. In some embodiments, each of the phase n and the predetermined value j may be represented as a data value, and the control logic circuit 240 may update the selection signal SEL1, the selection signal SEL2, and the selection signal SEL3 according to the data values. The delay line circuitry 210 may adjust the clock signals CLK1, CLK2, and CLK3 according to the select signal SEL1, the select signal SEL2, and the select signal SEL 3.

Each of the plurality of data sampling circuits 220,222, and 224 is configured to sample the data signal DQ according to a corresponding one of the clock signals CLK1, CLK2, and CLK2 to generate a corresponding one of the signals S1, S2, and S3. In detail, the data sampling circuit 220 may be triggered according to the positive edge (and/or the negative edge) of the clock signal CLK1 to output the data signal DQ as the signal S1. The data sampling circuit 222 may be triggered according to a positive edge (and/or a negative edge) of the clock signal CLK2 to output the data signal DQ as the signal S2 and provide the signal S2 to the processing circuit 110 of fig. 1A. In other words, as described above with reference to FIG. 1A, the clock signal CLK2 is used to read the data signal DQ. The data sampling circuit 224 may be triggered according to the positive edge (and/or the negative edge) of the clock signal CLK3 to output the data signal DQ as the signal S3.

In some embodiments, each of the plurality of data sampling circuits 220,222, and 224 may be implemented by, but not limited to, a D-type flip-flop circuit. The above embodiments of the plurality of data sampling circuits 220,222 and 224 are used for illustration, and various sampling circuits capable of acquiring current data according to the clock signal are all within the scope of the present disclosure.

The phase detecting circuits 230 and 232 are used for comparing the signal S1 with the signal S2 to generate a detecting signal D1, and comparing the signal S3 with the signal S2 to generate a detecting signal D2. For example, the phase detection circuit 230 may be used to compare the signal S1 with the signal S2. If the signal S1 is the same as the signal S2, the phase detection circuit 230 can output the detection signal D1 having a first logic value (e.g., logic value 1). Alternatively, if the signal S1 is different from the signal S2, the phase detection circuit 230 may output the detection signal D1 having a second logic value (e.g., logic value 0). Similarly, the phase detection circuit 232 may be used to compare the signal S3 with the signal S2. If the signal S3 is the same as the signal S2, the phase detection circuit 232 can output the detection signal D2 having the first logic value. Alternatively, if the signal S3 is different from the signal S2, the phase detection circuit 232 may output the detection signal D2 having the second logic value.

In some embodiments, each of the plurality of phase detection circuits 230 and 232 may be implemented by, but not limited to, an exclusive nor (XNOR) gate. The above embodiments of the phase detection circuits 230 and 232 are used for illustration, and various detection circuits capable of determining whether the data values are the same are all within the scope of the present disclosure.

The control logic 240 is configured to adjust the clock signal CLK1, the clock signal CLK2 and the clock signal CLK3 according to the detection signal D1 and the detection signal D2 to ensure that the phase of the clock signal CLK2 is stably aligned with the center of the data valid interval in the data signal DQ. In some embodiments, the control logic 240 is configured to output the select signal SEL1, the select signal SEL2 and the select signal SEL3 according to the detection signal D1 and the detection signal D2. The description about this will be described later with reference to fig. 2 to 5.

In some embodiments, the control logic circuit 240 may include at least one register for storing a predetermined maximum value j _ max, a predetermined minimum value j _ min, and a predetermined maximum value n _ max. The preset maximum value j _ max and the preset minimum value j _ min are used to set the range of the preset value j, and the preset maximum value n _ max is used to set the upper limit of the phase n of the clock signal CLK 2. In some embodiments, the values may be set automatically by software executed by the processing circuit 110 or may be input directly by a user. In some embodiments, such values may be used to adjust the speed at which the phase of the clock signal CLK2 is tracked.

In some embodiments, the control logic 240 may be implemented by at least one digital circuit. In some embodiments, the at least one digital circuit may be configured to execute a state machine corresponding to operations S420 through S450 of fig. 4A described below. In some embodiments, the at least one digital circuit may be, but is not limited to, a digital signal processing circuit, a microcontroller, or the like.

Fig. 3 is a schematic diagram of the delay line circuitry 210 of fig. 2, constructed in accordance with some embodiments of the present disclosure. In some embodiments, the delay line circuit system 210 includes a plurality of buffer circuits 310 and a plurality of multiplexer circuits 320,330, and 340. The plurality of buffer circuits 310 are coupled in series in sequence to delay the data strobe signal DQS. The output signals O1-Om of the buffer circuits 310 are transmitted to each of the multiplexer circuits 320,330 and 340. Each of the multiplexer circuits 320,330, and 340 may output a corresponding one of the output signals O1-Om as a corresponding one of the clock signals CLK1, CLK2, and CLK3 according to a corresponding one of the selection signal SEL1, the selection signal SEL2, and the selection signal SEL.

For example, the multiplexer circuit 330 may output the output signal On of the plurality of output signals O1-Om as the clock signal CLK2 according to the selection signal SEL 2. The multiplexer circuit 320 may output an output signal On-j (not shown) of the output signals O1-Om as a clock signal CLK1 according to the selection signal SEL 1. The multiplexer circuit 340 may output an output signal On + j (not shown) of the output signals O1-Om as the clock signal CLK3 according to the selection signal SEL 3. In other words, if one buffer circuit 310 introduces a delay time T, the clock signal CLK2 can be regarded as the data strobe signal DQS delayed by n buffer circuits 310. By analogy, the clock signal CLK1 may be regarded as the data strobe DQS delayed by n-j buffer circuits 310, and the clock signal CLK3 may be regarded as the data strobe DQS delayed by n + j buffer circuits 310. In some embodiments, the processing circuit 110 may select n buffer circuits 310 through software (or firmware) and delay the data strobe signal DQS through the n buffer circuits 310 to generate the clock signal CLK 2. In other words, the predetermined time Texp in fig. 1B corresponds to the sum of the n delay times T.

The operation of the memory controller device 120 is described with reference to fig. 2, 4A, 4B and 5. Fig. 4A is a flowchart of a phase correction method 400 according to some embodiments of the present disclosure, fig. 4B is a flowchart of operation S450 of fig. 4A according to some embodiments of the present disclosure, and fig. 5 is a schematic diagram of related waveforms of fig. 2 according to some embodiments of the present disclosure. In some embodiments, the phase correction method 400 may be performed by, but is not limited to, the control logic 240 of fig. 2.

In operation S410, after the electronic system 100 is powered on (powered), the phase of the clock signal CLK2 is automatically corrected to be phase n. For example, when the electronic system 100 is powered on, the processing circuit 110 may execute a software to issue a reset command (not shown) to the delay line circuit system 210. In response to the reset command, the delay line circuit system 210 may delay the data strobe signal DQS by a predetermined time Texp to generate the clock signal CLK2 having a phase n that is about 90 degrees out of phase with the data strobe signal DQS (as shown in fig. 1B earlier).

In operation S420, the data strobe signal DQS is delayed and the clock signals CLK1, CLK2, and CLK3 are generated according to the select signal SEL1, the select signal SEL2, and the select signal SEL 3. In operation S430, the data signal DQ is sampled according to the clock signal CLK1 to generate a signal S1, the data signal DQ is sampled according to the clock signal CLK2 to generate a signal S2, and the data signal DQ is sampled according to the clock signal CLK3 to generate a signal S3. In operation S440, the signal S1 is compared with the signal S2 to generate the detection signal D1, and the signal S3 is compared with the signal S2 to generate the detection signal D2. The operations S420, S430 and S440 can refer to the descriptions of fig. 2 and fig. 3, and thus are not repeated herein.

In operation S450, the select signal SEL1, the select signal SEL2 and the select signal SEL3 are updated according to the detection signal D1 and the detection signal D2 to adjust the phase of the clock signal CLK1, the phase of the clock signal CLK2 and the phase of the clock signal CLK 3. By repeatedly performing operations S420 to S450, the memory controller device 120 may automatically adjust the phase of the clock signal CLK to ensure that the processing circuit 110 can stably read valid data.

To understand operation S450, referring to FIGS. 4B and 5, operation S450 may include a plurality of steps S1-1 through S1-4, S2-1 through S2-3, S3-1 through S3-3, and S4-1 through S4-5.

In step S1-1, phase n is maintained. In step S1-2, it is determined whether the preset value j is the preset maximum value j _ max. If the preset value j is not the preset maximum value j _ max, the step S1-3 is executed. In step S1-3, a predetermined value j is added. If the preset value j is the preset maximum value j _ max, the step S1-4 is executed. In step S1-4, the select signal SEL1, the select signal SEL2 and the select signal SEL3 are updated.

For example, as shown in FIG. 5, in the first case, the sampling points corresponding to the phase n-j of the clock signal CLK1, the phase n of the clock signal CLK2 and the phase n + j of the clock signal CLK3 all fall within the data valid interval (i.e., near the center region of the data window) of the data signal DQ. Under this condition, the signal S2 is identical to each of the signals S1 and S3, so the detection signal D1 and the detection signal D2 both have the first logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the phase n (i.e., step S1-1) and gradually increase the predetermined value j to the preset maximum value j _ max (i.e., step S1-2 to step S1-4) to increase the boundary of the data sample (margin). Thus, the sampling points can cover the whole range of the effective interval of the data as much as possible.

With continued reference to FIG. 4B, in step S2-1, the preset value j is maintained. In step S2-2, phase n is decreased. In step S2-3, the select signal SEL1, the select signal SEL2 and the select signal SEL3 are updated. For example, as shown in FIG. 5, in the second case, the sampling points corresponding to the phases n-j of the clock signal CLK1 and the phase n of the clock signal CLK2 all fall within the data valid interval of the data signal DQ, and the sampling point corresponding to the phase n + j of the clock signal CLK3 falls within the data ambiguity (represented by the dotted area, i.e., the area near the transition edge) of the data signal DQ. Under this condition, the signal S2 is the same as the signal S1 and different from the signal S3, so the detection signal D1 has a first logic value and the detection signal D2 has a second logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 maintains the preset value j (i.e., step S2-1) and shifts the phase n left (i.e., step S2-2). Thus, the sampling points can be corrected back to the valid data interval.

With continued reference to FIG. 4B, in step S3-1, the preset value j is maintained. In step S3-2, phase n is incremented. In step S3-3, the select signal SEL1, the select signal SEL2 and the select signal SEL3 are updated. For example, as shown in FIG. 5, in the third case, the sampling point corresponding to the phase n-j of the clock signal CLK1 falls within the data ambiguity of the data signal DQ, and the sampling points corresponding to the phase n of the clock signal CLK2 and the phase n + j of the clock signal CLK3 all fall within the data valid interval. Under this condition, the signal S2 is the same as the signal S3 and different from the signal S1, so the detection signal D1 has the second logic value and the detection signal D2 has the first logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 maintains the preset value j (i.e., step S3-1) and shifts the phase n to the right (i.e., step S3-2). Thus, the sampling points can be corrected back to the valid data interval. In other words, when the signal S2 is different from one of the signal S1 and the signal S3 and the same as the other of the signal S1 and the signal S3 (i.e., the second case or the third case), the control logic circuit 240 can ensure that valid data can be sampled by shifting the phase n of the clock signal CLK 2.

With continued reference to FIG. 4B, in step S4-1, the phase n is maintained and the preset value j is set to the preset minimum value j _ min. In step S4-2, the select signal SEL1, the select signal SEL2 and the select signal SEL3 are updated. In step S4-3, it is determined whether the signal S2 is the same as the signal S1 and the signal S3 according to the detection signal D1 and the detection signal D2 received in the next cycle. If the signal S2 is different from each of the signals S1 and S3, go to step S4-4. If the signal S2 is the same as each of the signals S1 and S3, step S4-5 is performed. In step S4-4, phase n is reset. In step S4-5, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated.

For example, as shown in fig. 5, the fourth scenario may occur under two conditions. Under a first condition, phase n is corrupted such that at least two sample points (including the sample point corresponding to phase n) fall within the data ambiguity region. Under the second condition, the default value j is too large, so that a plurality of sampling points corresponding to the phases n-j of the clock signal CLK1 and the phase n + j of the clock signal CLK3 fall into the data ambiguity region. Under both conditions, the signal S2 is different from each of the signals S1 and S3, so the detection signal D1 and the detection signal D2 both have the second logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the phase n and set the predetermined value j to the predetermined minimum value j _ min (i.e., step S4-1), and determine whether the signal S2 is the same as the signal S1 and the signal S3 according to the detection signal D1 and the detection signal D2 received in the next stage (i.e., step S4-2 and step S4-3).

It should be understood that if the predetermined value j is the predetermined minimum value j _ min and the subsequent signal S2 is still different from each of the signals S1 and S3, it indicates that the phase n is erroneous, such that at least two sampling points (including the sampling point corresponding to the phase n) are still in the data ambiguity region (i.e., the aforementioned first condition occurs). Under this condition, the detection signals D1 and D2 still have the second logic value. In response to the detection signal D1 and the detection signal D2, the control logic 240 resets the phase n (i.e., step S4-4) to correct the plurality of sampling points back to the valid data interval. Alternatively, if the predetermined value j is the predetermined minimum value j _ min and the subsequent signal S2 is the same as each of the signals S1 and S3, the predetermined value j is too large (i.e., the second condition occurs). Under this condition, the detection signals D1 and D2 both have the first logic value, and the selection signal SEL1, SEL2 and SEL3 can be updated according to the current related parameters. In other words, by decreasing the default value j, it is sufficient to correct the plurality of sampling points back to the valid interval of data.

The above operations are merely examples, and need not be performed in the order in this example. Various operations under the phase correction method 400 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner of operation and scope of various embodiments of the disclosure. Alternatively, one or more of the operations under phase correction method 400 may be performed simultaneously or partially simultaneously.

In summary, the memory controller apparatus and the phase calibration method in some embodiments of the disclosure may not need to employ an analog circuit such as a phase-locked loop to automatically adjust the phase of the clock signal for reading the data signal. Thus, the circuit layout and the phase adjustment mechanism can be simplified. In addition, in some embodiments of the present disclosure, the related parameters for phase tracking can be set in a software manner, so that the present disclosure has high flexibility in use.

Although the embodiments of the present disclosure have been described above, the embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of patent protection sought by the present disclosure, in other words, the scope of patent protection of the present disclosure should be subject to the claims of the present specification.