阅读说明：本技术 阵列板短路修复 (Array board short circuit repair ) 是由 S·J·洛维特 R·E·法肯索尔 于 2019-06-05 设计创作，主要内容包括：本发明涉及阵列板短路修复。描述用于操作一或多个铁电存储器单元的方法、系统、技术及装置。单元群组可取决于(例如)所述单元群组、单元页及/或单元区段的单元板之间的关系以不同方式操作。可成对地或以更大倍数选择单元以便适应一群组、一页及/或一区段内的两个或两个以上单元之间的电流关系(例如短路)。当基于较小页尺寸执行存取时,可选择较大页尺寸的单元以适应所述较小页、所述较大页及/或包含所述较小页或所述较大页的存储器区段内的板之间的短路。(The invention relates to array board short circuit repair. Methods, systems, techniques, and devices for operating one or more ferroelectric memory cells are described. Cell groups may operate differently depending on, for example, the relationship between cell plates of the cell groups, cell pages, and/or cell sectors. Cells may be selected in pairs or greater multiples in order to accommodate current relationships (e.g., shorts) between two or more cells within a group, page, and/or a sector. When an access is performed based on a smaller page size, cells of a larger page size may be selected to accommodate shorts between the smaller page, the larger page, and/or plates within a memory segment that includes the smaller page or the larger page.)

1. A method, comprising:

Receiving a memory access command for a memory access operation associated with a first page size of memory cells;

Identifying, based at least in part on the memory access command, a first page of memory cells to be activated for the memory access operation, the first page having the first page size;

Determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size; and

Activating the second page of memory cells based at least in part on determining that there is a short circuit associated with the at least one memory cell.

2. The method of claim 1, wherein determining whether there is a short circuit associated with the at least one memory cell comprises:

Determining whether a first plate associated with the at least one memory cell of the second page is shorted to a second plate associated with at least a second memory cell of the second page.

3. The method of claim 2, wherein the at least the second memory cells are included in the first page and the at least the second memory cells are not included in the first page.

4. The method of claim 1, wherein the second page of memory cells comprises a third page of memory cells separate from the first page, the method further comprising:

Activating a first access line associated with the first page of memory cells and a second access line associated with the third page of memory cells based at least in part on the determination that there is a short circuit associated with the at least one memory cell, wherein activating the second page of memory cells comprises activating the first access line and the second access line.

5. The method of claim 4, wherein the first access line and the second access line are a first plate line and a second plate line, or a first digit line and a second digit line.

6. The method of claim 2, wherein activating the second page comprises:

Activating a first word line associated with the first page, an

A digit line and a plate line associated with the at least the second memory cell are activated without activating a second word line associated with the at least the second memory cell.

7. The method of claim 4, further comprising:

Activating a first driver associated with the first access line and a second driver associated with the second access line based at least in part on the determination that there is a short circuit associated with the at least one memory cell, wherein activating the second page of memory cells comprises activating the first driver and the second driver.

8. The method of claim 4, further comprising:

activating a first plurality of sense amplifiers associated with the first page of memory cells and a second plurality of sense amplifiers associated with the third page of memory cells based at least in part on the determination that there is a short circuit associated with the at least one memory cell.

9. The method of claim 2, wherein the first board is a first shared board associated with a first plurality of memory cells including the at least one memory cell, and the second board is a second shared board associated with a second plurality of memory cells including the at least the second memory cell.

10. The method of claim 2, wherein the first board is a first cell board associated with the at least one memory cell and the second board is a second cell board associated with the at least the second memory cell.

11. The method of claim 2, wherein the first plate and the second plate are adjacent plates in a patch comprising a plurality of plates associated with a plurality of memory cells, the method further comprising:

Activating all of the plurality of memory cells in the patch based at least in part on the determination that there is a short associated with the at least one memory cell.

12. The method of claim 2, wherein the first plate and the second plate are in different patches.

13. The method of claim 2, further comprising:

Performing the memory access operation on the second page of memory cells.

14. The method of claim 13, wherein performing the memory access operation on the second page comprises:

Generating a first set of data for the first page and a second set of data for a remaining plurality of cells in the second page;

Transmitting the first set of data; and

Refraining from transmitting the second set of data.

15. The method of claim 1, further comprising:

Activating the first page of memory cells without activating a remaining plurality of cells in the second page based at least in part on determining that there is no short associated with the at least one memory cell.

16. The method of claim 1, wherein the memory access command specifies the first page size.

17. The method of claim 1, wherein determining whether there is a short circuit associated with the at least one memory cell comprises receiving a signal indicating whether there is a short circuit associated with the at least one memory cell.

18. An electronic memory apparatus, comprising:

A memory array comprising a first page of memory cells having a first page size and a second page of memory cells comprising the first page and having a second page size;

A command component configured to:

Receiving a memory access command associated with the first page size memory cells in the memory array, an

Sending, based at least in part on the memory access command, a range of addresses associated with the first page of memory cells; and

A logic component coupled with the command component and the memory array, the logic component configured to:

Receiving the address range associated with the first page of memory cells from the command component, an

Activating a signal based at least in part on the address range and in response to determining that there is a short associated with at least one memory cell of the second page of memory cells, wherein the memory array is configured to activate the second page of memory cells based at least in part on the activation of the signal.

19. The electronic memory device of claim 18, further comprising:

A first plate associated with the at least one memory cell; and

A second plate associated with at least a second memory cell in the second page, wherein the determination that there is a short associated with the at least one memory cell comprises determining that the first plate is shorted to the second plate.

20. the electronic memory device of claim 19, wherein activating the second page of memory cells comprises activating the first plate and the second plate.

21. The electronic memory device of claim 19, wherein the first board is a first shared board associated with a first plurality of memory cells including the at least one memory cell, and the second board is a second shared board associated with a second plurality of memory cells including the at least the second memory cell.

22. The electronic memory device of claim 19, wherein the logic component comprises an or tree.

23. An electronic memory apparatus, comprising:

a memory array comprising a plurality of layers of memory cells each comprising a plurality of sections of memory cells divided into a plurality of pages;

A command component configured to:

Receiving a memory access command associated with a first page size, an

Sending, based at least in part on the memory access command, an indication of a segment number associated with a first page of the plurality of pages, wherein the first page has the first page size and is in a first segment associated with the segment number; and

A logic component coupled with the command component and the plurality of layers, the logic component configured to:

receiving said indication of said segment number, an

Activating a signal in response to determining that there is a short associated with at least one memory cell in a second section associated with the section number based at least in part on the indication, wherein the memory array is configured to activate all of the memory cells in the first section based at least in part on the activation of the signal.

24. The electronic memory device of claim 23, wherein the second section is in a different layer than the first section.

25. The electronic memory apparatus of claim 23, wherein the second section and the first section are the same section in the same layer.

Technical Field

Background

The following generally relates to memory devices and, more particularly, to selection of and operation related to cell plates.

Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, which are generally designated by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, the electronic device may read or sense a stored state in the memory device. To store information, the electronic device may write or program a state in the memory device.

There are various types of memory devices, including Random Access Memory (RAM), Read Only Memory (ROM), Dynamic RAM (DRAM), Synchronous Dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), flash memory, and others. The memory devices may be volatile or non-volatile. Non-volatile memory, such as flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAMs) may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charging or discharging capacitor. The charged capacitor may become discharged over time through leakage current, resulting in a loss of stored information. Certain aspects of volatile memory may provide performance advantages, such as faster read or write speeds, while aspects of non-volatile memory (such as the ability to store data without periodic refresh) may be advantageous.

FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Thus, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices. In certain FeRAM designs (as well as other design types), vertically cut cell plates or other closely spaced cell plates and other components may include one or more non-ideal or undesirable relationships or communications that render the cell plates, other elements, and/or other components unusable, and potentially require numerous redundant and expensive memory elements.

Disclosure of Invention

In one example, a method comprises: receiving a memory access command for a memory access operation associated with a first page size of memory cells; identifying, based at least in part on the memory access command, a first page of memory cells to be activated for the memory access operation, the first page having the first page size; determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size; and activating the second page of memory cells based at least in part on determining that there is a short circuit associated with the at least one memory cell.

In one example, an electronic memory apparatus or memory device includes: a memory array comprising a first page of memory cells having a first page size and a second page of memory cells including the first page and having a second page size. The electronic memory apparatus or memory device also includes: a command component configured to: a memory access command associated with memory cells of the first page size in the memory array is received, and an address range associated with the first page of memory cells is sent based at least in part on the memory access command. The electronic memory apparatus or memory device also includes: a logic component coupled with the command component and the memory array, the logic component configured to: receiving, from the command component, an address range associated with the first page of memory cells, and activating a signal based at least in part on the address range and in response to determining that there is a short circuit associated with at least one memory cell of the second page of memory cells, wherein the memory array is configured to activate the second page of memory cells based at least in part on the activation of the signal.

In one example, an electronic memory apparatus or memory device includes: a memory array including a set of layers each including a set of memory cell segments divided into a set of pages of memory cells. The electronic memory apparatus or memory device also includes: a command component configured to: a memory access command associated with a first page size is received, and an indication of a segment number associated with a first page of the set of pages is sent based at least in part on the memory access command, wherein the first page has the first page size and is in a first section associated with the segment number. The electronic memory apparatus or memory device also includes: a logic component coupled with the command component and the set of layers, the logic component configured to: receiving the indication of the segment number, and based at least in part on the indication, activating a signal in response to determining that there is a short associated with at least one memory cell in a second segment associated with the segment number, wherein the memory array is configured to activate all memory cells in the first segment based at least in part on the activation of the signal.

drawings

Example embodiments of the present invention are described with reference to the following drawings.

Fig. 1 illustrates an example memory array supporting selection and operation based on one or more cell plates, according to various embodiments of the invention.

Fig. 2 illustrates an example circuit of memory cells supporting selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 3 illustrates an example hysteresis loop for a ferroelectric memory cell that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 4 illustrates an example of a memory array and other components that support the selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 5 illustrates an example of a memory array and other components that support the selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 6 illustrates an exemplary memory array and component relationships that support selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 7 illustrates a memory array that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

Figure 8 illustrates a system including a memory array that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 9 and 10 are flow diagrams illustrating methods for selecting and operations related to one or more cell plates, according to various embodiments of the invention.

Fig. 11 illustrates an example memory array that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 12 illustrates an example memory array that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

fig. 13 illustrates an example memory array that supports selection and operation related to one or more cell plates, according to various embodiments of the invention.

Fig. 14 is a flow chart illustrating a method for selecting and operation related to one or more cell plates, according to various embodiments of the invention.

Detailed Description

In memory designs, the risk of accidental defects increases when long traces or continuous portions of memory elements are printed. These defects can create operational problems and can render portions of the complete memory array unusable. In some array designs, the cell plates and other elements are close together, and there is an unexpected current risk and other relationships between cell plates, including but not limited to adjacent cell plates. Based on manufacturing or other actions, a cell plate may have a galvanic relationship with an adjacent cell plate, or a cell plate may have other defects with respect to an adjacent cell plate. Such relationships or defects may weaken or inhibit the performance of one or more of the cell plates. Examples of such relationships include short circuits, parasitic fields or signals, and the like.

Some cell plates may include vertically cut cell plates and others, which may be common in a smaller number of digit lines (e.g., 4-16) and a relatively larger number of word lines (e.g., 512-1024). The manner in which the cell plates are formed during fabrication can affect array performance. In some examples, because the distance between respective cell plates is relatively narrow (e.g., such as the distance between wordlines, e.g., the word lines), there may be an unintended current relationship between the cell plates. In some embodiments, a current relationship (e.g., a short circuit) between a group of cell plates can cause a group, segment, or some other memory element to be inoperable. In some cases, the risk of shorts between cells may cause manufacturers to employ expensive wholesale or local redundancy, or both; and the risk of such defects may facilitate other relatively complex solutions, including more robust design parameters (e.g., increasing the spacing between the plates). These alternatives increase cost and reduce memory design functionality and capability.

As described herein, a memory array may be built and operated to mitigate defect risk. By way of example, two or more plates may be selected together to permit operation and filling of one or more sensing components based on one or more current relationships between various cell plates (and other elements), despite the presence of a current relationship (e.g., a short circuit) between the plates that would otherwise render the plates or other elements (e.g., segments) inoperable. In some embodiments, this selection may be based at least in part on selecting two plates simultaneously. In some embodiments, this selection may be based on selecting both plates simultaneously. In some embodiments, this selection may be based on selecting a pair of plates that include a current relationship. In some embodiments, this selection may be based on selecting a pair of plates that do not themselves contain a current relationship, but are spatially or otherwise related to the plates having the current relationship. In some embodiments, for memory access operations associated with a smaller page size, this selection may be based at least in part on selecting all of the memory cells of the larger page size. In some embodiments, this selection may be based at least in part on selecting all memory cells in a section having two plates shorted together.

In some embodiments, cell plates selected in one or more cell plate groups (e.g., two, four, or eight cell plate groups) may be selected based on relative positions to each other or other elements or components. For example, and as described further below, if a cell plate in a group of eight plates is in a zero position (e.g., a first position in the group) and the cell plates in one position (e.g., a second position in the group) have a current relationship (e.g., there is a short circuit between the plates), the cell plates in this or other groups may be selected together or paired using an "even-odd" relationship corresponding to a position-based zero-one relationship. As another example, if a cell plate in three positions (e.g., in a fourth position in a group) has a reverse current relationship (e.g., there is a predetermined current level) with a cell plate in a fourth position (e.g., a fifth position in a group), cell plates in this and/or other groups may be selected together or paired using an "odd-even" relationship corresponding to a position-based three-four relationship.

In some embodiments, by selecting the cell plates in a corresponding pair, corresponding select components (e.g., transistors) are arranged to enable connection of a first set of cell plates (e.g., plates 0, 2, 4, and 6) to a specified sensing component (e.g., sense amplifier) using corresponding digit lines and a second set of cell plates (e.g., plates 1, 3, 5, and 7) to a specified sensing component (e.g., sense amplifier) using corresponding digit lines. In this way, when one or more pairs of adjacent plates are selected, the designated sensing components corresponding to eight plates (for example) may each be correctly populated with data despite one or more current relationships existing between plates, elements, or components, for example. As discussed further below, in some embodiments, this selection of plates and corresponding correctly populated sensing components may be based on seven plates (e.g., plates 0-6, plates 1-seven) from the first group of cell plates and one plate (e.g., plate 7, plate 0) from the second group of cell plates, providing eight correctly populated sensing components. However, other selections may be based on differently sized plate groups; for example, groups with more or less than 8 plates.

In some embodiments, selecting the plate includes selecting one or more memory cells associated with the plate, such as by activating one or more word lines, digit lines, plate lines, sensing components, etc., associated with the memory cells. In some embodiments, the select plate includes all other access lines or sense components that bias the plate with a select voltage without having to activate the memory cells associated with the plate.

Some memory devices may support memory accesses based on different page sizes; for example, the memory device may be capable of performing memory accesses based on page size (e.g., 256B, 128B, 64B, etc.). The page size may be the minimum number of memory cells that can be selected or accessed simultaneously for a memory access operation. In some cases, a memory device may be configured to perform memory accesses based on a particular page size; that is, during a memory access operation, a memory device may be configured to simultaneously select or activate multiple memory cells for the memory access operation based on the page size. For example, a memory device may be configured to simultaneously access different numbers (e.g., pages) of memory cells corresponding to different page sizes 64B, 128B, or 256B.

In some cases, one or more access lines (e.g., word lines, digit lines, and/or plate lines) of a memory array may be shared among multiple memory cells within a page. Configuring a memory device to use a smaller page size (e.g., 128B, 64B) can reduce the amount of power required for memory access by, for example, reducing the amount of power required for access line drivers (e.g., word line drivers, digit line drivers, plate line drivers) and the number of sense amplifiers activated during memory access operations relative to the amount of power required for a larger page size (e.g., 256B). In some cases, accessing the smaller page size includes activating or selecting a subset of the plates in each plate group. For example, if each group has four pads, a memory access of 64B pages can only activate or select the memory cells associated with the first pad in each pad group. Memory access for 128B pages may select only the memory cells associated with two plates (e.g., first and third plates or second and fourth plates) in each plate group. A memory access of 256B pages may select all memory cells associated with all four plates in each plate group.

In some cases, a memory device configured to perform memory accesses based on a smaller page size may instead perform memory accesses based on a larger page size to mitigate undesirable electrical connections. For example, if a plate of a target memory cell that is to be accessed using a smaller page size has an electrical short with a plate of a second memory cell that is not within the same page (which may be, for example, an adjacent plate in a group), the memory device may perform memory accesses based on the larger page size that includes both the target memory cell and the second memory cell in order to avoid potentially corrupting the state of the second memory cell. In some cases, if the memory device determines that there is a short between a first plate included in a first page and a second plate that is not included in the first page but is included in a second, larger page, the memory device may "facilitate" memory accesses from the smaller page size to the larger page size to activate both shorted plates. In some cases, selecting all of the memory cells in the larger page may include selecting all of the memory cells in a section that includes the larger page.

The embodiments of the invention introduced above are further detailed below in the context of memory arrays, as well as in other contexts. Next, specific embodiments of the cell plate are described, including vertically cutting the cell plate and associated operational options, among others. These and other embodiments of the present invention are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow charts related to selection of operations based, at least in part, on one or more groups of cell plates, plates of one or more pages, and/or plates of one or more sectors.

In the present invention, cell plates are used synonymously with plates, unless one or more specific embodiments indicate otherwise. As described herein, a plate may be associated with a single memory cell or a plurality of memory cells.

Fig. 1 illustrates an example memory array 100 supporting one or more cell plates and operations related to one or more cell plates, according to various embodiments of the invention. The memory array 100 may also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 is programmable to store two states labeled logic 0 and logic 1. In some embodiments, memory cell 105 is configured to store more than two logic states. Each state may generate a corresponding voltage across memory cell 105 when memory cell 105 is accessed. Memory cell 105 may include a capacitor that stores a charge representing a programmable state; for example, charged and uncharged capacitors may represent two logic states. DRAM architectures may typically use this design, and the capacitors employed may comprise dielectric materials with linear electrical polarization properties. In contrast, a ferroelectric memory cell may include a capacitor with a ferroelectric as the dielectric material. Different charge levels of the ferroelectric capacitor may represent different logic states. The ferroelectric material has non-linear polarization properties, and details and advantages of ferroelectric memory cell 105 are discussed below.

Operations (e.g., reads and writes) may be performed on memory cells 105 by activating or selecting the appropriate word lines 110 and digit lines 115. Activating or selecting a word line 110 or digit line 115 may include applying a voltage to the respective line. In some embodiments, digit lines 115 may be referred to as bit lines. The word lines 110 or the digit lines 115, or both, may be referred to as access lines. The word lines 110 and digit lines 115 may be made of a conductive material. In some embodiments, the word lines 110 and digit lines 115 are made of metal (e.g., copper, aluminum, gold, tungsten, etc.). Each row of memory cells 105 is connected to a single word line 110, and each column of memory cells 105 is connected to a single digit line 115.

By activating one word line 110 and one digit line 115, a single memory cell 105 can be accessed at its intersection. The intersection of word line 110 and digit line 115 may be referred to as an address of a memory cell. In some embodiments, each digit line 115 may be connected to one or more sensing components 125, in some embodiments, a sensing component 125 may include a sense amplifier corresponding to each digit line 115.

In some embodiments, memory cells 105 may be organized into sectors, which may be a row of multiple groups of memory cells 105. In some cases, the plates in the same location within each group (e.g., the first plate in each group) may be served by a single wordline 110, or multiple pairs of plates within a group may be served by a single wordline, or all plates in a group or sector may be served by a single wordline.

in some embodiments, one or more read or write operations may be based on or derived from one or more on-board cell selections. For example, selection of one or several cell boards may indicate a board pair between two cell boards or a board pairing of each set (e.g., a set of two cell boards) within one or more groups, sections, pages, banks, dies, etc. For example, the selection of one or more cell plates may include a selection of cell plate pairs within each group or a selection of all cell plates in a group or sector.

in some architectures, the logic storage device (e.g., capacitor) of the cell may be electrically isolated from the digit line by the selection device. A word line 110 may be connected to and may control the select device. For example, the select device may be a transistor, and the word line 110 may be connected to the gate of the transistor. Activating a word line 110 creates an electrical connection between the capacitor of a memory cell 105 and its corresponding digit line 115. The digit lines can then be accessed to read or write to memory cells 105.

access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, a column decoder 130 receives a column address from a memory controller 140 and activates the appropriate digit lines 115. Thus, by activating the word line 110 and digit line 115, the memory cell 105 can be accessed. As discussed herein, in various embodiments, the address or location of one or more cells or cell boards may affect the identification, determination, or selection related to the cell board as well as other elements or components. In some embodiments, the address or location of the memory cell may affect the selection, such as a selection based on an absolute address or location or a relative address or location. In some embodiments, the presence of address or location and current relationships for memory cells may affect the selection of plate pairs within or across a group of cell plates. In some embodiments, the presence of address, location, or sector and current relationships of memory cells may affect the selection or activation of a page of memory cells or a sector of memory cells.

After access, the memory cells 105 may be read or sensed by the sensing component 125. When the memory cell 105 is read, the stored state can generate a corresponding signal across the cell's capacitor and thus at the digit line 115. For example, sensing component 125 may compare a signal (e.g., a voltage) of the associated digit line 115 to a reference signal (not shown) in order to determine a stored state of memory cell 105. For example, if digit line 115 has a higher voltage than the reference voltage, sense component 125 can determine that the stored state in memory cell 105 is a logic 1, and vice versa. The sensing component 125 may include various transistors or amplifiers in order to detect and amplify differences in signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output as output 135 through column decoder 130.

Memory cell 105 may be set, written, or initialized to a state by similarly activating the associated word line 110 and digit line 115. As discussed above, activating a word line 110 electrically connects a corresponding row of memory cells 105 to their respective digit lines 115. By controlling the associated digit line 115 when the word line 110 is activated, the memory cell 115 can be written-i.e., a logical value can be stored in the memory cell 105. Column decoder 130 may accept data to be written to memory cells 105, such as input 135. In the case of a ferroelectric capacitor, memory cell 105 is written by applying a voltage across the ferroelectric capacitor. This process is discussed in more detail below.

In some memory architectures, accessing memory cell 105 may degrade or corrupt the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to memory cell 105. In a DRAM, for example, the capacitor may partially or fully discharge during sensing operations, as well as others, destroying the stored logic state. The logic state may be rewritten after the sensing operation. Additionally, activating a single word line 110 can cause one or more memory cells in a row to all discharge; thus, it may be desirable to rewrite one or more memory cells 105 in a row.

Some memory architectures that include DRAM may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage current, resulting in the loss of stored information. The refresh rate of these so-called volatile memory devices can be relatively high (e.g., for DRAMs, tens of refresh operations per second), which can result in significant power consumption. With larger and larger memory arrays, increased power consumption can inhibit the deployment or operation of the memory array (e.g., power supply, heat generation, material limitations, etc.), especially for mobile devices that rely on limited power sources, such as batteries. As discussed below, ferroelectric memory cells may have beneficial properties that may result in improved performance relative to other memory architectures. For example, because ferroelectric memory cells tend to be less susceptible to degradation by stored charge, memory arrays 100 employing ferroelectric memory cells 105 may require less or no refresh operations, and may therefore require less power to operate.

The memory controller 140 may control the operation (read, write, rewrite, refresh, etc.) of the memory cells 105 through various components, such as the row decoder 120, column decoder 130, and sensing component 125. The memory controller 140 may generate row and column address signals in order to activate the desired word line 110 and digit line 115. The memory controller 140 may also generate and control various voltage potentials used during operation of the memory array 100. In general, the amplitude, shape, or duration of the applied voltages discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory array 100. Furthermore, one, more, or all of the memory cells 105 within the memory array 100 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state. For example, a page of memory cells 105 in the memory array 100 may be configured to be accessed simultaneously (simultaneously/concurrrently) based on a page size specified in a memory access command or based on a page size of the memory array. In this case, the memory controller 140 may generate a series of addresses to access the page of memory cells.

In some embodiments, a memory device may include multiple levels or tiers of memory cells 105, which may include multiple stacked memory arrays 100, such as in a cross-point memory architecture. In some cases, each layer may have its own row decoder 120, sensing component 125, column decoder 130, and/or input/output 135. In some cases, a single memory controller 140 may control multiple layers by generating row or column address signals for memory cells in different layers.

In some embodiments, memory controller 140 may be associated with or in electronic communication with a first cell plate and a second cell plate. The first digit line may be in electronic communication with the first cell plate and a first sensing component (e.g., a sense amplifier) via a first select component (e.g., a transistor). The second digit line may also be in electronic communication with a second cell plate and a second sensing component (e.g., a sense amplifier) via a second selection component (e.g., a transistor). Based at least in part on the electronic communication, the controller is operable to initiate or perform one or more operations related to selecting one or more cell plate pairs. In some embodiments, memory controller 140 may be operable to determine a current relationship associated with one or more cell plates. Based at least in part on this determination or identification, memory controller 140 may initiate (e.g., send an instruction or signal to or control another element or component to operate) and operate using the first selection component or the second selection component to select the first cell plate and the second cell plate. In some embodiments, such selection may include electronic communication from the controller to the one or more selection components.

In some embodiments, memory controller 140 is operable to receive memory access commands for memory access operations associated with memory cells of a first page size. The first page size may be specified in a memory access command, for example, or may be a configuration option for the memory controller 140. The memory controller can identify, based at least in part on a memory access command, a first page of memory cells to be activated for the memory access operation. The first page may have a first page size, and the memory controller 140 may identify the first page by generating row and column address signals in order to activate one or more word lines 110 and/or digit lines 115 associated with the first page. In some embodiments, the memory controller 140 may include or be coupled with a logic component (not shown) operable to determine whether there is a short associated with at least one memory cell of a second page of memory cells including the first page and having a second page size greater than the first page size. The short can be, for example, a short between a first plate and a second plate associated with a second page of memory cells. In some embodiments, the logic component determines whether a short exists by receiving a signal associated with the short (e.g., a signal from a fuse based on a short trigger). The memory array 100 is operable to activate a second page of memory cells (e.g., including a first page of memory cells) based at least in part on determining that a short exists. In some embodiments, the memory controller 140 can activate the second page of memory cells by generating row and column address signals associated with the second page in order to activate the word lines 110 and digit lines 115 associated with the second page. In some embodiments, the memory array 100 generates row and column address signals associated with the second page based at least in part on the received signals; for example, by modifying the row and column addresses generated by the memory controller 140 and associated with the first page.

Fig. 2 illustrates an example circuit 200 that supports selecting and operations related to one or more cell plates, according to various embodiments of the invention. Circuit 200 may include ferroelectric memory cell 105-a, word line 110-a, digit line 115-a, and sensing component 125-a, which may be embodiments of memory cell 105, word line 110, digit line 115, and sensing component 125, respectively, as described with reference to FIG. 1 and/or others. The circuit 200 includes a logic storage element, such as a capacitor 205, which may include conductive terminals including a plate 210 and a cell bottom 215. The terminals may be separated by an insulating ferroelectric material. Various states may be stored by charging or discharging capacitor 205, as described in the present disclosure.

The stored state of the capacitor 205 may be read or sensed by operating various elements represented in the circuit 200. Capacitor 205 may be in electronic communication with digit line 115-a. Capacitor 205 may thus be isolated from digit line 115-a when select element 220 is deactivated, and capacitor 205 may be connected to digit line 115-a via select element 220 when select element 220 is activated to select ferroelectric memory cell 105-a. In other words, ferroelectric memory cell 105-a may be selected using selection component 220 in electronic communication with ferroelectric capacitor 205, where ferroelectric memory cell 105-a includes selection component 220 and ferroelectric capacitor 205. In some embodiments, the selection component 220 may be or may include a transistor, and its operation may be controlled by applying a voltage to the transistor gate, where the voltage has a magnitude greater than the threshold magnitude of the transistor. The word line 110-a may activate the select element 220; for example, a voltage applied to word line 110-a is applied to the transistor gate, thereby connecting capacitor 205 with digit line 115-a.

In the example depicted in fig. 2, capacitor 205 is a ferroelectric capacitor. Due to the ferroelectric material between the plates of capacitor 205, and as discussed in more detail below, capacitor 205 may not discharge after being connected to digit line 115-a. Instead, plate 210 may be biased by an external voltage (e.g., via plate line 230), resulting in a change in the stored charge on capacitor 205. The change in the stored charge corresponds to and/or depends on the initial logic state of the capacitor 205. The voltage applied to the capacitor 205 changes the charge of the capacitor 205. The change in charge can be compared to a reference value 225 (e.g., a reference voltage) by the sensing component 125-a in order to determine a stored logic state in the memory cell 105-a.

The particular sensing scheme or process may take many forms. In one example, digit line 115-a may have intrinsic capacitance and may generate a non-zero voltage as capacitor 205 charges or discharges in response to the voltage applied to plate 210. The intrinsic capacitance may depend on physical characteristics, including the size of the digit line 115-a, among others. Digit line 115-a may connect many memory cells 105, so digit line 115-a may have a length that produces a non-negligible capacitance (e.g., on the order of pF or fF). The subsequent voltage of digit line 115-a may depend on the initial logic state of capacitor 205, and sensing component 125-a may compare this voltage to a reference voltage, which may include reference voltages generated by other memory cells 105. For example, a voltage may be applied to the plate 210, and the voltage at the capacitor bottom 215 may change with respect to the stored charge. The voltage at the capacitor bottom 215 may be compared to a reference voltage at the sensing component 125-a, and the comparison to the reference voltage may indicate a change in charge of the capacitor 205 due to the applied voltage, and thus, the logical state stored in the memory cell 105-a. The relationship between the charge and the voltage in the capacitor 205 is described in more detail with reference to fig. 3 and others.

In some cases, plate 210 may be shared among multiple memory cells 105, such that applying a voltage to a single plate 210 or plate line 230 may change the voltage of multiple capacitor bottoms 215. Such an approach may be useful, for example, for reducing the number of plate lines required to simultaneously access multiple memory cells 105.

Other sensing processes may be used. For example, two or more sensing components 125-a may each sense a voltage or other characteristic at two or more digit lines 115-a that each correspond to one or more plates 210. In some embodiments, when two or more boards 210 include adjacent boards 210, these boards 210 may be selected together, and the value sensed by each sensing component 125-a (e.g., sense amplifier) may be accurately read or monitored so that the eight sensing components 125-a corresponding to the eight board group (or portions of the two board groups) are each correctly populated with data. In some embodiments, each of the four sensing components 125-a is populated based on one of the four digit lines 115-a corresponding to the first cell plate 210, and each of the four sense amplifiers is populated based on one of the four digit lines corresponding to the second cell plate 210. By using the selection and shifting techniques and methods of the present disclosure and selecting two cell plates 210 together, eight sensing components (e.g., sense amplifiers) may be accurately populated regardless of any current relationship associated with two cell plates 210 or between two cell plates 210 and/or one or more other defects or adverse conditions associated with two cell plates 210 or other elements or components. Similarly, by using the page-based selection techniques and methods of the present disclosure and selecting memory cells of a larger page size than the page size associated with a memory access command, a memory device can accurately fill the associated sense components and avoid corrupting data stored in memory cells associated with a plate that has a short to another plate.

To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, the select component 220 may be activated by the word line 110-a in order to electrically connect the capacitor 205 to the digit line 115-a. The voltage of cell plate 210 can be controlled by using plate line 230 and the voltage of cell bottom 215 can be controlled by using digit line 115-a to apply a voltage across capacitor 205. To write a logic "0," the cell plate 210 may be made high, i.e., a positive voltage may be applied to plate line 230, and the cell bottom 215 may be made low, e.g., virtual ground, using digit line 115-a. The reverse process is performed to write a logic "1," i.e., cell plate 210 can be made low and cell bottom 215 can be made high. The read and write operations of the capacitor 205 may take into account the non-linear properties associated with ferroelectric devices.

In the example depicted in FIG. 2, a single plate 210 and/or plate line 230 may be associated with a single memory cell 105-a. In other examples, a single plate may be associated with or shared by multiple memory cells, and the voltage applied via plate line 230 may thereby affect multiple memory cells. In some cases, multiple smaller plates 210 may be electrically coupled via a larger shared plate 210 to enable biasing of multiple memory cells via a single plate line 230. As used herein, a plate may refer to any such embodiment or combination of embodiments.

Fig. 3 illustrates an example hysteresis loop 300 for a ferroelectric memory cell that supports selection and operation related to one or more cell plates, according to various embodiments of the invention. Hysteresis loops 300-a and 300-b illustrate the write and read processes, respectively, of an example ferroelectric memory cell. The hysteresis loop 300 depicts the charge Q stored on the ferroelectric capacitor (e.g., capacitor 205 of fig. 2) as a function of the voltage difference V.

Ferroelectric materials are characterized by spontaneous polarization, i.e., they maintain a non-zero electrical polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and Strontium Bismuth Tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electrical polarization within the ferroelectric capacitor creates a net charge at the surface of the ferroelectric material and attracts the opposite charge through the capacitor terminals. Accordingly, charge can be stored at the interface of the ferroelectric material and the capacitor terminal. Because the electrical polarization can be maintained for a longer or even indefinite period of time in the absence of an applied electric field, charge leakage can be greatly reduced compared to, for example, capacitors employed in DRAM arrays. This may reduce the need to perform the refresh operations described above for some architectures.

The hysteresis loop 300 can be understood from the perspective of a single terminal of the capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charges may accumulate at the terminals. Likewise, if the ferroelectric material has a positive polarization, negative charges can accumulate at the terminals. In addition, the voltage in the hysteresis loop 300 represents the voltage difference across the capacitor and is directional. For example, the positive voltage may be applied by applying a positive voltage to the terminal under consideration and maintaining the second terminal at a reference voltage, which may be ground (e.g., about zero volts (0V)). A negative voltage may be applied by maintaining the terminal under consideration at ground and applying a positive voltage to the second terminal, i.e., a positive voltage may be applied to negatively polarize the terminal under consideration. Similarly, two positive voltages, two negative voltages, or a combination of positive and negative voltages can be applied to the appropriate capacitor terminals to generate the voltage difference shown in the hysteresis loop 300.

As depicted in hysteresis loop 300-a, the ferroelectric material can maintain positive or negative polarization with zero voltage difference, resulting in two possible charge states: charge state 305 and charge state 310. According to the example of fig. 3, charge state 305 represents a logic 0 and charge state 310 represents a logic 1. In some embodiments, the logic values of the respective charge states may be reversed to accommodate other schemes for operating the memory cells.

A logic 0 or 1 can be written to the memory cell by controlling the electrical polarization of the ferroelectric material and thus the charge on the capacitor terminals (by applying a voltage). For example, applying a net positive voltage 315 across the capacitor results in charge accumulation until the charge state 305-a is reached. After the positive voltage 315 is removed, the charge state 305-a follows path 320 until it reaches the charge state 305 at zero voltage potential. Similarly, the charge state 310 is written by applying a net negative voltage 325 that results in the charge state 310-a. After the negative voltage 325 is removed, the charge state 310-a changes along path 330 until it reaches the charge state 310 at zero voltage. The charge states 305-a and 310-a may also be referred to as remnant polarization (Pr) values, i.e., the polarization (or charge) that remains after the external bias (e.g., voltage) is removed. The coercive voltage is the voltage at which the charge (or polarization) is zero.

to read or sense the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge changes and the degree of change depends on the initial charge state-i.e., the degree of change in the stored charge of the capacitor depends on whether charge state 305-b or 310-b was initially stored. For example, hysteresis loop 300-b illustrates two possible stored charge states 305-b and 310-b. A net voltage 335 may be applied across the capacitor. Although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may vary along path 340. Likewise, if charge state 310-b is initially stored, then charge state 305-b changes along path 345. The final positions of the charge states 305-c and 310-c depend on several factors including the particular sensing operation and circuitry.

In some embodiments, the charge sensed during a read operation may depend on the intrinsic capacitance of the digit line of the memory cell. For example, if the ferroelectric capacitor of the memory cell is electrically connected to the digit line and a voltage 335 is applied, the voltage of the digit line may be raised due to its intrinsic capacitance. Thus, the voltage measured at the sense component may not equal the voltage 335, but may depend on the voltage of the digit line. Thus, the location of the final charge states 305-c and 310-c on the hysteresis loop 300-b may depend on the capacitance of the digitline and may be determined by load line analysis, i.e., the charge states 305-c and 310-c may be defined with respect to the digitline capacitance. Thus, the voltage of the capacitor (voltage 350 or voltage 355) may be different and may depend on the initial state of the capacitor.

By comparing the digital line voltage to a reference voltage, the initial state of the capacitor can be determined. For example, the reference voltage may be an average of two quantities (voltage 335-voltage 350) and (voltage 335-355). After the comparison, it can be determined whether the sensed digit line voltage is above or below the reference voltage. Then, a value (i.e., a logic 0 or 1) of the ferroelectric cell may be determined based on the comparison.

As discussed above, reading DRAM memory cells can degrade or damage stored logic. However, the ferroelectric memory cell may maintain an initial logic state after a read operation. For example, if charge state 305-b is stored and a read operation is performed, the charge state may return to the initial charge state 305-b after voltage 335 is removed, e.g., by changing in the opposite direction by path 340.

in some cases, applying a voltage to a capacitor plate without selecting the corresponding digit line associated with the plate can result in undesirable device behavior, such as destroying the state of the memory cell associated with the plate. Thus, in some cases, if two pads are shorted such that one of the pads is accidentally biased or activated, it may be desirable to select the digit lines associated with the two pads to avoid unnecessary device behavior even if only one of the pads desires an access operation.

Fig. 4 illustrates an example array 400 that supports selection and operation related to one or more cell plates, according to various embodiments of the invention. Array 400 may include ferroelectric memory cells, one or more word lines (not shown for simplicity), digit lines (e.g., 115-a-115-h, 115-n, 115-x-115-z, etc.), sense components (e.g., 125-a-125-p), plates (e.g., 210-a-210-p), and/or select components (e.g., 220-a-220-h), which may be examples of memory cells 105, word lines 110, digit lines 115, sense components 125, plates 210, and select components 220, respectively, described with reference to fig. 1, 2, or otherwise. The array 400 may include logic storage components, such as capacitors (e.g., the capacitor 205 discussed with reference to fig. 2), which may include conductive terminals, including the plate 210 and the cell bottom 215 (also discussed with reference to fig. 2). The terminals may be separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging capacitor 205.

According to various embodiments of the present disclosure, additional elements are contemplated, although each may not be explicitly labeled or shown. For example, in addition to selecting component pair 455-a (relating to selecting component 220-a and selecting component 220-b) and selecting component pair 455-d (associated with selecting component 220-g and selecting component 220-h), array 400 may include additional components or selecting component pairs or both, among other features. For example, array 400 may include a select component pair 455-b (associated with select component 220-c and select component 220-d) and a select component pair 455-c (associated with select component 220-e and select component 220-f). As another example, the array 400 may include four or another number of digit lines per plate (e.g., plate 210-a), which may be different and may be individually identified, although only some of the digit lines shown (e.g., 115-a-115-h, 115-n, and 115-x-115-z, etc.) are explicitly labeled. Such different digit lines may enable access to multiple memory cells associated with a single plate 210.

Array 400 may also include plate pairs 445-a through 445-h relating to two or more instances of plate 210 (e.g., 210-a and 210-b). In some embodiments, the plate pairs 445-a through 445-h may fall within one or more plate groups 450 shown in FIG. 4 (e.g., plate groups 450-a and 450-b). Array 400 may also include select component pairs 455-a through 455-d associated with two select components 220 (e.g., 220-a and 220-b). The array 400 may also include a group of sense elements (e.g., 460-a-460-d) associated with one or more sense elements 125 (e.g., 125-a-125-d).

in some embodiments, the array 400 includes eight sensing elements 125 per plate group (e.g., plate group 450-a), wherein each sensing element 125 is in electronic communication with one or more digit lines (e.g., digit line 115-a, digit line 115-b) associated with one or more plates (e.g., plate 210-a, plate 210-b). In other embodiments, the array 400 includes more or less than eight sense components 125 per plate group (e.g., plate group 450-a, plate group 450-b).

As previously noted, although the discussion of the sensing process herein describes groups of eight plates, other group sizes are possible, such as groups of two or four plates. In this case, there may be more or fewer word lines, digit lines, plate lines, sense components (e.g., sense amplifiers), etc. associated with the plates in the group relative to the word lines, digit lines, plate lines, sense components depicted in FIG. 4.

In some embodiments, array 400 and associated techniques may be used for vertical cut boards (e.g., board 210-a, board 210-b) which may be used for FeRAM or other RAM designs (e.g., resistive RAM such as CBRAM). In the case of the various plates 210, there is typically a galvanic relationship between two plates or between groups of plates. In some embodiments, this current relationship is based on two adjacent plates being coupled or otherwise having a path between them that supports unexpected communication, inducement, interference, or electron flow. The relationship between such plates may be referred to as a current relationship or a performance-based relationship or the like, as there may be a current flow or effect on the current between the two plates. In some embodiments, this current relationship may include, among other things, an accidental short circuit existing between the two plates. Such an accidental short may be the result of a defect introduced during the manufacturing process or caused by post-manufacturing device damage, for example.

In some embodiments, two or more plates 210 may be selected based on identifying a current relationship between two plates (e.g., plates 210-a and 210-b). This selection may include grouping the two cell plates into plate pairs (e.g., plate pair 445-a) to facilitate reading, writing, or other operations, despite the current relationship between the two plates. If there is a short between two plates in a section of the memory array, such selection may include selecting all of the memory cells within the section (and/or biasing the corresponding plates), or may include selecting memory cells of a page size larger than that specified by the memory access command.

As one example of grouping cell plates, plate 210-a (in the "0" position) and plate 210-b (in the "1" position) may have a current relationship, which may be understood as an "even-odd" current relationship (based on the "0" and "1" positions of plate 210). In some embodiments, this current relationship may be identified or determined based on one of the plates being biased or some other method or technique. For example, by biasing plate 210-a for a read operation and knowing that biasing plate 210-a results in plate 210-b having a current or other value below a threshold, if the current (or other value) of plate 210-b is above the threshold, it can be determined that a current relationship exists between plate 210-a and plate 210-b. In some embodiments, this identification, determination, or selection may be performed during testing, while in other embodiments, this identification, determination, or selection may be performed on an end product having the capability or one or more structural features that enable cell plate selection based on current relationships.

Returning to the example of grouping cell boards, in some embodiments, based on identifying a short circuit or other current relationship, a board pair 445-a may be selected. As an example, such selection of the boards 210-a and 210-b may be accompanied by selection of the selection component pair 455-a of the selection components 220-a and 220-b. By selecting plates 210-a and 210-b and select elements 220-a and 220-b (and corresponding word lines and digit lines (e.g., 115-a-115-h)), each of sense elements 125-a through 125-h can be appropriately filled with data, and groups of sense elements 460-a and 460-b can be completely filled to allow read, write, or other operations.

In some embodiments, one or more other plate pairs (e.g., 445-b, 455-c) may be selected based on identifying a current relationship between plates 210-a and 210-b within the first plate group 450-a, as one example. For example, selection plates 210-g and 210-h may be accompanied by selection component pair 455-d selecting selection components 220-g and 220-h. By selecting plates 210-g and 210-h and select elements 220-g and 220-h (and corresponding word lines and digit lines), each of the sense elements 125 corresponding to digit lines 115 can be appropriately filled with data and the group of sense elements 460 can be completely filled to allow read, write, or other operations.

In some embodiments, a set of select components 220 (as well as other components or elements) may be in electronic communication with or associated with a plurality of board groups 450, boards 210, or other sets of memory components. For example, a set of selection elements 220 (e.g., selection elements 220-a through 220-h) may facilitate or perform selection of one or more boards 210 associated with one or more board groups 450 (e.g., board group 450-a, board group 450-b).

Additionally or alternatively, one or more other select components 220 (as well as other components or elements) may be in electronic communication with or associated with multiple board groups 450, boards 210, and/or other sets of memory components. As an example, one set of select elements 220 (e.g., select elements 220-a through 220-h) may facilitate or perform selection of one or more boards associated with one board group 450 (e.g., board group 450-a), and another set of select elements 220 (e.g., select elements 220-i through 220-p) may facilitate or perform selection of one or more boards 210 associated with one board group 450 (e.g., board group 450-b).

In some embodiments, array 400 may include plate pairs (e.g., 445-a, 445-b, 445-c, 445-d) that fall within the same plate group 450-a, and may be selected based on the current relationship between plates 210 within plate group 450-a.

In some embodiments, the array 400 may include plate pairs 445 (e.g., 445-e, 445-f, 445-g, 445-h) that fall within another plate group 450-b, and may be selected based on the current relationships between plates within the other plate group 450 (e.g., plate group 450-a). This selection may be based on a variety of factors, including the granularity of selection, determination, identification, or array discussed below.

For example, in some embodiments, an element of array 400 (or some related component or element discussed in other figures, such as memory controller 140) may be configured to select plate group 450 shown in FIG. 4 based on the current relationship between plates 210-a and 210-b. Based on determining (via read or write operations or monitoring performance of one or more plates) or identifying current relationships, one or more elements (e.g., fuses) associated with a plurality of groups of plate groups may initiate or correlate to selection of plate pairs (e.g., 445-a to 445-h, etc.). In some embodiments, the number of elements or components that facilitate selection of a plate and/or plate pair may be minimal, and may be based on anticipated or known design parameters, including, for example, one or more known current relationships between plates.

for example, in some embodiments, a die may include one element that facilitates selection of a board (e.g., one fuse) to provide desired selection and pairing capabilities related to various technologies or approaches. In such cases, when a fuse is triggered, then one plate pair, multiple plate pairs, each plate in a page, each plate in a segment, or each plate on a die may be grouped into plate pairs based on one or more identified or determined current relationships (e.g., the location of shorted plates within a group, page, segment, or layer; whether some are even-odd; or whether some are odd-even).

In some embodiments, based on the fuse being triggered, each plate may be selected to pair in odd-even (e.g., barrel shift) relationship to mitigate the effect of one or more (identified, determined, and/or unknown) current relationships. This barrel shift relationship and/or selection allows grouping related to one plate from the first group of plates and one plate from the second group of plates, among other examples. Barrel shifting (or cyclic shifting) as applied herein is discussed in more detail with reference to fig. 5, among others.

In some embodiments, the selection may be finer and may apply only to boards in a current relationship, boards in the same board group, boards in an adjacent board group, and/or boards in some other structure of a larger memory sample (e.g., one or more dies, banks, a subset of one or more banks, half-banks, pages, sectors, half-sectors, and/or a subset of one or more banks, groups, pages, sectors, etc.). For example, in some embodiments, each section may include a set of fuses (and/or some other element and/or component) per section (with hundreds of sections on the memory chip), which allows for more defects and/or current relationships on the memory chip, and which also allows for finer adjustment and/or selection by the section (and/or a bank including multiple sections) based on the designed granularity. In some embodiments, the selected granularity and associated fuse set may be based on actually identifying or determining the amount and/or location (e.g., current relationship) of one or more defects. In other embodiments, the selected granularity and associated fuse sets may be predicted, expected, and/or calculated to identify or determine the amount and/or location (e.g., current relationships) of one or more defects based on past yield, design parameters, desired robustness, some combination, and/or other factors and/or parameters.

In some embodiments, each plate within a larger page size (relative to the page size associated with the memory access command) may be selected, or each plate within a section may be selected, based on the fuse being triggered. In some embodiments, for a multi-layer memory device, a single fuse associated with a section may be shared by multiple layers, such that a fuse triggered based on detecting a short in a first section of a first layer may affect plate selection in a first section of a second layer. In other cases, each layer may have a set of independent fuses, e.g., one fuse per segment per layer.

In some embodiments, selecting one or more plate pairs may be performed before and/or during identifying and/or determining one or more current relationships between one or more plate pairs. For example, by detecting various features, qualities, and/or measurements at one or more various granularities (e.g., a segment), one or more elements or components may report, identify, read, and/or determine performance factors and/or characteristics (e.g., timing, current, voltage, resistance, etc.) associated with and/or specific to one or more granularities. Then, based on the detection associated with the one or more plates, as an example, a second plate and/or other plates and/or plate pairs associated with the one or more plates may be selected. If one or more performance factors (and other detected information) increase, decrease, and/or are modified, a current relationship (among other things) may exist between one or more boards and a second board. Additional pairings, selections, and/or shifts may then be derived from the current relationships associated with the one or more plates and the second plate, among others.

Fig. 5 illustrates an example array 500 that supports operations related to selecting one or more cell plates and one or more cell plates, according to various embodiments of the invention. Array 500 may include ferroelectric memory cells, one or more word lines, digit lines (e.g., 115-a-115-h, 115-n, 115-x, 115-z, etc.), sense components 125 (e.g., 125-a-125-p), plates 210 (e.g., 210-a-210-p), and select components 220 (e.g., 220-a-220-h), which may be examples of memory cells 105, word lines 110, digit lines 115, sense components 125, plates 210, and select components 220, respectively, described with reference to fig. 1, 2, 4, or otherwise. The array 500 may include logic storage components, such as capacitors (e.g., the capacitor 205 discussed with reference to fig. 2), which may include conductive terminals, including the plate 210 and the cell bottom 215 (also discussed with reference to fig. 2). The terminals may be separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging the capacitor 205. Array 500 may include features similar to, the same as, or different from the features discussed with respect to array 400 or with figures 4 and 6 and other features, methods, techniques, and structures discussed otherwise or in relation to figures 4 and 6 and others.

According to various embodiments of the present disclosure, additional elements are contemplated, although each may not be explicitly labeled or shown. For example, array 500 may include additional components in addition to selection component pair 455-a (related to selection component 220-a), selection component pair 455-b (related to selection component 220-b and selection component 220-c), and selection component pair 455-e (related to selection component 220-h). For example, array 500 may include select component pair 455-c (relating to select component 220-d and select component 220-e), select component pair 455-d (relating to select component 220-f and select component 220-g), or both. As another example, array 500 may include four or another number of digit lines per plate 210 (e.g., plate 210-a), which may be different and may be individually identified, although only some of the digit lines shown (e.g., 115-a-115-h, 115-n, and 115-x-115-z, etc.) are explicitly labeled.

Array 500 may also include plate pairs 445-a through 445-i relating to two or more of plates 210 (e.g., 210-b and 210-c). In some embodiments, the plate pairs 445-a through 445-i may fall within one or more plate groups 450 shown in FIG. 5 (e.g., plate groups 450-a and 450-b). Array 500 may also include a pair of selection components 455 (e.g., 455-a through 455-e) associated with two selection components 220 (e.g., 220-b and 220-c). The array 500 may also include groups of sense elements 460-a-460-d that may be associated with a plurality of sense elements 125 (e.g., 125-a-125-d).

In some embodiments, two or more plates 210 may be selected based on identifying a current relationship between two plates (e.g., plates 210-b and 210-c). This selection may include grouping the two cell plates into plate pairs (e.g., plate pair 445-b) to facilitate reading, writing, or other operations, despite the current relationship between the two plates.

As one example, plates 210-b (in the "1" position) and plates 210-c (in the "2" position) may have a current relationship, which may be understood as an "odd-even" current relationship (based on the "1" and "2" positions of plates 210). In some embodiments, this current relationship may be identified or determined based on one of the plates being biased or some other method or technique. For example, by biasing plate 210-b for a read operation and knowing that biasing plate 210-b results in plate 210-c having a current or other value below a threshold, if the current (or other value) of plate 210-c is above the threshold, it can be determined that a current relationship exists between plate 210-b and plate 210-c. In some embodiments, this identification, determination, or selection may be performed during testing, while in other embodiments, this identification, determination, or selection may be performed on an end product having the capability or one or more structural features that enable cell plate selection based on current relationships.

in some embodiments, based on identifying this or other current relationships, plate pair 445-b may be selected. As one example, such selection of boards 210-b and 210-c may be accompanied by selection of selection component pair 455-b of selection components 220-b and 220-c. By selecting plates 210-b and 210-c and select elements 220-b and 220-c (and corresponding word lines and digit lines), each of the corresponding sense elements 125 (e.g., 125-a through 125-h) can be appropriately filled with data, and groups of sense elements 460-a and 460-b can be completely filled to allow for read, write, and other operations.

In some embodiments, one or more other plate pairs 445 (e.g., 445-a, 445-d) may be selected based on identifying a current relationship between plates 210-b and 210-c (as an example) within the first plate group 450-a. This selection of plates 210-f and 210-g may be accompanied by selection of selection element pair 455-d that selects selection elements 220-f and 220-g. By selecting plates 210-f and 210-g and select elements 220-f and 220-g (and corresponding word lines and digit lines), each of the sense elements 125 corresponding to a digit line can be appropriately filled with data, and groups of sense elements can be completely filled to allow read, write, and other operations.

In some embodiments, one or more plates or one or more plate pairs may be selected based on a relationship associated with the one or more plates or the one or more plate pairs or both. In some embodiments, such a relationship may include a spatial relationship, such as one or more absolute positions, one or more relative positions of one, two, and/or more plates and/or pairs, plate addresses (including absolute or relative plate addresses or both) of one or more plates or related units, some combination, or otherwise. In some embodiments, such a relationship may include a location, such as a location directly (directly/immediately) proximate or near or adjacent to one, two or more boards or pairs, among other things. In some embodiments, a plate within a plate group (e.g., plate group 450-a) may be proximate and/or adjacent to other plates within the plate group. In other embodiments, the plates within different plate groups (e.g., plates 210-h and plates 210-j of plate groups 450-a and 450-b, respectively) may be positioned adjacent to each other.

In some embodiments, one or more other plate pairs (e.g., 445-a, 455-e) may be selected based on identifying a current relationship between plates 210-b and 210-c (as an example) within the first plate group 450-a. In some embodiments, a first plate (e.g., plate 210-h) may be selected to be associated with a second plate (e.g., plate 210-i), which may be associated with a second plate group (e.g., plate group 450-b). In some embodiments, this selection may include barrel shifting, barrel selection, wrap around shifting or wrap around selection, or some combination, among other variations. This selection of plates 210-h and 210-j may be accompanied by selecting a selection element pair 455-e of selection element 220-h and one or more other selection elements 220. In some embodiments, the one or more selection elements 220 may be included in another group of associated selection elements 220 (e.g., a first selection element of another group of selection elements), or the one or more selection elements 220 may include a selection element 220-a from a first selection element pair 455 (e.g., a group) which may then be paired with selection element 220-h, or some combination.

Similarly, in some embodiments, a first plate (e.g., plate 210-p) and a second plate (e.g., plate 210-a, another plate (not shown)) may be selected, which may be related to a first plate group (e.g., 450-a) and a third plate group (e.g., 450-c).

By selecting plates in odd-even plate pairs (e.g., 210-f and 210-g) and select elements 220-f and 220-g (and corresponding word lines and digit lines), each of the sense elements 125 corresponding to digit lines 115 can be appropriately filled with data, and one or more groups 460 of sense elements can be completely filled to allow read, write, or other operations.

For example, as shown in FIG. 4, selection components 220 (e.g., 220-a-220-h), which may each be instances of transistors that are capable of being selected in some embodiments, are arranged to connect respective digit lines (e.g., 115-a-115-h) from respective plates (e.g., 210-a-210-h) to sensing components (e.g., sensing components 125-a-125-h) to facilitate selection of one or more plate pairs. Digit lines from some of the pads (e.g., pads 210-a, 210-c, 210-e, 210-g) may be connected to or in electronic communication with a first group of sense elements (e.g., sense element group 460-a). Digit lines from some of the pads (e.g., pads 210-b, 210-d, 210-f, 210-h) may be connected to or in electronic communication with a second group of sense elements (e.g., sense element group 460-b). In some embodiments, when one or more plate pairs (e.g., 445-a, 445-b, 445-c, 445-d) are selected (regardless of the order of each pair (e.g., odd-even, even-odd, some other order)), the first group of sense elements and the second group of sense elements will be accurately filled with data. The same principles, acts, and operations apply equally to other embodiments, methods, and techniques described in this disclosure.

According to various embodiments of the present invention, a set of select components (as well as other components or elements) may be in electronic communication with or associated with a plurality of board groups, boards, or other sets of memory components. For example, a set of selection elements (e.g., selection elements 220-a through 220-h) may facilitate or perform selection of one or more boards associated with one or more board groups (e.g., board group 450-a, board group 450-b), or some combination of both.

Further, alternatively, one or more other set selection components 220 (as well as other components or elements) may be in electronic communication with or related to a plurality of board groups, boards, or other sets of memory components. As an example, one set of select elements 220 (e.g., select elements 220-a through 220-h) may facilitate or perform selection of one or more boards associated with one board group (e.g., board group 450-a), and another set of select elements 220 (e.g., select elements 220-h through 220-p) may facilitate or perform selection of one or more boards associated with one or more other board groups (e.g., board group 450-b).

In some embodiments, array 500 may include plate pairs (e.g., 445-b, 445-c, 445-d) that fall within the same plate group 450-a, and may be selected based on the current relationships between plates within plate group 450-a and/or one or more other plate groups.

In some embodiments, array 500 may include plate pairs (e.g., 445-a, 445-e, 445-f, 445-g, 445-h) that fall within one or more other plate groups (e.g., 450-b, 450-c), and may be selected based on the current relationships between plates within the same plate group or one or more other plate groups (e.g., plate groups 450-a and/or 450-b), as well as others. Such selection may be based on one or more factors, including the granularity of selection and/or related components, the design of the array, the presence of one or more current relationships, the design of one or more plate groups, one or more elements or components of the array and/or memory cells and/or electronic memory devices, performance relationships, current relationships, electronic communication relationships, status determinations and/or identifications, some combinations, and/or other factors.

For example, in some embodiments, elements of array 500 (and/or some related components and/or elements discussed in other figures, such as memory controller 140) may be configured to select the group of plates shown in FIG. 4 and/or FIG. 5 based on the current relationship between plates 210-b and 210-c. Based at least in part on determining (via read or write operations or monitoring performance of one or more plates, among other methods and techniques) and/or identifying current relationships, one or more elements (e.g., fuses) associated with one or more groups of plate groups may initiate selection of plate pairs (e.g., 445-a to 445-i, etc.).

In some embodiments, the selection may be finer and may apply only to plates in a current relationship, in the same plate group, in an adjacent plate group, and/or in some other subsection of a larger memory sample.

In some embodiments, methods and techniques for operating ferroelectric memory cells according to various embodiments of the present disclosure are described. The methods and techniques may include: identifying a first cell plate included in the first cell plate group; identifying a second cell plate adjacent to the first cell plate and included in the first cell plate group or the second cell plate group; and selecting the first cell plate and the second cell plate based at least in part on a current relationship between the first cell plate and the second cell plate, among other operations. The methods and techniques may include: receiving a memory access command for a memory access operation associated with a first page size of memory cells; identifying, based at least in part on the memory access command, a first page of memory cells to be activated for the memory access operation, the first page having the first page size; determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size; and activating the second page of memory cells based at least in part on determining that there is a short circuit associated with the at least one memory cell.

In some embodiments, the current relationship may include, inter alia, a short circuit between the first cell plate and the second cell plate. In some embodiments, the current relationship may include, among other things, a first current level of the first cell plate and/or a second current level of the second cell plate. In some embodiments, the first current level results from applying a voltage to the first cell plate and the second current level results from applying a voltage to the second cell plate. In some embodiments, the short associated with the memory cell includes a short between the first plate and the second plate associated with the memory cell.

In some embodiments, one or more cell plates may be contained in one or more groups and may be organized and/or ordered in one or more locations within one or more groups. In some embodiments, the first cell plate and/or the second cell plate may be included in the first cell plate group. In some embodiments, the first cell plate may be included in a first cell plate group, and/or the second cell plate may be included in a second cell plate group. In some embodiments, the first cell plate is in the last position in the first cell plate group, and/or the second cell plate may be in the first position in the second cell plate group.

In some embodiments, a sector of a memory array may contain a row of groups, with each group containing multiple plates. In some embodiments, a page of memory cells may include memory cells associated with a subset of the plates within each group in a sector, or may include memory cells associated with all of the plates within each group in a sector.

In some embodiments, the memory cells associated with one or more plates in each group may be accessed based on a page size associated with a memory access command. For example, accesses based on smaller page sizes may include: biasing, selecting, or activating all memory cells associated with the first plate in each group in a section, such that executing a memory access command based on a smaller page size may include: only the memory cells associated with the first plate in each group are biased, selected, or activated. In some cases, the larger page size may include memory cells associated with two or more plates in each group, such as memory cells associated with the first and third plates in each group, or memory cells associated with alternate plates in each group, or memory cells associated with all plates in each group. In this case, executing the memory access command based on the larger page size may include: all memory cells associated with multiple plates within each group are selected, biased, or activated. In some cases, a larger page of memory cells may be a full section or multiple full sections of the memory array, and selecting or activating a larger page of memory cells may include: all memory cells associated with all plates in the sector are selected or activated.

one executable operation associated with one or more cell plates may include a read operation, including a value-based or logic-based read operation. In some embodiments, methods and techniques for operating memory cells according to various embodiments of the present disclosure may include: information is read from the first cell plate and the second cell plate based at least in part on reading information from a first sense amplifier in electronic communication with the first cell plate and a second sense amplifier in electronic communication with the second cell plate. In some embodiments, methods and techniques may include reading information from a first cell plate and a second cell plate in combination based at least in part on the selection.

in some embodiments, methods and techniques for operating memory cells according to various embodiments of the present disclosure may include: identifying a third cell plate included in the third cell plate group; identifying a fourth cell plate included in the second cell plate group or the third cell plate group; identifying a third cell plate adjacent to the fourth cell plate; and selecting the third cell plate and the fourth cell plate as a pair based at least in part on a current relationship between the first cell plate and the second cell plate.

In some embodiments, one or more cell plates may be contained in one or more groups or may be organized and ordered in one or more locations within one or more groups, in accordance with various embodiments of the present disclosure. In some embodiments, a third cell plate may be included in the third cell plate group, and/or a fourth cell plate may be included in the second cell plate group. In some embodiments, the third cell plate may be in a first position in the third cell plate group and/or the fourth cell plate may be in a last position in the second cell plate group.

Fig. 6 illustrates example arrays 605-625 each supporting the selection and operation associated with one or more cell plates, according to various embodiments of the invention. Each of the arrays 605-625 may include ferroelectric memory cells, one or more word lines, digit lines, one or more sense elements, one or more plates (e.g., plates 210-a-210-p), select elements, or groups of plates (e.g., plate group 450-a, plate group 450-b), which may be memory cells 105, word lines 110, digit lines 115, sense elements 125, plates 210, and/or select elements 220, respectively, as described with reference to fig. 1, 2, 4, 5, or otherwise. Each of the arrays 605-625 may include features similar, identical, or different from the features discussed with respect to the arrays 400, 500 or with fig. 1-5 and other discussion or related to fig. 1-5 and others.

In some embodiments, additional elements are contemplated, although each may not be explicitly labeled or shown, in accordance with various embodiments of the present disclosure. For example, in addition to the group of plates (e.g., 450-a), plates (e.g., 210-a), plate pairs (e.g., 665-a), and current performance relationships (e.g., 665-a) shown in fig. 6, other elements or components disclosed, described, or contemplated based on fig. 1-5, among others, are contemplated. For example, although FIG. 6 does not explicitly show the digit lines, word lines, select components, sense components, or other elements described or shown in FIGS. 1-5 (among others), the present disclosure (including the embodiments shown and described with respect to FIG. 6) contemplates each of the digit lines, word lines, select components, sense components, or other elements, alone or in combination.

Example arrays 605-625 illustrate various current relationships that may exist between the cell plates of the array, including short circuits.

as shown in example array 605, plates 210-a through 210-h are organized as part of plate group 450-a, and plates 210-i through 210-p are organized as part of plate group 450-b. In some embodiments, the current relationship 665-a is detected based at least in part on one or more identifications or determinations. Based at least in part on this detection of current relationship 665-a, one or more plate pairs (e.g., plate pair 645-a) are selected by one or more system elements or components. In some embodiments, first plate pair 645-a is identified as corresponding to the even-odd relationship of plates 210-a and 210-b associated with current relationship 665-a. As discussed in this disclosure, one or more elements may perform the selection of plates 210-a and 210-b based at least in part on the detected current relationship 665-a directly related to plates 210-a and 210-b.

In some embodiments, plate pair 645-a may be individual and other plate pairs in the same plate group (e.g., plate group 450-a) or in other plate groups (e.g., plate group 450-b) may not be selected based at least in part on current relationship 665-a. This single pair of granularities in identifying, determining, or selecting may be applicable in certain designs or other embodiments. For example, such a single pair selection reduces power consumption associated with alternative embodiments that may require reading, writing, or performing other operations based on multiple, numerous, or every two boards in a section, column, die, bank, and/or other structure.

In some embodiments, the plate pair 645-a versus the first plate group (e.g., 450-a) may be individual, and may be related to plate pair 645-b or may otherwise correspond to plate pair 645-b, as shown in example array 605. In this example, one or more elements or components may select one plate pair in a first group (e.g., plate group 450-a) and one plate pair in one or more other plate groups (e.g., plate group 450-b). In some embodiments, these plate pairs (e.g., 645-a and 645-b) may be selected based on the current relationship 665-a and other parameters, factors, or conditions associated with the array 605 or other system elements or components. In some embodiments, the selection of plate pairs 645-a and 645-b may be based on determining a current relationship 665-a that affects a first plate in the first group (e.g., plate 210-a of plate group 450-a) and a second plate in the first group (e.g., plate 210-b of plate group 450-a). In some embodiments, selection of plate pair 645-b may be performed before, during, or after selection of plate pair 645-a is performed based on identifying current relationship 665-a. Thus, indirect selection of plates 210-i and 210-j may be based on the current relationships between other plates (e.g., plates 210-a and 210-b in array 605), which may be based on the current relationships (e.g., 665-a) between particular plates having current relationships (e.g., plates 210-a and 210-b in array 605) being performed independently of, in addition to, in place of, or otherwise related to direct selection.

As shown in example array 610, plates 210-a through 210-h are organized as part of plate cluster 450-a, and plates 210-i through 210-p are organized as part of plate cluster 450-b. In some embodiments, plates 210-a and 210-j may be included in a first page having a smaller page size (e.g., 64B), and plates 210-a, 210-j, 210-B, and 210-j may be included in a second page having a larger page size (e.g., 128B). In some embodiments, groups 450-a and 450-b and corresponding plates 210-a through 210-p may be part of a section containing multiple other groups (not shown).

In some embodiments, based on one or more identifications or determinations, the current relationship 665-b can be detected (e.g., identified, determined, etc.). Based at least in part on this detection of current relationship 665-b, one or more plate pairs (e.g., plate pair 645-c) are selected by one or more system elements or components. In some embodiments, first plate pair 645-c is identified as corresponding to the even-odd relationship of plates 210-a and 210-b associated with current relationship 665-b. As discussed in this disclosure, one or more elements may perform the selection of plates 210-c and 210-d based on the detected current relationship 665-b indirectly associated with plates 210-c and 210-d. In addition, plate pair 645-d may be selected based on detection of current relationship 665-b, selection of plate pair 645-c, some combination, and/or other information. In some embodiments, plate pair 645-d may be selected based on the relative position of each plate (e.g., plate 210-k in the "2" position and plate 210-1 in the "3") and this may or may not be correlated with the relative position of one or more other plates (e.g., plate 210-c in the "2" position and plate 210-d in the "3").

in some embodiments, as shown in example array 610, plate pair 645-d may correspond to the relative position of plate pair 645-c (which includes plate 210-c and plate 210-d), shown in the "2" and "3" positions of plate group 450-a. In some embodiments, as shown in example array 610, plate pair 645-d may correspond to the relative position of current relationship 665-b (which is based on plates 210-a and 210-b) and the ordering of current relationship 665-b, shown in the "0" and "1" positions of plate group 450-a. For example, the ordering (e.g., even-odd) of current relationships 665-b may affect, at least in part, or otherwise affect the selection of plate pair 645-d (relative to plates 210-k and 210-1).

In some embodiments, as shown in example array 615, there may be multiple current relationships between plates in one or more plate groups. For example, one or more identifications or determinations may be performed to determine at least one of current relationships 665-c and 665-d that may each affect two or more plates (e.g., plates 210-a, 210-b, 210-e, 210-f) as well as other elements or components.

In some embodiments, based on identifying or determining current relationship 665-c or current relationship 665-d, one or more selections corresponding to plate pairs 645-e or 645-f, among others, may be made. One or more plate pairs may be selected using a controller, one or more fuses, one or more other elements or components, some combinations, and/or other structures by comparing the spatial relationships of one or more current relationships, plate order, plate relative position (even-odd, odd-even), and/or other factors.

Alternatively or additionally, a particular plate pair (e.g., 645-e, 645-f, 645-g) is selected based on identifying or determining (among other operations) one or more current relationships in one or more plate groups. In some embodiments, this selection may be based on identifying or determining some, most, or all of the current relationships present in one, multiple, or each board group within a particular die, bank, section, group, and/or other subset. For example, one or more plate pairs (e.g., 645-e, 645-f, 645-g) may be selected by identifying, comparing, or otherwise determining the current relationships 665-c, 665-d, 665-e, 665-f, and 665-g. In some embodiments, this detection may be based on a comparison or determination of whether each current relationship is an even-odd current relationship or an odd-even current relationship.

In some embodiments, such detection may be based on a comparison or determining whether one or more current relationships are determined to be similar to one or more current relationships without determining whether one or more current relationships are odd-even, even-odd, affect the first and second plates, affect the second and third plates, and/or some combination. For example, such detection may be based on a comparison and/or a determination of whether current relationship 665-c is similar to current relationship 665-d and/or current relationship 665-e without determining whether each of the current relationships is even, even-odd, affects the first and second plates, affects the second and third plates, affects other plates, and/or some combination.

In other embodiments, this detection may be made independent of or dependent on comparing or determining whether each current relationship is an even-odd current relationship or an odd-even current relationship.

In some embodiments, as shown in example array 620, there are multiple current relationships among the plates in the first plate group, the second plate group, and/or between the first plate and the second plate group (among other variations). For example, one or more identifications or determinations may be performed to determine at least one of current relationships 665-h, 665-i, and 665-j that each affect two or more plates (e.g., plates 210-b and 210-c, 210-h and 210-i, 210-1, and 210-m), as well as other elements or components.

In some embodiments, one or more selections corresponding to plate pairs 645-h or 645-i, as well as others or some combination, may be made based on identifying or determining one or more of current relationships 665-h, 665-i, and 665-j. One or more plate pairs may be selected by comparing the spatial relationship of one or more current relationships, plate order, plate relative position (even-odd, odd-even), and/or other factors. In some embodiments, the selection may be based on one or more of the current relationships between different plate groups and/or subgroups. For example, as shown in example array 620, there is one or more of a current relationship (e.g., current relationship 665-i) between a first plate group (e.g., 450-a) and a second plate group (e.g., 450-b) or between a second plate group (e.g., 450-b) and an additional plate group (e.g., a third plate group).

One or more plate pairs or groups may be selected based at least in part on one or more of the current relationships between two or more plate groups. In some embodiments, based on determining a first current relationship (e.g., current relationship 665-i), one or more plate pairs may be selected. The selected one or more plate pairs may include plate pairs in similar absolute and/or relative positions (e.g., position "7" and position "0"), may have similar order (e.g., odd-even as current relationship 665-i), and/or other factors.

In some embodiments, selecting one or more plate pairs may affect one plate group based on determining two or more current relationships (e.g., current relationship 665-i and current relationship 665-j). By determining that two or more current relationships affect one plate group (e.g., plate group 450-b), one or more selections may be made regarding the affected plate group (e.g., plate group 450-b) and/or one or more other plate groups, including, but not limited to, two or more other plate groups that are adjacent or neighboring plate group 450-b and two or more other plate groups that are not adjacent or neighboring plate group 450-b but may still be contained within the same die library or sector.

In some embodiments, as shown in example array 625, there are multiple current relationships between plates in the first plate group, the second plate group, or between the first plate and the second plate group (and other variations). For example, one or more identifications or determinations may be performed to determine at least one of current relationships 665-k, 665-1, and/or 665-m that each affect two or more plates (e.g., plates 210-b and 210-c, 210-h and 210-i, and 210-m) as well as other elements or components.

In some embodiments, one or more selections corresponding to plate pairs 645-j, 645-k, and/or 645-1, among others, may be made based on identifying or determining one or more of current relationships 665-k, 665-1, and/or 665-m. One or more plate pairs may be selected by comparing the spatial relationship of one or more current relationships, plate order, plate relative position (even-odd, odd-even), and/or other factors. In some embodiments, the selection may be based on one or more of the current relationships between different plate groups. For example, as shown in example array 625, one or more of a current relationship (e.g., current relationship 665-1) may exist between a first plate group (e.g., 450-a) and a second plate group (e.g., 450-b) and/or between the second plate group (e.g., 450-b) and an additional plate group (e.g., a third plate group).

One or more plate pairs or groups may be selected based at least in part on one or more of the current relationships between two or more plate groups. In some embodiments, one or more plate pairs may be selected based on determining a first current relationship (e.g., current relationship 665-1 or 665-k). The selected one or more plate pairs may include plate pairs in similar absolute or relative positions (e.g., position "7" and position "0" depicted by plate pair 645-k), may have a similar order (e.g., odd-even as current relationship 665-i or 665-1), and/or other factors.

In some embodiments, selecting one or more plate pairs may be based on determining that two or more current relationships have a similar order (e.g., odd-even, even-odd) and/or the relative position of at least one of the plates in a plate pair (e.g., plate pair 645-k). For example, an initial determination may be made as to the order of some, most, and/or all detected current relationships within a specified set (e.g., segment, die, bank, group, subset). By determining that at least one of the detected current relationships (e.g., current relationships 665-i and 665-j) affects a particular plate and/or a particular plate pair (e.g., affects plates in position "7", such as 210-h, etc., based on odd-even order), a plate pair including at least one plate from the first plate group and at least one plate from the second plate group (e.g., first plate and plate 210-a shown by plate pair 645-j, plates 210-h and 210-i shown by plate pair 645-k, etc.) may be selected.

In some embodiments, the selection may be based on determining whether each current relationship (e.g., 665-k, 665-1, 665-m) includes a particular order (or does not include a particular order), such as even-odd or odd-even (or more complex orders involving additional plates), and determining whether all plate relationships are similar based on the relative position of one or more plates that are directly and/or indirectly affected by at least one current relationship (e.g., position "0" or "4" or "7").

In some embodiments, the selection may be performed based on determining whether a subset of the current relationships (e.g., 665-1) includes a particular order (or does not include a particular order), such as even-odd or odd-even (or a more complex order involving additional plates), and the presence of one or more other current relationships, the order of the plates of one or more other current relationships, the absolute or relative position of one or more other current relationships, some combination, or other factors. For example, based on determining or identifying current relationship 665-1, a selection of plates 210-h and/or 210-i may be made to form plate pair 645-k. Alternatively or additionally, based on the identification or determination regarding the plate pairs 645-k, all other similarly positioned pairs within a section and/or other granularity (e.g., bin, die) may be selected. For example, based on an identification or determination regarding plate pair 645-k, other plate pairs in the same location (e.g., locations "7" and "0" in this example) may be paired, resulting in selection of plate pair 645-j or plate pair 645-1, among others.

Alternatively or additionally, based on the identification or determination regarding paddle pairs 645-k, all other paddles within a section and/or other granularity (e.g., library, die) may be selected in a similar manner. For example, based on the identification or determination regarding plate pair 645-k, all other plates may be paired regardless of their location and/or other characteristics, resulting in selection of plates 210-b and 210-c, 210-d and 210-e, 210-f and 210-g, 210-j and 210-k, 210-1 and 210-m, 210-n and 210-o, a first plate and plate 210-a in plate pair 645-j, a second plate and plate 210-p in plate pair 645-1, and/or others.

In some embodiments, electronic memory devices according to various embodiments of the present invention are described. The electronic memory apparatus may include a first cell plate group, a second cell plate group, a first cell plate included in the first cell plate group, or a second cell plate adjacent to the first cell plate and included in the first cell plate group or the second cell plate group. In some embodiments, the first cell plate and the second cell plate are in electronic communication.

In some embodiments, the electronic communication may include, inter alia, a short circuit between the first cell plate and the second cell plate. In some embodiments, the electronic communication is based on a proximity of the first cell plate to the second cell plate. As described in accordance with various embodiments of the present invention, the proximity may include one or more absolute positions (locations/positions), relative positions, positions adjacent to another cell plate in the same group, positions adjacent to another cell plate in at least one other group, some combination, or other variation.

In some embodiments, an electronic memory apparatus according to various embodiments of the invention can include a first digit line in electronic communication with a first cell plate and a first sense amplifier via a first transistor. In some embodiments, an electronic memory apparatus according to various embodiments of the invention can include a second digit line in electronic communication with a second cell plate and a second sense amplifier via a second transistor. In some embodiments, the first transistor and/or the second transistor may be an embodiment of a sensing component according to various embodiments of the present disclosure.

In some embodiments, one or more cell plates may be included in one or more groups, and may be organized and/or ordered in one or more locations within one or more groups, in accordance with various embodiments of the present invention.

In some embodiments, the first cell plate and the second cell plate are each included in a first cell plate group. In some embodiments, the first cell plate is included in a first cell plate group and the second cell plate is included in a second cell plate group. In some embodiments, the first cell plate is included in one cell plate group, and the second cell plate is included in another cell plate group different from the cell plate group of the first cell plate. In some embodiments, the first cell plate is in a first position in the first cell plate group and the second cell plate is in a last position in the second cell plate group. In some embodiments, the first cell plate is in a last position in the first cell plate group and the second cell plate is in a first position in the second cell plate group. In some embodiments, the first cell plate is not in a first position in the first group of cell plates and/or the second cell plate is not in a last position in the second group of cell plates.

In some embodiments, additional methods and techniques involving redundant memory elements or components may be used in addition to employing the methods and techniques described in this disclosure that support the selection of cell plates and plate pairs and operations related to cell plates and plate pairs. For example, certain design parameters may need to have a redundancy level that may require full redundant segments (and/or more localized but more expensive redundancy on a group basis, etc.). Based on the use of board selection and the use of one or more board pairs within a board group, sector, bank, die, or other organization, the need for redundant sectors may be greatly reduced (and in some embodiments eliminated), reducing the cost of redundant memory sectors and avoiding expensive localized redundancy control (e.g., board groups, etc.). The use of the plate selection techniques and methods associated herein enable existing memory elements to be more robust and avoid large-scale discarding of groups, sectors, banks, and/or dies based on secondary current performance relationships, which may include shorting between vertically cut plates, among other things.

For example, where multiple redundant sections may be needed for conventional designs based on one or more of yield constraints, defect density, and/or technology dependent decisions, the use of plate pairs and selection techniques related to one or more plate pairs in a plate group, a page, a section, a die, a bank or column, and/or another granularity may actually make the elements more efficient and robust by virtue of using plate selection to reduce the required redundancy.

In some embodiments, associated methods and techniques may include: identifying redundancy or robustness factors or requirements, determining how plate selection and/or displacement of one or more plate pairs will affect the redundancy or robustness factors or requirements, and/or reducing the redundancy or robustness factors or requirements based on the determination. These steps (and others) may be performed before, as part of, or after the plate selection step or other steps, according to various embodiments of the present invention.

This hybrid solution, including board selection and a reduced amount of redundant memory, may enable memory devices and products to provide additional features and capabilities without the need for a fully redundant memory solution that is fully duplicative and prohibitively expensive. In some designs, the original number of redundancies may be reduced from three redundant segments to one redundant segment using plate selection techniques and methods, as just one example. In many embodiments, however, the techniques and methods described throughout this disclosure support selecting, shifting cells, and cell-related operations without the need for original redundancy or hybrid techniques.

The example arrays 605-625, each supporting the selection of cell plates and operations related to the cell plates, are used merely as embodiments according to various embodiments of the invention. Each of these embodiments may be modified, adjusted, duplicated, include additional steps, omit some steps, or otherwise adjusted based at least in part on the various embodiments and circumstances described.

FIG. 7 shows a block diagram 700 of a memory array 100-a that supports selection and operation related to one or more cell plates, according to various embodiments of the invention. Memory array 100-a may be referred to as an electronic memory device and may include a memory controller 140-a and memory units 105-b, which may be embodiments of memory controller 140 and memory units 105 described with reference to fig. 1 and 2, among others. The memory controller 140-a may include a bias component 710 and a timing component 715, and may operate the memory array 100-a as described in fig. 1-3. Memory controller 140-a may be in electronic communication with word line 110-b, digit line 115-aa, sensing element 125-q, and/or plate 210-q, which may be embodiments of word line 110, digit line 115, sensing element 125, and plate 210 (among other embodiments) described with reference to fig. 1-6 and 11-14, as well as others. The memory array 100-a may also include a reference component 720 or a latch 725. The components of the memory array 100-a may be in electronic communication with each other and may perform the functions described with reference to fig. 1-6 and 11-14, as well as others. In some embodiments, reference component 720, sense component 125-q, and latch 725 may be components of memory controller 140-a.

Memory controller 140-a may be configured to activate word line 110-b, plate 210-q, or digit line 115-q by applying voltages to various nodes. For example, bias component 710 may be configured to apply a voltage to operate memory cell 105-b to read or write memory cell 105-b, as described above. In some embodiments, memory controller 140-a may include a row decoder, a column decoder, or both, as described with reference to FIG. 1, among others. This may enable memory controller 140-a to access one or more memory cells 105. The biasing component 710 may also provide a voltage potential to the reference component 720 to generate a reference signal for the sensing component 125-q. In addition, bias component 710 may provide a voltage potential for operation of sensing component 125-q.

in some embodiments, memory controller 140-a may perform its operations using timing component 715. For example, timing component 715 may control the timing of various word line selections or plate biases, including the timing for switching and voltage application to perform the memory functions discussed herein (e.g., read and write). In some embodiments, timing component 715 may control the operation of bias component 710.

In some embodiments, reference component 720 may generate a reference signal for sensing component 125-q. The reference component 720 may, for example, include circuitry configured to generate a reference signal. In some embodiments, the reference component 720 may be other ferroelectric memory cells 105. In some embodiments, the reference component 720 may be configured to output a voltage having a value between two sense voltages, as described with reference to fig. 3, among others. Alternatively, the reference component 720 may be designed to output a virtual ground voltage (i.e., about 0V).

In some embodiments, sensing component 125-1 may compare a signal from memory cell 105-b (via digit line 115-a) to a reference signal from reference component 720. Once the logic state is determined, the sensing component can store an output in latch 725, where the output can be used in accordance with the operation of the electronic device in which the memory array 100-a and other components or elements are used.

in some embodiments, memory controller 140-a may be associated with or in electronic communication with a first cell board and a second cell board, which may each be an embodiment of various boards 210 (described with reference to fig. 1-6, and others). The first digit line may be in electronic communication with the first cell plate and a first sensing component (e.g., a sense amplifier) via a first select component (e.g., a transistor). The second digit line may also be in electronic communication with a second cell plate and a second sensing component (e.g., a sense amplifier) via a second selection component (e.g., a transistor). In some embodiments, memory controller 140-a may be in electronic communication with one or more elements of memory array 100-a (as well as other memory arrays and/or memory devices), including, but not limited to, a first sensing element and/or a second sensing element.

Based at least in part on the electronic communication, the controller may be operable to initiate and/or perform one or more operations. In some embodiments, memory controller 140-a may be operable to determine or identify a current relationship associated with one plate 210 (e.g., 210-q), with two different proximate or adjacent plates (e.g., two plates as described with reference to fig. 4-6 and 11-14, and others), with one or more plates in a single plate group, with two or more plates (at least one of which is included in a plate group, page, segment, or layer that is distinct from the others, some combinations, and/or other components or elements).

In some embodiments, such a determination may include measuring, reading, writing, calculating, comparing, correlating, verifying, linking, analyzing, estimating, or accessing one or more characteristics, values, measurements, current or voltage levels or relationships, locations, performance relationships, operations, and/or other parameters specific to, related to, or based on one or more plates, digitlines, sensing components, selection components, and/or plate groups, among other things. In some embodiments, such identification may include detecting, distinguishing, comparing, correlating, measuring, reading, linking, analyzing, estimating, and/or accessing one or more characteristics, values, measurements, current or voltage levels or relationships, locations, performance relationships, operations, and/or other parameters specific to, related to, or based on one or more plates, digitlines, sensing components, selection components, and/or plate groups, among other things. As one example, memory controller 140-a may determine and/or identify a current relationship between a first cell plate and a second cell plate, which may be based at least in part on reading and/or otherwise receiving information from one or more sensing components each associated with at least one of the first cell plate and the second cell plate.

Based at least in part on this determination or identification, the memory control may initiate (e.g., send an instruction or signal to or control another element or component to operate) to operate to select the first cell plate and the second cell plate based at least in part on the spatial relationship. In some embodiments, such selection may include electronic communication from the controller to one or more selection components, which may include communicating with two or more selection components (e.g., including one or more selection component pairs) based at least in part on the determination or identification. In some embodiments, such spatial relationship may be based, at least in part, on absolute or relative positions of one or more cell plates or other elements or components.

In some embodiments, such spatial relationship may be based, at least in part, on the position of a first cell plate relative to a second cell plate, including whether these cell plates (and/or others) are adjacent, proximate, in a particular order, in a relative position within a group, and/or otherwise related to each other (and/or other cell plates and/or elements or components). For example, the selection may include and/or may be based at least in part on a spatial relationship relating to a position of the first cell plate in the first cell plate group relative to the second cell plate in the first cell plate group. The selection may include and/or may be based at least in part on the location of a first cell plate in the first cell plate group being in a "7" location (e.g., a final or final location) and the location of a second cell plate in the first cell plate group being in a "0" location (e.g., a first or initial location), in a "4" location (e.g., in a non-end point, an intermediate location), or in a "6" location (e.g., a neighboring location).

Additional cell boards (via the memory controller and/or one or more other elements or components) may be selected. For example, in some embodiments, a third cell plate may be included in the first group of cell plates, and a fourth cell plate may be included in the first group of cell plates, where each of these cell plates may be identified and/or determined to be associated with the first and second cell plates, as well as other elements or components. In some embodiments, memory controller 140-a is operable to select a third cellplate and a fourth cellplate based, at least in part, on the spatial relationship. For example, the third cell plate and/or the fourth cell plate may be selected based at least in part on determining that the third cell plate is adjacent to at least one of the first cell plate and the fourth cell plate (and in some embodiments, both the first cell plate and the fourth cell plate).

In some embodiments, this selection of the third cell plate and the fourth cell plate may be based, at least in part, on the spatial relationship of the third and fourth cell plates themselves. In other embodiments, this selection of the third cell plate and the fourth cell plate may be based at least in part on a spatial relationship between the first cell plate and the second cell plate. In other embodiments, this selection of the third cell plate and the fourth cell plate may be based, at least in part, on a spatial relationship between at least one of the first cell plate and the second cell plate and the third cell plate and the fourth cell plate.

In some embodiments, memory controller 140-a may initiate or be operable to read information from at least one of the first and second sensing components (and other elements or components) based at least in part on the selection. In some embodiments, this may include: memory controller 140-a reads values from a first sense amplifier and a second sense amplifier on selected two or more transistors corresponding to and/or otherwise related to two plates having and/or related to current relationships, among other factors.

Fig. 8 shows a diagram of a system 800 that supports selecting and operations related to one or more cell plates, according to various embodiments of the invention. The system 800 may include a device 805, which may be or include a printed circuit board that connects or physically supports various components. The device 805 may include a memory array 100-b, which may be an example of the memory array 100 described in fig. 1 and 7, among others. Memory array 100-b may contain a memory controller 140-b and one or more memory cells 105-c, which may be embodiments of memory controller 140 described with reference to fig. 1 and 7, among others, and memory cells 105 described with reference to fig. 1, 2, and 7, among others. The device 805 may also include a processor 810, a BIOS component 815, one or more peripheral components 820 and/or an input/output control component 825, among other components or elements. The components of the device 805 may be in electronic communication with each other over a bus 830.

the processor 810 may be configured to operate the memory array 100-a through the memory controller 140-b. In some embodiments, processor 810 performs the functions of memory controller 140 or 140-a described with reference to FIGS. 1 and 7, as well as others. In other embodiments, memory controller 140-b may be integrated into processor 810. The processor 810 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components, and the processor 810 may perform various functions described herein, including performing identification, determination, or selection related to one or more cell boards and/or other components or elements. The processor 810 may, for example, be configured to execute computer-readable instructions stored in the memory array 100-a to cause the device 805 to perform various functions or tasks.

The BIOS component 815 may be a software component that includes a basic input/output system (BIOS) operating as firmware, which may initialize and run various hardware components of the system 800. The BIOS component 815 may also manage the flow of data between the processor 810 and various components (e.g., peripheral components 820, input/output controller components 825, etc.). The BIOS component 815 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

The one or more peripheral components 820 may be any input or output device or interface for such a device that is integrated into the device 805. Embodiments may include a hard disk controller, a sound controller, a graphics controller, an ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot (e.g., a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot).

Input/output controller component 825 may manage data communication between processor 810 and peripheral components 820, input devices 835, or output devices 840. The input/output controller component 825 may also manage peripheral devices that are not integrated into the device 805. In some embodiments, the input/output controller component 825 may represent a physical connection or port to an external peripheral device.

Input 835 may represent a device or signal external to device 805 that provides input to device 805 or a component thereof. This may include a user interface or interfacing with or between other devices. In some embodiments, input 835 may be a peripheral that interfaces with device 805 via peripheral components 820 or may be managed by input/output controller components 825.

Output device 840 may represent a device or signal external to device 805 that is configured to receive output from the device or any of its components. Embodiments of output device 840 may include a display, an audio speaker, a printing device, another processor or printed circuit board, or the like. In some embodiments, the output device 840 may be a peripheral that interfaces with the device 805 via the peripheral components 820 or may be managed by the input/output controller components 825.

The components of memory controller 140-b, device 805, and memory array 100-b may be comprised of circuitry designed to perform their functions. This may include various circuit elements configured to implement the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements.

Fig. 9 shows a flow diagram illustrating a method 900 of selecting one or more cell plates and operations related to the one or more cell plates, in accordance with various embodiments of the present disclosure. The operations of the methods and techniques discussed with reference to fig. 4-8, as well as others, may be implemented by the memory array 100, as described with reference to fig. 1-8. For example, operations related to fig. 4-6, as well as other methods and techniques, may be performed by memory controller 140, as described with reference to fig. 1,7, and 8, as well as others. In some embodiments, the memory controller 140 may execute a set of codes to control the functional elements of the memory array 100 to perform the functions described below. Additionally or alternatively, the memory controller 140 may perform embodiments of the functions described below using dedicated hardware. Additionally or alternatively, memory controller 140 may initiate one or more signals and/or instructions to enable one or more other components or elements to perform the embodiments of the functions described below using dedicated hardware.

At block 905, the method may include identifying a first cell plate included in a first group of cell plates, as described with reference to fig. 1-8, among others. In some embodiments, this identification of the first cell plate may be based on one or more operational characteristics of the first cell plate, another cell plate, a combination of the first cell plate and the second cell plate, and/or one or more other individual cell plates. For example, the operating characteristics may include voltages, currents, values, current relationships associated with one or more plates, performance relationships associated with one or more plates, absolute positions of one or more plates and/or other components, relative positions of one or more plates and/or other components, some combinations, and/or other characteristics and/or relationships. In some embodiments, the operations of block 905 may be performed by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 905 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 905 may be performed by different elements and/or components of a memory array and/or memory device other than the memory controller 140.

At block 910, the method may include identifying a second cell plate adjacent to the first cell plate and/or included in the first cell plate group or the second cell plate group, as described with reference to fig. 1-8, among others. In some embodiments, this identification of the second cell plate may be based on one or more operating characteristics of the first cell plate, another cell plate, a combination of the first cell plate and the second cell plate, and/or one or more other individual cell plates, among other factors. For example, the operating characteristics may include voltage, current, value, current relationships associated with one or more plates, performance relationships associated with one or more plates, absolute positions of one or more plates and/or other components, relative positions of one or more plates and/or other components, some combination, and/or others. In some embodiments, the operations of block 910 may be performed by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 910 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 910 may be performed by different elements and/or components of a memory array and/or memory device, among others.

At block 915, the method may include selecting a first cell plate and a second cell plate based on a current relationship between the first cell plate and the second cell plate, as described with reference to fig. 1-8, among others. This selection may be performed by and/or may be performed on one or more memory elements or components, and/or may be based on electronic communication with one or more elements or components. In some embodiments, such selection may include selecting one or more selection components (which may include transistors, among others, in some embodiments). In some embodiments, such selection may include selecting one or more select element pairs that may enable the sense elements corresponding to each digit line to be accurately filled with data depending on each select element. In some embodiments, the method may further include reading from one or more sensing components associated with one or more selection components, plates, and/or digit lines based on the selection.

In some embodiments, the one or more selections may be based on one or more triggering events including, but not limited to, the fuse being triggered by one or more signals and/or one or more operating parameters associated with one or more elements or components (e.g., cell boards and/or sensing components). In some embodiments, the operations of block 915 may be performed by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 915 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 915 may be performed by different elements and/or components of a memory array and/or memory device, among others.

Fig. 10 shows a flow diagram illustrating a method 1000 of selecting one or more cell plates and operations related to the one or more cell plates, in accordance with various embodiments of the present disclosure. The operations of the methods and techniques discussed with reference to fig. 4-9, as well as others, may be implemented by the memory array 100, as described with reference to fig. 1-9. For example, operations related to fig. 4-6 and other related methods and techniques may be performed by memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the memory controller 140 may execute a set of codes to control the functional elements of the memory array 100 to perform the functions described below. Additionally or alternatively, the memory controller 140 may perform embodiments of the functions described below using dedicated hardware. Additionally or alternatively, memory controller 140 may initiate one or more signals and/or instructions to enable one or more other components or elements to perform the embodiments of the functions described below using dedicated hardware.

at block 1005, the method may include identifying a first cell plate included in a first cell plate group, as described with reference to fig. 1-9, and others. In some embodiments, such identification of the first cell plate may be based on one or more operational characteristics of the first cell plate, another cell plate, a combination of the first cell plate and the second cell plate, and/or one or more other individual cell plates. For example, the operating characteristics may include voltage, current, value, current relationships associated with one or more plates, performance relationships associated with one or more plates, absolute positions of one or more plates and/or other components, relative positions of one or more plates and/or other components, some combination, and/or others. In some embodiments, the operations of block 1005 may be performed by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 1005 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 1005 may be performed by different elements and/or components of a memory array and/or memory device, among others.

at block 1010, the method may include identifying a second cell plate adjacent to the first cell plate and/or included in the first cell plate group or the second cell plate group, as described with reference to fig. 1-8, among others. In some embodiments, this identification of the second cell plate may be based on one or more operational characteristics of the first cell plate, another cell plate, a combination of the first cell plate and the second cell plate, and/or one or more other individual cell plates. For example, the operating characteristics may include voltage, current, value, current relationships associated with one or more plates, performance relationships associated with one or more plates, absolute positions of one or more plates and/or other components, relative positions of one or more plates and/or other components, some combination, and/or others.

In some embodiments, identification of a second cell plate adjacent to the first cell plate may be made regardless of whether the second cell plate is included in a particular plate group (e.g., first cell plate group, second cell plate group). In some embodiments, the identification of a second cell plate that is adjacent to a first cell plate may be made based on whether the second cell plate is included in a particular plate group itself (e.g., a first cell plate group, a second cell plate group) and/or based on whether another plate (e.g., a first cell plate) is included in the same plate group (regardless of which particular plate group it is), a different plate group, a related plate group, an adjacent plate group, some combination, and/or other factors. In some embodiments, the operations of block 1010 may be performed by memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 1010 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 1010 may be performed by different elements and/or components of a memory array and/or memory device, among others.

At block 1015, the method may include identifying or determining that a first cell plate is included in a first cell plate group and a second cell plate is included in a second cell plate group, as described with reference to fig. 1-8 and others. Such identification and/or determination may be performed by and/or may be performed on one or more memory elements or components and/or may be based on electronic communication with one or more elements or components. In some embodiments, such identifying and/or determining may include identifying or determining a location and/or spatial relationship between the first cell plate and the second cell plate. Such identification or determination of a location and/or spatial relationship may be based, inter alia, on determining or identifying whether the second cell plate is located in the same cell plate group as the first cell plate.

Additionally or alternatively, such identification or determination of a location and/or spatial relationship may be based on, among other things, determining whether a second cell plate is adjacent to a first cell plate in a first cell plate group. Such identification or determination of a position and/or spatial relationship may be based on, among other things, determining or identifying whether the first cell plate and the second cell plate are positioned within absolute and/or relative respective positions within the first cell plate group and/or the second cell plate group. Such identification or determination of the position and/or spatial relationship may be based on, among other things, determining or identifying whether the first cell plate and the second cell plate are positioned relative to a plate pair related to and/or including a current relationship, which may or may not include the first cell plate and/or the second cell plate.

In some embodiments, the operations of block 1015 may be performed by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 1015 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 1015 may be performed by different elements and/or components of a memory array and/or memory device, among others.

At block 1020, the method may include identifying or determining that a first cell plate is in a last position in a first cell plate group and a second cell plate is in a first position in a second cell plate group, as described with reference to fig. 1-8 and others. Such identification and/or determination may be performed by and/or may be performed on one or more memory elements or components and/or may be based on electronic communication with one or more elements or components. In some embodiments, such identifying and/or determining may include identifying or determining a location of each of the first cell plate and the second cell plate and/or a spatial relationship between the first cell plate and the second cell plate. Such identification or determination of a location and/or spatial relationship may be based on, among other things, determining or identifying whether a second cell plate is adjacent (and other relationships) to a first cell plate, but where each of these is positioned in a separate cell plate group. This identification or determination may be based on one or more other identifying, determining, and/or selecting steps, among other things.

Such identification or determination of a position and/or spatial relationship may be based on, among other things, determining or identifying whether the first cell plate and the second cell plate are positioned within absolute and/or relative respective positions within the first cell plate group and/or the second cell plate group. For example, such identification or determination may be based on determining whether the first cell plate is in a first position and/or initial position (e.g., position "0") of the first cell plate group. Such identification or determination may be based on an identification and/or determination related to the first cell plate and may be based on a determination of whether the second cell plate is in a first position and/or an initial position (e.g., position "0"), an intermediate initial position (e.g., position "1" to position "6"), and/or a last and/or a final (e.g., position "7") in the second (or another) group of cell plates. Such identification or determination of the position and/or spatial relationship may be based on, among other things, determining or identifying whether the first cell plate and the second cell plate are positioned relative to a plate pair that is related to and/or includes a current relationship. In some embodiments, such a plate pair may or may not include a first cell plate and/or a second cell plate.

In some embodiments, the operations of block 1020 may be performed by memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 1020 may be initiated by the memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 1020 may be performed by different elements and/or components of a memory array and/or memory device, among others.

At block 1025, the method may include selecting a first cell plate and a second cell plate based on a short circuit between the two cell plates, as described with reference to fig. 1-8, among others. This selection may be performed by and/or may be performed on one or more memory elements or components and/or may be based on electronic communication with one or more elements or components. In some embodiments, such selection may include selecting one or more selection components (which may include transistors, among others, in some embodiments). In some embodiments, such selection may include selecting one or more select element pairs that may enable the sense elements corresponding to each digit line to be accurately filled with data depending on each select element. In some embodiments, the method may further include reading from one or more sensing components associated with one or more selection components, plates, and/or digit lines based on the selection.

in some embodiments, the one or more selections may be based on a triggering event including, but not limited to, the fuse being triggered by one or more signals and/or operating parameters associated with one or more elements or components (e.g., cell boards and/or sensing components). In some embodiments, the presence and/or determination (e.g., short circuit) of an unfavorable direct electron flow between two cell plates is based on. In some embodiments, the operations of block 1025 may be performed by memory controller 140, as described with reference to fig. 1,7, and 8, among others. In some embodiments, the operations of block 1025 may be initiated by memory controller 140, as described with reference to fig. 1,7, and 8, among others. In other embodiments, the operations of block 1025 may be performed by different elements and/or components of the memory array and/or memory device, among other things.

Other techniques for selecting plates based on detection of shorts are possible, as described with reference to fig. 11 to 14.

FIG. 11 shows a patch array 1100, which may be a portion of the memory array 100 described with respect to FIG. 1. Patch array 1100 is organized into a plurality of patches 1105, each of which may contain a plurality of plates (not shown). Each plate within patch 1105 may be associated with one or more memory cells. In some cases, a patch may be an instance of a plate group (e.g., plate groups 440-a, 440-b) along with memory cells and drivers associated with the plate group. In some cases, a patch may include distributed driver circuitry, such as one or more word line drivers, digit line drivers, and/or plate line drivers that may be coupled with corresponding word lines, digit lines, and/or plate lines associated with the patch, such as described in more detail with respect to fig. 12.

In some embodiments, a row of patches 1105 may be referred to as a segment 1110. The exemplary patch array 1100 is organized into 32 sectors 1110, where each sector 1110 includes a row of 18 patches. Other array sizes are possible. In some cases, each patch 1105 may include an array of memory cells; for example, a patch may include a 1000x1000 array of memory cells, or may be an array of another size, depending on the feature size and density of the memory array.

In some cases, a segment 1110 can be accessed via one or more word lines, such as word line 110. In some cases, a column of the patch array 1100 may be accessible via one or more digit lines, such as digit line 115.

In some cases, a memory array may include multiple layers 1115 of memory cells, where each layer is organized into patches 1105 and sectors 1110.

In some cases, a memory device may be configured to access the patch array 1100 based on the page size. The page size may be the minimum number of memory cells that can be selected for a memory access operation. For example, a memory device may be configured to access the patch array 1100 based on a page size of 64B, 128B, 256B, 2KB, etc. In this case, the memory device may select a page of memory cells for a memory access operation based on the page size. In some cases, a page of memory cells may be distributed throughout multiple patch blocks 1105. For example, if each patch 1105 includes four plates, performing a memory access operation based on a page size of 64B may include selecting the memory cells associated with the first plate in each patch in a section. Performing a memory access operation based on a page size of 128B may include selecting memory cells associated with two of the plates in each patch in a section. Performing a memory access operation based on a page size of 256B may include selecting all memory cells associated with all four plates in each patch in a section; for example, each memory cell of the sector is selected. Performing a memory access operation based on a page size greater than 256B may include selecting some or all of the memory cells (and thus some or all of the plates) in a plurality of sectors.

FIG. 12 shows a patch array 1200 that supports array plate short repair techniques according to an embodiment of the invention. The patch array 1200 includes an array of six patches 1205, where each patch 1205 includes four plates 1210 (plates 0, 1, 2, and 3). For example, patch array 1200 may be a portion of patch array 1100 or memory array 100. Each row 1235 in a patch 1205 of the patch array 1200 may be part of a section, such as the section 1110 described with respect to fig. 11.

The patch array 1200 includes wordline drivers 1215 for selecting or activating a plate 1210 and memory cells (not shown) associated with the plate 1210, a digit line driver 1220, and a sense component 1225. (for simplicity, FIG. 12 may not include all drivers and/or sensing components 1225 that may be present in each patch 1205.) in some cases, word line drivers 1215 and digit line drivers 1220 are distributed around the periphery of the patch 1205 to enable finer activation and selection of plates and memory cells, and to provide various other device advantages. In some cases, the sense component 1225 can be activated based on activation of the corresponding digit line driver 1220. In some cases, each sense component 1225 may be shared by two boards 1210 and may include 16 sense amplifiers.

In some embodiments, each of the four plates 1210 in the patch 1205 can be associated with a separate plate driver (not shown) such that each plate within the patch can be independently biased or activated. In some cases, each of the four pads 1210 in the patch 1205 may be associated with one or more digit lines (not shown) that may be coupled with a digit line driver 1220 of the patch 1205 to enable memory access operations of one or more memory cells associated with the pad 1210, such as described with respect to fig. 4-5.

In some embodiments, each of the four plates 1210 in the patch 1205 may be associated with one or more wordlines (not shown) that may be coupled with wordline drivers 1215 of the patch 1205 to enable selection of one or more memory cells associated with the plate 1210. In some cases, two or more plates 1210 within a patch 1205 can be associated with memory cells that share a common word line.

In some embodiments, the patch array 1200 may activate one or more wordline drivers 1215, digitline drivers 1220, and/or plateline drivers (not shown) to select a page of memory cells for a memory access operation. For example, if a (smaller) page of memory cells includes only memory cells associated with the first plate (plate 0) in each patch in a sector, activating a page of memory cells may include activating a word line driver, one or more digit line drivers, and a plate line driver associated with plate 0 of each patch 1205, without activating any drivers associated with the other plates in each patch. Activating a larger page of memory cells can include activating one or more word line drivers, digit line drivers, plate line drivers, etc., associated with, for example, plates 0 and 2 of each patch 1205.

In some cases, a first plate 1210 may have an accidental short circuit with a second plate 1210 (e.g., an adjacent plate within the same patch) due to, for example, a manufacturing defect. In the patch array 1200, for example, there is a short 1240-a between the first plate 1210-a and the second plate 1210-b in the patch of the first section 1235-a, and a short 1240-b between the second plate 1210-c and the third plate 1210-d in the patch of the second section 1235-c. In this case, activating plate 1210-a without activating the memory cells associated with plate 1210-b may result in data corruption (or other undesirable effects) of the memory cells associated with plate 1210-b, and the plates 1210-c and 1210-d cases are similar.

In some embodiments, a memory device can receive a memory access command associated with a first page size and a first page of a memory array that identifies the memory access command; for example, a first page of a memory array on which a memory access operation is to be performed is identified. In some cases, the first page may not include all of the plates in each patch in the section.

by way of example, the memory device may identify a first page of a memory array that includes all memory cells associated with the first plate 1210 (plate 0) of each patch 1205 in the section 1235-a based on the first page size.

In some embodiments, the memory device can determine whether there is a short associated with at least one memory cell of a second page of memory cells, wherein the second page is larger than and includes the first page. In this example, the second page may be in the same section 1235-a as the first page, and may include memory cells associated with one or more additional plates in each patch. For example, the second page may include all memory cells associated with plate 0 (e.g., the memory cells in the first page) and may also include all memory cells associated with plate 1 of each patch in the section 1235-a. In this case, because there is a short associated with plate 1210-b included in the second page, the memory device can determine that there is a short associated with at least one memory cell in the second page. Based on determining that there is a short associated with at least one memory cell in the second page, the memory device may activate the second page instead of activating only the first page. That is, the memory device may activate all of the memory cells associated with both plate 0 and plate 1 in each patch of the segment 1235-a rather than only activating the memory cells associated with plate 0. In this way, the memory device can mitigate the effects of a short circuit between plates 1210-a and 1210-b and avoid unwanted device behavior.

In the above example, the identified short 1240-a is associated with at least one memory cell in the first page; such as memory cells associated with plate 1210-a. That is, there is a short between the plate 1210-a contained in the first page and the plate 1210-b contained in the second page but not contained in the first page. However, in some embodiments, the memory array can activate the second page even if the short does not involve the plate or memory cells in the first page. For example, the memory array may determine whether there is a short associated with any memory cell in the segment containing the first page-even if the short does not involve any plate or memory cells in the first page-and if so, the memory array may activate the second (larger) page.

By way of example, the memory device can determine that there is a short 1240-b between memory cells associated with a first plate 1210-c in the segment 1235-c and memory cells associated with a second plate 1210-d in the segment 1235-c. Neither of the plates 1210-c, 1210-d is contained in the first page. In this case, the memory device may activate all of the memory cells associated with all of the plates 1210 in the section 1235-c based on determining that there is a short, which may be equivalent to activating a larger page of memory cells. Thus, in some cases, if the memory device determines that there is a short anywhere within the section including the first page, the memory device may activate all of the memory cells in the section and thereby "facilitate" the memory access operation to a larger (e.g., maximum) page size.

In some embodiments, the memory array may perform a memory access operation (e.g., a read operation) on all memory cells in a second (larger) page, and thereby generate a complete set of data for the second page. In some embodiments, the memory array may transmit the complete set of data to another component, e.g., via an I/O line or the like. In some cases, the memory array may only transmit a portion of the complete set of data; for example, data for the first page. The memory array may discard (e.g., refrain from transmitting) data for the remaining cells in the second page.

In some embodiments, activating the second page can include activating all of the drivers and access lines associated with all of the memory cells in the second page. In some cases, activating the second page can include activating all drivers and access lines associated with all memory cells in the first page, but only activating plate lines and digit lines associated with the remaining cells in the second page. The latter approach may reduce the amount of power associated with the memory access operation while still ensuring that the memory cells associated with the shorting plate are not damaged during the memory access operation. In this case, the memory access operation may not be performed on all memory cells in the second page; the memory access operation may be performed only on the memory cells in the first page (e.g., selected aspects of the memory access operation may be performed only on all of the memory cells in the second page).

In some embodiments, if the memory array determines that there are no shorts associated with the memory cells in the second page, e.g., if the second page is in section 1235-b and does not include any shorting plates, the memory array may select only the first page of memory cells and not the remaining cells in the second page. That is, if the memory array determines that there is no short, the memory array may perform a memory access operation based on the first page size as usual.

In some embodiments, the memory array can be configured to activate a larger page (e.g., a section) of memory cells in response to identifying a short anywhere within a section containing smaller pages of memory cells, whether or not the short is associated with memory cells in the first page. This may be referred to as a zone level of granularity of short repair, and in this case a single fuse or signal may be used to indicate whether there is a short throughout the zone. In other embodiments, the memory array can be configured to activate larger pages (e.g., 128B, 256B) of memory cells based on finer granularity. For example, the memory array may be configured to activate a larger page of memory cells only when a detected short is associated with a plate included in the first page of memory cells. This may be referred to as board level granularity, and additional fuses or signals (e.g., more than one fuse or signal per segment) may be required to provide separate signals indicating shorts within different page sizes. In other embodiments, the memory array can be configured to activate larger pages of memory cells based on a coarser granularity. For example, a multi-layer memory array may be configured to activate a larger page (e.g., a section) of memory cells in response to identifying a short anywhere within the same section of any layer, whether the short is within the first page or within the same layer as the first page. In this case, a single fuse or signal may be shared among the layers and used to indicate whether a short exists in a particular segment number of any layer.

FIG. 13 illustrates an example memory array 1300 that supports techniques for array plate short repair, according to an embodiment of the invention. Memory array 1300 includes a command component 1305, a logic component 1310, and a patch array 1315. The command component 1305 and/or the logic component 1310 may be included in a memory controller, such as the memory controller 140. Memory array 1300 may be an example of a memory array configured to detect and repair shorts at a granularity of a sector level; that is, if the memory array 1300 determines that there is a short anywhere within a section containing the first page to be accessed, the memory array 1300 may activate all of the memory cells in the section and/or operate in a larger page size mode.

The command component 1305 may be configured to receive a memory access command specifying a memory access operation, such as a read, write, set, or reset operation. The memory access command may be associated with a first page size of memory cells. The command component may be configured to identify a first page in a section of the patch array 1315 for a memory access operation based on a first page size, and send an address range associated with a first page sizer unit based on a memory access command. In the exemplary memory array 1300, the patch array 1315 includes 32 sectors, and the command component 1305 may send an address range, such as a sector address and/or a sector number, that includes an indication of the patch array 1315 of the sector.

The logic component 1310 may be configured to receive an address range (e.g., a sector address and/or a sector number) from a command component. Logic component 1310 may be configured to also receive a fuse signal for each section that indicates whether there is a short associated with at least one of the memory cells of that section. For example, if there is a short between two plates in section 0, fuse signal 0 may be set to a "1" value or otherwise asserted, thereby indicating a short in section 0. The fuse signal may be received from a physical or logical fuse triggered based on detection of a short in the corresponding section, such as described, for example, with respect to fig. 4.

The logic component may activate a repair signal 1320 based on the received address range and the corresponding fuse signal. In some cases, the logic components include a physical or logical or tree, such as depicted in fig. 13, if any fuse signal is set to a "1" value (or otherwise asserted) and the address in the corresponding section is received from the command component, the repair signal 1320 is activated; for example, if the command component sends a sector address for a sector that has a short circuit between two boards in the sector. Those skilled in the art will appreciate that other techniques for identifying shorts and activating repair signals may be used for similar effects. Further, while the OR tree depicted in FIG. 13 may be associated with a segment level of granularity for short detection and repair, other OR trees (or other types of logic) may be suitable for different levels of granularity. For example, for board level granularity, or trees may include additional fuse signals or repair signals.

The patch array 1315 can be coupled with the logic component 1310 and configured to activate a larger page of memory cells (e.g., a segment) based at least in part on activation of the repair signal 1320. In some embodiments, patch array 1315 may be configured to operate in a larger page size mode whenever repair signal 1320 is activated. In some cases, activating the repair signal adjusts the address range associated with the first page of memory cells to the address range associated with the second, larger page of memory cells.

For a multi-layer memory device, the same fuse signal may be shared between layers, or each layer may have its own set of independent fuse signals. If the same fuse signal is shared between the layers, the command component may be configured to send an indication of a segment number associated with a first page for a memory access operation based at least in part on the memory access command, where the first page is in a section with that segment number of the first layer. The logic component may be configured to receive an indication of a segment number and activate a repair signal if there is a short associated with a memory cell in the same segment number, whether the memory cell is in the first tier or the second tier. For example, if the first page is in section (1) of layer 2 and there is a short between the two plates in section (1) of layer 1, the repair signal may be activated, and the memory array may in turn activate the larger page of memory cells in layer 2. This approach may reduce the number of fuses needed to indicate a short at the potential cost of performing larger page size accesses more frequently.

Electronic memory devices according to various embodiments of the present invention are described. The electronic memory device may include: a memory array comprising a first page of memory cells having a first page size and a second page of memory cells comprising the first page and having a second page size; a command component to: receiving a memory access command associated with the first page size memory cells in the memory array; sending a range of addresses associated with the first page of memory cells based at least in part on the memory access command; and a logic component coupled with the command component and the memory array, the logic component configured to: receiving, from the command component, the address range associated with the first page of memory cells; and activating a signal based at least in part on the address range and in response to determining that there is a short associated with at least one memory cell of the second page of memory cells, wherein the memory array is configured to activate the second page of memory cells based at least in part on the activation of the signal.

In some examples, an electronic memory apparatus may include: a first plate associated with the at least one memory cell; and a second plate associated with at least a second memory cell in the second page, wherein the determination that there is a short associated with the at least one memory cell includes determining that the first plate is shorted to the second plate.

In some examples, activating the second page of memory cells includes activating the first plate and the second plate.

In some examples, the first plate is a first shared plate associated with a first plurality of memory cells including the at least one memory cell, and the second plate is a second shared plate associated with a second plurality of memory cells including the at least the second memory cell. In some examples, the logical component includes an or tree.

Electronic memory devices according to various embodiments of the present invention are described. The electronic memory apparatus may include: a memory array comprising a plurality of layers of memory cells each comprising a plurality of sectors divided into a plurality of pages of memory cells; a command component configured to: receiving a memory access command associated with a first page size; sending an indication of a segment number associated with a first page of the plurality of pages based at least in part on the memory access command, wherein the first page has the first page size and is in a first segment associated with the segment number; and a logic component coupled with the command component and the plurality of layers, the logic component configured to: receiving the indication of the segment number; and activating a signal in response to determining that there is a short associated with at least one memory cell in a second section associated with the section number based at least in part on the indication, wherein the memory array is configured to activate all of the memory cells in the first section based at least in part on the activation of the signal.

In some examples, the second section is in a different layer than the first section. In some examples, the second section and the first section are the same section in the same layer.

Electronic memory devices according to various embodiments of the present invention are described. The electronic memory apparatus may include: a memory array comprising a plurality of layers of memory cells each comprising a plurality of sectors divided into a plurality of pages of memory cells; a command component configured to: receiving a memory access command associated with a first page size; sending an indication of a segment number associated with a first page of the plurality of pages based at least in part on the memory access command, wherein the first page has the first page size and is in a first segment associated with the segment number; and a logic component coupled with the command component and the plurality of layers, the logic component configured to: receiving the indication of the segment number; and based at least in part on the indication, activating a signal in response to determining that there is a short associated with at least one memory cell in a second section associated with the section number, wherein the memory array is configured to activate all of the memory cells in the first section based at least in part on the activation of the signal.

Fig. 14 shows a flow diagram illustrating a method 1400 of selecting one or more cell plates and operations related to the one or more cell plates, in accordance with various embodiments of the invention. The operations of the methods and techniques discussed with reference to fig. 11-13, as well as others, may be implemented by the memory array 100 or the patch arrays 1100, 1200, 1315 described with reference to fig. 1-13. For example, the operations of methods and techniques related to fig. 11-13 and others may be performed by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13 and others. In some embodiments, memory controller 140 may execute a set of codes to control the functional elements of memory array 100 or patch arrays 1100, 1200, 1315 to perform the functions described below. Additionally or alternatively, the memory controller 140 may perform embodiments of the functions described below using dedicated hardware. Additionally or alternatively, memory controller 140 may initiate one or more signals and/or instructions to enable one or more other components or elements to perform the embodiments of the functions described below using dedicated hardware.

At block 1405, the method may include receiving a memory access command for a memory access operation associated with memory cells of a first page size. In some embodiments, for example, the first page size may be 64B or 128B. In some embodiments, the first page size may be specified by a memory access command. In some embodiments, the first page size may not be specified by a memory access command, and a memory controller and/or memory array (or other portion of a memory device) may be configured to execute memory access commands based on the first page size.

In some embodiments, the operations of block 1405 may be performed by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In some embodiments, the operations of block 1405 may be initiated by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In other embodiments, the operations of block 1405 may be performed by different elements and/or components of a memory array and/or memory device, among others.

At block 1410, the method may include identifying, based at least in part on a memory access command, a first page of memory cells to be activated for the memory access operation, the first page having the first page size. In some embodiments, the memory cells of the first page may be identified by the memory controller 140. In some embodiments, the first page may include memory cells associated with one or more plates in each patch in a section; for example, the first page may include memory cells associated with the first plate of each patch in a section or with the first and second plates of each patch in the section, and so on.

In some embodiments, the operations of block 1410 may be performed by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In some embodiments, the operations of block 1410 may be initiated by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In other embodiments, the operations of block 1410 may be performed by different elements and/or components of a memory array and/or memory device, among other things.

At block 1415, the method may include determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size. In some embodiments, for example, the second page size may be 128B or 256B. In some cases, determining whether there is a short associated with the at least one memory cell includes: it is determined whether a short exists between a first plate associated with the at least one memory cell and a second plate associated with a second memory cell. In some cases, the at least one memory cell may be included in the first page, and the second memory cell may be included in the second page but not the first page. In some examples, determining whether a short exists may include receiving a signal indicating that a short exists, such as receiving a fuse signal from a fuse or receiving a repair signal from a logic component, as described with respect to fig. 13. In some cases, determining whether a short exists may include performing a post-manufacturing or run-time test of the memory array that determines that a short exists and optionally triggering the corresponding fuse.

In some embodiments, the operations of block 1415 may be performed by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In some embodiments, the operations of block 1415 may be initiated by the memory controller 140 and/or the command component 1305 and the logic component 1310, as described with reference to fig. 1,7, 8, and 13, among others. In other embodiments, the operations of block 1415 may be performed by different elements and/or components of the memory array and/or the memory device, among others.

At block 1420, the method may include activating the second page of memory cells based at least in part on determining that there is a short associated with the at least one memory cell. In some examples, the memory controller and/or the memory array or the patch array may activate the second page of memory cells by activating one or more word lines, digit lines, and/or plate lines associated with the second page of memory cells. In some examples, activating the second page of memory cells includes promoting a memory access operation from an access based on a first page size to an access based on a second page size by, for example, adjusting an address range associated with the first page to an address range associated with the second page.

In some embodiments, the operations of block 1420 may be performed by memory controller 140 and/or command component 1305, logic component 1310, and/or patch arrays 1100, 1200, 1315, as described with reference to fig. 1,7, 8, and 11-13, among others. In some embodiments, the operations of block 1420 may be initiated by memory controller 140, command component 1305, logic component 1310, and/or patch arrays 1100, 1200, 1315, as described with reference to fig. 1,7, 8, and 11-13, among others. In other embodiments, the operations of block 1420 may be performed by different elements and/or components of a memory array, patch array, and/or memory device, among others.

An apparatus for performing the method 1400 is described. The apparatus may include: means for receiving a memory access command for a memory access operation associated with a first page size of memory cells; means for identifying, based at least in part on the memory access command, a first page of memory cells to be activated for the memory access operation, the first page having the first page size; means for determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size; and means for activating the second page of memory cells based at least in part on determining that there is a short circuit associated with the at least one memory cell.

In some examples, the means for determining whether there is a short associated with at least one memory cell may include means for determining whether a first plate associated with the at least one memory cell of the second page is shorted with a second plate associated with at least a second memory cell of the second page.

In some examples, the at least the second memory cells are included in the first page and the at least the second memory cells are not included in the first page.

In some examples, the second page of memory cells includes a third page of memory cells separate from the first page, and the apparatus may include: means for activating a first access line associated with the first page of memory cells and a second access line associated with the third page of memory cells based at least in part on the determination that there is a short circuit associated with the at least one memory cell, wherein the means for activating the second page of memory cells can include means for activating the first access line and the second access line.

In some examples, the first access line and the second access line are a first plate line and a second plate line, or a first digit line and a second digit line.

In some examples, the means for activating the second page may include: means for activating a first word line associated with the first page; and means for activating a digit line and a plate line associated with the at least the second memory cell without activating a second word line associated with the at least the second memory cell.

In some examples, the apparatus may include: means for activating a first driver associated with the first access line and a second driver associated with the second access line based at least in part on the determination that there is a short circuit associated with the at least one memory cell. In some examples, the means for activating the second page of memory cells may include means for activating the first driver and the second driver.

In some examples, the apparatus may include: means for activating a first plurality of sense amplifiers associated with the first page of memory cells and a second plurality of sense amplifiers associated with the third page of memory cells based at least in part on the determination that there is a short circuit associated with the at least one memory cell. In some examples, the first plate is a first shared plate associated with a first plurality of memory cells including the at least one memory cell, and the second plate is a second shared plate associated with a second plurality of memory cells including the at least the second memory cell. In some examples, the first plate is a first cell plate associated with the at least one memory cell and the second plate is a second cell plate associated with the at least the second memory cell.

In some examples, the first plate and the second plate are adjacent plates in a patch comprising a plurality of plates associated with a plurality of memory cells, and the apparatus may include: means for activating all of the plurality of memory cells in the patch based at least in part on the determination that there is a short associated with the at least one memory cell.

In some examples, the first plate and the second plate are in different patches.

In some examples, the apparatus may include means for performing the memory access operation on the second page of memory cells. In some examples, the means for performing the memory access operation on the second page may include: means for generating a first set of data for the first page and a second set of data for a remaining plurality of cells in the second page; means for transmitting the first set of data; and means for refraining from transmitting the second set of data.

In some examples, the apparatus may include: means for activating the first page of memory cells without activating a remaining plurality of cells in the second page based at least in part on determining that there is no short associated with the at least one memory cell.

In some examples, the memory access command specifies the first page size.

In some examples, the means for determining whether there is a short circuit associated with the at least one memory cell may include means for receiving a signal indicating whether there is a short circuit associated with the at least one memory cell.

Thus, methods 900, 1000, and 1400 and other methods described throughout this disclosure and contemplated by this disclosure may provide for selection of one or more cell plates and operations associated with the cell plates using one or more elements or components. It should be noted that: methods 900, 1000, and 1400 and other described possible implementations contemplated throughout the description and this disclosure, and operations and steps may be rearranged, omitted, modified, supplemented, or otherwise modified such that other implementations are possible and contemplated. In some embodiments, embodiments from two or more of the methods 900, 1000, and 1400 and other methods described throughout and contemplated by the present invention may be combined.

The description herein provides embodiments, and is not limited in scope, capability, or embodiment as set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the invention. Various embodiments may omit, substitute, or add various programs or components as appropriate. Moreover, features described with respect to some embodiments may be combined in other embodiments.

The description set forth herein in connection with the appended drawings describes example configurations and is not intended to represent all embodiments which may be practiced or within the scope of the claims. As used herein, the terms "example" and "exemplary" mean "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dashed line and a second label that distinguishes among the similar components. When a first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, it should be understood by one of ordinary skill in the art that the signals may represent a signal bus, where the bus may have a variety of bit widths.

As used herein, the term "virtual ground" refers to a node of a circuit that is held at a voltage of about zero volts (0V) but is not directly connected to ground. Thus, the voltage of the virtual ground may temporarily fluctuate and return to about 0V at steady state. The virtual ground may be implemented using various electronic circuit elements, such as a voltage divider composed of an operational amplifier and a resistor. Other embodiments are possible.

The term "electronic communication" refers to the relationship between components that supports the flow of electrons between the components. This may include direct connections between components and/or may include intermediate components. Components in electronic communication may or may not actively exchange electrons or signals (e.g., in a powered circuit) but may be configured and operated to exchange electrons or signals after the circuit is powered on. By way of example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

as used herein, the term "short" refers to a direct conductive path established between two conductive elements. In some cases, the conductive path between two elements may be an unintended conductive path resulting from a manufacturing defect or device damage. For example, two conductive elements (e.g., two plates or two wires) designed to be manufactured physically close to each other may be accidentally shorted together if a manufacturing defect results in an accidental conductive path being established between the two elements. The short circuit may allow current to travel along an unintended path with a very low (e.g., negligible) electrical impedance, which may result in damage to one or both of the shorted elements or components electrically connected to one or both of the elements.

The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-Sapphire (SOP) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. The doping may be performed by ion implantation or any other doping method during the initial formation or growth of the substrate.

the transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerated) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. Similarly, if the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be covered by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The various illustrative blocks, components, and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other embodiments and implementations are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features implementing functions may also be physically located at various locations, including: are distributed such that portions of the functionality are implemented at different physical locations. Further, as used herein, including in the claims, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as at least one of ". or one or more of". such that, for example, a list of at least one of A, B or C components means a or B or C or AB or AC or BC or ABC (i.e., a and B and C).

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the present invention is not intended to be limited to the embodiments and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.