阅读说明：本技术 半导体装置及其制造方法 (semiconductor device and method for manufacturing the same ) 是由 筱原博文 于 2019-06-05 设计创作，主要内容包括：本发明涉及半导体装置以及制造方法。半导体装置(1)具备：包括第1导电型的高浓度漏极区域(14a)、第1漏极漂移区域(14b)和第2漏极漂移区域(14c)的第1导电型的漏极区域(14)、第1导电型的源极区域(15)、第2导电型的体区域(16)、栅极绝缘膜(12)、栅极电极(13)、以及在漏极区域(14)上形成的STI绝缘膜(11)。以从远离STI绝缘膜(11)的第1角部(11a)距离x1的第1位置(11f)朝向第2角部(11b)的方向延伸的方式形成第2漏极漂移区域(14c)。(The invention relates to a semiconductor device and a manufacturing method. A semiconductor device (1) is provided with: the semiconductor device includes a 1 st conductivity type drain region (14) including a 1 st conductivity type high concentration drain region (14 a), a 1 st drain drift region (14 b), and a 2 nd drain drift region (14 c), a 1 st conductivity type source region (15), a 2 nd conductivity type body region (16), a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). A2 nd drain drift region (14 c) is formed so as to extend from a 1 st position (11 f) distant from a 1 st corner (11 a) of the STI film (11) by a distance x1 in a direction toward a 2 nd corner (11 b).)

1. A semiconductor device is formed on a semiconductor substrate, and includes: a drain region of a 1 st conductivity type, a source region of a 1 st conductivity type, a body region of a 2 nd conductivity type formed between the drain region and the source region, a gate insulating film formed on the body region, a gate electrode formed on the gate insulating film, a trench provided in the drain region, and a thick film insulating film formed in the trench and having a film thickness thicker than that of the gate insulating film, the semiconductor device being characterized in that,

The trench has: a 1 st trench side surface facing the body region, a 2 nd trench side surface formed so as to face the 1 st trench side surface and the body region and be further from the body region than the 1 st trench side surface, a trench bottom surface, a 1 st corner portion provided at an intersection of the trench bottom surface and the 1 st trench side surface in cross section, and a 2 nd corner portion provided at an intersection of the trench bottom surface and the 2 nd trench side surface,

The drain region includes: a 1 st drain drift region formed so as to contact the trench bottom surface from the body region, the 1 st trench side surface and the 1 st corner to a 1 st position, a 2 nd drain drift region formed so as to extend from the 1 st position in a direction toward the 2 nd corner and to contact the trench bottom surface and having an impurity concentration higher than that of the 1 st drain drift region, and a high-concentration drain region formed so as to be distant from the body region, the 1 st trench side surface and the trench bottom surface and having an impurity concentration higher than that of the 2 nd drain drift region.

2. The semiconductor device according to claim 1, wherein a sidewall insulating film is provided so as to be in contact with a side surface of the gate electrode facing the high-concentration drain region, and wherein the 1 st position is substantially the same as a position of an end portion of the sidewall insulating film facing the high-concentration drain region in a plan view.

3. The semiconductor device according to claim 1, wherein a region which is in contact with the 2 nd drain drift region and includes the 2 nd corner and the high-concentration drain region in a plan view has a 3 rd drain drift region having an impurity concentration higher than that of the 2 nd drain drift region.

4. The semiconductor device according to claim 2, wherein a region which is in contact with the 2 nd drain drift region and includes the 2 nd corner and the high-concentration drain region in a plan view has a 3 rd drain drift region having an impurity concentration higher than that of the 2 nd drain drift region.

5. The semiconductor device according to claim 3,

A 2 nd sidewall insulating film formed in contact with the 1 st trench side surface and the 2 nd trench side surface and the thick film insulating film formed in contact with the 2 nd sidewall insulating film are provided in the trench,

The 2 nd sidewall insulating film formed so as to be in contact with the 1 st trench side surface is formed on the trench bottom surface between the 1 st corner and the 1 st position.

6. The semiconductor device according to claim 4,

A 2 nd sidewall insulating film formed in contact with the 1 st trench side surface and the 2 nd trench side surface and the thick film insulating film formed in contact with the 2 nd sidewall insulating film are provided in the trench,

The 2 nd sidewall insulating film formed so as to be in contact with the 1 st trench side surface is formed on the trench bottom surface between the 1 st corner and the 1 st position.

7. The semiconductor device according to any one of claims 1 to 6, wherein a region between the body region and the 1 st trench side face and in contact with the 1 st trench side face and below the gate insulating film to a depth shallower than the 1 st corner portion has a surface drain drift region having an impurity concentration higher than that of the 1 st drain drift region.

8. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor substrate is an SOI substrate.

9. A method for manufacturing a semiconductor device, the semiconductor device being formed on a semiconductor substrate and including a thick-film insulating film having a thickness larger than a thickness of a gate insulating film in a drain region including an impurity of a 1 st conductivity type, the method comprising:

A 1 st drain drift region forming step of implanting a 1 st conductivity type impurity from a surface of the semiconductor substrate to form a 1 st drain drift region in the drain region;

A 1 st insulating film opening forming step of depositing a 1 st insulating film on the semiconductor substrate, and etching the 1 st insulating film to form an opening;

A trench forming step of forming a trench by etching the semiconductor substrate using the 1 st insulating film opening as a mask, the trench having a 1 st trench side surface, a 2 nd trench side surface, a trench bottom surface, a 1 st corner portion formed at an intersection of the 1 st trench side surface and the trench bottom surface, and a 2 nd corner portion formed at an intersection of the 2 nd trench side surface and the trench bottom surface;

A thick film insulating film forming step of forming a thick film insulating film in the trench by depositing a 2 nd insulating film on the semiconductor substrate and in the trench to a thickness such that an upper surface of the trench is flat, and then removing the 2 nd insulating film in a region other than the trench;

A gate insulating film forming step of forming the gate insulating film on the semiconductor substrate;

A gate electrode forming step of forming a gate electrode on the gate insulating film; and

And a 2 nd drain drift region forming step of forming a 2 nd drain drift region of a 1 st conductivity type having an impurity concentration higher than that of the 1 st drain drift region in the 1 st drain drift region and in contact with the trench bottom surface in a direction from a 1 st position distant from the 1 st corner toward the 2 nd corner along the trench bottom surface.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the 2 nd drain drift region forming step is a step of forming the 2 nd drain drift region by ion-implanting an impurity of the 1 st conductivity type through the thick film insulating film at an implantation energy of a magnitude exceeding the bottom surface of the trench after the thick film insulating film forming step.

11. the method for manufacturing a semiconductor device according to claim 10,

The gate electrode forming step further includes a step of forming a 1 st sidewall insulating film so as to be in contact with both side surfaces of the gate electrode by depositing a 3 rd insulating film on the gate electrode and then etching back the 3 rd insulating film by anisotropic etching,

the 2 nd drain drift region forming step is a step of forming a 2 nd drain drift region by ion-implanting a 1 st conductivity type impurity with implantation energy having a magnitude exceeding a bottom surface of the trench, using the 1 st sidewall insulating film on a side surface of the gate electrode facing the drain region as a mask.

12. The method for manufacturing a semiconductor device according to claim 9,

The trench forming step is a step of forming the trench by anisotropic dry etching of the semiconductor substrate using the 1 st insulating film as a mask and further by continuing isotropic etching so that the 1 st corner portion and the 2 nd corner portion extend outside the opening of the 1 st insulating film in a plan view, and further,

The 2 nd drain drift region forming step is a step of ion-implanting an impurity of the 1 st conductivity type using the 1 st insulating film as a mask to form a 2 nd drain drift region in a direction from the 1 st position along the trench bottom surface toward the 2 nd corner portion, and,

The thick film insulating film forming step is performed after the 2 nd drain drift region forming step.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the 2 nd drain drift region forming step is a step of: after the trench forming step, a 4 th insulating film is deposited in the trench and on the semiconductor substrate to a thickness not completely filling the trench, the 4 th insulating film is etched back to form a 2 nd sidewall insulating film on the 1 st trench side surface and the 2 nd trench side surface, and a 1 st conductivity type impurity is ion-implanted using the 2 nd sidewall insulating film as a mask to form the 2 nd drain drift region in a direction from the 1 st position along the trench bottom surface toward the 2 nd corner.

14. The method for manufacturing a semiconductor device according to any one of claims 9 to 13, comprising a 3 rd drain drift region forming step, wherein the 3 rd drain drift region forming step is a step of: after the gate electrode forming step, a 1 st conductivity type impurity is ion-implanted at an inclination angle of 15 degrees or more using the gate electrode as a mask, and a 3 rd drain drift region having an impurity concentration higher than that of the 1 st drain drift region is formed in a region in contact with the 1 st trench side surface and having a depth not reaching the 1 st corner.

Technical Field

The invention relates to a semiconductor device and a method for manufacturing the same.

Background

In recent years, with the development of high-functionality ultrasonic diagnostic devices used for nondestructive testing of medical diagnostic devices, building structures, and the like, or sonar or devices for underwater communication, there is an increasing demand for ICs (Integrated circuits) that can operate at high power supply voltages and supply large currents to loads. Therefore, a semiconductor device having high breakdown voltage and low on-resistance is required for an output element in such an IC.

As a Semiconductor device having high breakdown voltage and low on-resistance that can be integrated on a Semiconductor substrate and used for supplying a switching signal or amplifying the amplitude of the signal, an LDMOSFET (laterally diffused Metal Oxide Semiconductor Field Effect Transistor) is known.

In general, the drain drift region is extended in length to form a thick insulating film or the like on the drain drift region to relax the drain electric field, thereby increasing the withstand voltage of the drain of the LDMOSFET. In many cases, a thick insulating film is used in combination with an element isolation film used in a CMOS logic circuit integrated at the same time. Therefore, for example, when a design rule larger than approximately 0.25um is adopted in a semiconductor manufacturing process for manufacturing a semiconductor device, a LOCOS (Local Oxidation of Silicon) insulating film used for element isolation is adopted as the thick insulating film.

patent document 1 (see fig. 1) discloses a technique for realizing the following LDMOSFET: by forming an STI (Shallow Trench Isolation) insulating film as a thick insulating film in the drain drift region of the LDMOSFET, the required area on the plane is reduced while the drain withstand voltage is increased while the length of the drain drift region is extended in the vertical direction, and the on-resistance per unit area is reduced.

Disclosure of Invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and a method for manufacturing the same, which can suppress hot carrier degradation and achieve higher withstand voltage of a drain, reduction in on-resistance, and improvement in long-term reliability.

Means for solving the problems

In order to solve the above problem, the present invention employs the following means.

That is, the semiconductor device is formed on a semiconductor substrate, and includes: a drain region of a 1 st conductivity type, a source region of a 1 st conductivity type, a body region of a 2 nd conductivity type formed between the drain region and the source region, a gate insulating film formed on the body region, a gate electrode formed on the gate insulating film, a trench provided in the drain region, and a thick film insulating film formed in the trench and having a film thickness thicker than that of the gate insulating film, the semiconductor device characterized in that the trench has: a 1 st trench side surface facing the body region, a 2 nd trench side surface formed so as to face the 1 st trench side surface and the body region and be farther from the body region than the 1 st trench side surface, a trench bottom surface, a 1 st corner portion provided at an intersection of the trench bottom surface and the 1 st trench side surface in cross section, and a 2 nd corner portion provided at an intersection of the trench bottom surface and the 2 nd trench side surface, the drain region including: a 1 st drain drift region formed so as to contact the trench bottom surface from the body region, the 1 st trench side surface and the 1 st corner to a 1 st position, a 2 nd drain drift region formed so as to extend from the 1 st position in a direction toward the 2 nd corner and to contact the trench bottom surface and having an impurity concentration higher than that of the 1 st drain drift region, and a high-concentration drain region formed so as to be distant from the body region, the 1 st trench side surface and the trench bottom surface and having an impurity concentration higher than that of the 2 nd drain drift region.

Further, a method for manufacturing a semiconductor device, which is formed on a semiconductor substrate and includes a thick-film insulating film having a thickness thicker than a thickness of a gate insulating film on a drain region including an impurity of a 1 st conductivity type, is provided, the method comprising: a 1 st drain drift region forming step of implanting a 1 st conductivity type impurity from a surface of the semiconductor substrate to form a 1 st drain drift region in the drain region; a 1 st insulating film opening forming step of depositing a 1 st insulating film on the semiconductor substrate, and etching the 1 st insulating film to form an opening; a trench forming step of forming a trench by etching the semiconductor substrate using the 1 st insulating film opening as a mask, the trench having a 1 st trench side surface, a 2 nd trench side surface, a trench bottom surface, a 1 st corner portion formed at an intersection of the 1 st trench side surface and the trench bottom surface, and a 2 nd corner portion formed at an intersection of the 2 nd trench side surface and the trench bottom surface; a thick film insulating film forming step of forming a thick film insulating film in the trench by depositing a 2 nd insulating film on the semiconductor substrate and in the trench to a thickness such that an upper surface of the trench is flat, and then removing the 2 nd insulating film in a region other than the trench; a gate insulating film forming step of forming the gate insulating film on the semiconductor substrate; a gate electrode forming step of forming a gate electrode on the gate insulating film; and a 2 nd drain drift region forming step of forming a 2 nd drain drift region of a 1 st conductivity type having an impurity concentration higher than that of the 1 st drain drift region in the 1 st drain drift region and in contact with the trench bottom surface in a direction from a 1 st position distant from the 1 st corner toward the 2 nd corner along the trench bottom surface.

Effects of the invention

According to the present invention, the impurity concentration in the vicinity of the corner of the STI insulating film in the drain drift region is reduced to relax the drain electric field, thereby suppressing hot carrier degradation. In the drain drift region, the impurity concentration of a region which is separated by a predetermined distance from the corner of the STI insulating film toward the high-concentration drain region can be increased, thereby reducing the on-resistance. Therefore, a semiconductor device having both high withstand voltage of the drain, reduction in on-resistance, and improvement in long-term reliability can be realized.

Drawings

Fig. 1 is a sectional view of a semiconductor device according to embodiment 1 of the present invention.

Fig. 2 is a sectional view showing a manufacturing process of a semiconductor device according to embodiment 1.

Fig. 3 is a sectional view of a semiconductor device according to embodiment 2 of the present invention.

Fig. 4 is a sectional view showing a manufacturing process of a semiconductor device according to embodiment 2.

Fig. 5 is a sectional view of a semiconductor device according to embodiment 3 of the present invention.

Fig. 6 is a sectional view showing a manufacturing process of a semiconductor device according to embodiment 3.

Fig. 7 is a sectional view of a semiconductor device according to embodiment 4 of the present invention.

Fig. 8 is a sectional view showing a manufacturing process of a semiconductor device according to embodiment 4.

Fig. 9 is a sectional view of a semiconductor device according to embodiment 5 of the present invention.

Fig. 10 is a sectional view showing a manufacturing process of a semiconductor device according to embodiment 5.

Fig. 11 is a sectional view of a semiconductor device in which a part of embodiment 3 and a part of embodiment 5 are combined.

Fig. 12 is a sectional view of the semiconductor device after applying embodiment 1 to an SOI substrate.

Fig. 13 is a sectional view of a conventional semiconductor device.

Detailed Description

Before describing the embodiments of the present invention, in order to facilitate understanding of the embodiments, a problem of hot carrier (hot carrier) degradation in a semiconductor device having an STI insulating film in a drain drift region, which is found by the inventors, will be described.

Fig. 13 is a cross-sectional view of an N-channel LDMOSFET, which is a conventional semiconductor device 8. The semiconductor device 8 includes an N-type drain region 84 and a source region 85 formed on a P-type semiconductor substrate 80, a P-type body region 86, a gate insulating film 82, a gate electrode 83, and an STI insulating film 81. The drain region 84 is composed of a high-concentration drain region 84a and a 1 st drain drift region 84b, and the STI insulating film 81 is formed on the 1 st drain drift region 84 b.

The 1 st drain drift region 84b covers the 1 st trench side surface 81c, the 2 nd trench side surface 81d, the trench bottom surface 81e, the 1 st corner 81a, and the 2 nd corner 81b, and contacts a part of the body region 86. During the on operation of the semiconductor device 8, electrons flowing from the source region 85 toward the high-concentration drain region 84a along the channel formed on the surface of the body region 86 travel while diffusing in the depth direction in the 1 st drain drift region 84b as indicated by the paths a, b, c, and d indicated by the broken-line arrows.

For example, a part of the electrons flowing into the 1 st drain drift region 84b curvedly travels along the surfaces of the 1 st trench side surface 81c and the trench bottom surface 81e while linearly traveling in the lateral direction along the path a indicated by the broken-line arrow to reach the 1 st trench side surface 81 c. The degree of this curved progression decreases as the direction of the channel flow into the 1 st drain drift region 84b moves away from the surface of the semiconductor substrate 80 as indicated by the paths b, c, d indicated by the dashed arrows. However, any electron traveling through the paths a, b, c, and d passes through the vicinity of the 1 st corner 81a, and therefore the density of the drain current flowing therethrough increases. When passing through the vicinity of the 1 st corner 81a, these electrons travel toward the high-concentration drain region 84a while diffusing in the depth direction in the 1 st drain drift region 84b, and therefore the drain current density decreases.

Here, when a high voltage is applied to the drain and the depletion layer spreads from the boundary with the channel into the 1 st drain drift region 84b, hot carriers having high energy are easily generated in the vicinity of the 1 st corner 81a due to the drain electric field in the depletion layer and the increased drain current density. The hot carriers generate secondary carriers due to their energy when colliding with the lattice existing in the current path. When the secondary carriers are trapped in the gate insulating film, the potential distribution of the semiconductor substrate in the vicinity of the channel changes, and the potential distribution changes to cause characteristic deterioration such as variation in threshold voltage or channel mobility (channel mobility). When the secondary carriers are trapped in the insulating film on the 1 st drain drift region 84b, the potential distribution of the semiconductor substrate in the vicinity thereof changes, and this change in potential distribution causes deterioration in characteristics such as variation in drain current.

Such degradation of the characteristics due to hot carriers impairs the long-term reliability of the semiconductor device. The present invention has been devised based on such findings to suppress hot carrier degradation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings as appropriate. Here, an N-channel LDMOSFET will be described as an example of a semiconductor device. In the drawings used in the following description, some of the drawings may be omitted or enlarged to facilitate understanding of the features of the present invention, and the dimensional ratio may be different from the actual dimensional ratio.

(embodiment 1)

The semiconductor device and the method for manufacturing the same according to embodiment 1 will be described below.

Fig. 1 is a sectional view showing a semiconductor device 1 according to embodiment 1 of the present invention.

The semiconductor device 1 of embodiment 1 is formed on a semiconductor substrate 10 such as P-type silicon, and includes: a drain region 14 and a source region 15 of N-type, a body region 16 of P-type formed between the drain region 14 and the source region 15, a body contact region 17 of P-type formed on the body region 16, and a gate insulating film 12 and a gate electrode 13. The drain region 14 includes a high concentration drain region 14a, a 1 st drain drift region 14b, and a 2 nd drain drift region 14 c. In addition, a trench 111 is provided in the drain region 14, and an STI insulating film 11 (thick film insulating film) having a film thickness thicker than the gate insulating film 12 is formed in the trench 111. Next, the constituent elements of the semiconductor device 1 according to embodiment 1 will be described.

The STI insulating film 11 is formed of an insulating film such as a silicon oxide (silicon oxide) film thicker than the gate insulating film 12, and is the same film as an element isolation film used in a CMOS logic circuit integrated at the same time. The STI insulating film 11 is an insulating film buried in the trench 111 formed in the semiconductor substrate 10, and is surrounded by a 1 st trench side surface 11c facing the body region 16, a trench bottom surface 11e, and a 2 nd trench side surface 11d facing the high-concentration drain region 14a in cross section. A1 st corner 11a is provided at an intersection where the 1 st trench side surface 11c and the trench bottom surface 11e meet, and a 2 nd corner 11b is provided at an intersection where the 2 nd trench side surface 11d and the trench bottom surface 11e meet. The 1 st corner 11a and the 2 nd corner 11b also depend on the conditions of the trench etching, but have an internal angle of about 90 degrees to 110 degrees. The angle is sharper than the corner of the same position of the LOCOS insulating film.

The high-concentration drain region 14a is formed in a region of the 1 st drain drift region 14b distant from the body region 16, the 1 st trench side surface 11c, and the trench bottom surface 11e, and is connected to a drain electrode wiring (not shown) to which a drain voltage is applied. The high-concentration drain region 14a is formed of 1 × 10 to obtain ohmic contact with the drain electrode wiring²⁰/cm³The above N-type impurity having a high impurity concentration.

The 1 st drain drift region 14b is formed so as to contact the body region 16, the 1 st trench side surface 11c, and a part of the trench bottom surface 11e including the 1 st corner 11 a. The 1 st drain drift region 14b is formed of an N-type impurity having an impurity concentration lower than that of the body region 16 so as to resist PN junction breakdown with the body region 16 against application of a high drain voltage. The depth and impurity concentration of the 1 st drain drift region 14b are adjusted so that the depletion layer extending in the upward direction on the 1 st drain drift region 14b side, which occurs between the 1 st drain drift region 14b and the P-type semiconductor substrate 10 below when the drain voltage is applied, reaches the trench bottom surface 11 e. Accordingly, a RESURF (Reduced Surface Field) effect is obtained in which extension of the lateral depletion layer expanding from the boundary with the body region 16 into the 1 st drain drift region 14b at the time of drain voltage application is promoted to relax the drain electric Field. The P-type region below the 1 st drain drift region 14b for obtaining the RESURF effect may be a P-type diffusion region formed in the semiconductor substrate 10.

The 2 nd drain drift region 14c is formed in a region of the 1 st drain drift region 14b away from the body region 16, and is formed of an N-type impurity having a higher impurity concentration than the 1 st drain drift region 14 b. The distance between the 2 nd drain drift region 14c and the body region 16 is set in consideration of the extension of the depletion layer and the like so as not to impair the required drain withstand voltage. Further, the distance x is set from the 1 st corner 11a₁The 1 st position 11f of (3) extends in the direction of the 2 nd corner 11b and forms the 2 nd drain drift region 14c so as to contact the trench bottom surface 11 e.

The impurity concentration of the 1 st drain drift region 14b is set low in order to relax the drain electric field in the drain current concentration portion generated in the vicinity of the 1 st corner 11 a. Further, the impurity concentration of the 2 nd drain drift region 14c is made higher than that of the 1 st drain drift region 14b, thereby reducing the drain resistance.

The gate electrode 13 is an electrode for controlling formation of a channel on the surface of the body region 16 via the gate insulating film 12, and is connected to a gate metal wiring (not shown). The gate electrode 13 is formed over the semiconductor substrate 10 including the body region 16 and over the STI insulating film 11.

A source region 15 formed in the body region 16 and to which a source voltage is appliedThe source electrode wiring (not shown) is connected. The source region 15 is formed of 1 × 10 lines to obtain ohmic contact with the source electrode wiring²⁰/cm³The above N-type impurity having a high impurity concentration.

The body region 16 is a P-type impurity region for forming a channel on the surface of the semiconductor substrate 10, and a body voltage is supplied from a body electrode wiring through a body contact region 17 including a high concentration of P-type impurities. In general, the body voltage and the source voltage are often equal, and in this case, the body contact region 17 and the source region are formed adjacent to each other, and the source electrode wiring is connected to them all together.

In embodiment 1, the concentration of the drain current in the vicinity of the 1 st corner 11a occurs in the same manner as in the conventional case. However, since the impurity concentration of the 1 st drain drift region 14b is reduced as compared with the conventional art, the electric field in the depletion layer generated by the application of the drain voltage at the 1 st corner 11a is weakened as compared with the conventional art. Therefore, generation of hot carriers and hot carrier degradation at the 1 st corner 11a are suppressed.

On the other hand, at a distance x from the 1 st corner 11a₁The 2 nd drain drift region 14c having a higher impurity concentration than the 1 st drain drift region 14b is formed so as to extend in the direction of the 2 nd corner 11b from the 1 st position 11 f. Therefore, an increase in drain resistance accompanying a decrease in impurity concentration of the 1 st drain drift region 14b is suppressed.

By doing so, embodiment 1 achieves an increase in the withstand voltage of the drain voltage due to a decrease in the concentration of the 1 st drain drift region 14b, a decrease in the on-resistance due to a decrease in the drain resistance due to the structure of the 2 nd drain drift region 14c, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

next, a method for manufacturing the semiconductor device 1 according ~ embodiment 1 will be described mainly with reference ~ characteristic steps (a) ~ (c) of fig. 2.

first, as shown in fig. 2 a, an N-type 1 st drain drift region 14b is formed by ion implantation and thermal diffusion of an N-type impurity from the surface of a P-type semiconductor substrate 10, a mask insulating film is deposited, a mask insulating film opening is formed by etching the mask insulating film ~ expose (not shown) the surface of the semiconductor substrate 10, then, etching is performed from the surface of the semiconductor substrate 10 ~ a depth not exceeding the 1 st drain drift region 14b using the mask insulating film as a mask ~ form a trench 111, then, an insulating film such as a silicon oxide film is deposited thereon, and planarization is performed by a CMP (chemical mechanical Polishing) method or the like ~ form an STI insulating film 11 in the trench 111. the STI insulating film 11 is surrounded by the 1 st trench side surface 11c, the 2 nd trench side surface 11d, the trench bottom surface 11e, and the 1 st corner 11a and the 2 nd corner 11b formed at the intersection of those surfaces, and has a thickness of about 350 ~ 450nm larger than the thickness of a gate insulating film ~ be formed later.

next, as shown in fig. 2 (b), a resist (resist) 18 is applied to the surface of the semiconductor substrate 10, and patterned by photolithography, and then, the substrate is separated from the 1 st corner 11a by a distance x₁The 2 nd drain drift region 14c in the direction from the 1 st position 11f toward the 2 nd corner 11b forms a resist opening. The resist 18 is patterned by aligning the alignment mark (alignment mark) formed in the same layer as the STI insulating film 11. By doing so, the distance x between the 1 st corner 11a and the 2 nd drain drift region 14c is suppressed₁Is offset. Next, N-type impurities having a higher concentration than that of the 1 st drain drift region 14b are ion-implanted using the resist 18 as a mask, thereby forming a 2 nd drain drift region 14 c. At this time, high ion implantation energy is selected for the formation of the 2 nd drain drift region 14c below the trench bottom surface 11e and not beyond the depth of the 1 st drain drift region 14 b. Thus, with regard to resist 18, the thickness against which energy is also selected. According to the above, the 2 nd drain drift region 14c is formed at the distance x from the 1 st corner 11a₁And includes a region where the high-concentration drain region 14a forms a predetermined region, and the 1 st position 11f of (1) is directed toward the 2 nd corner portion 11 b.

Next, as shown in fig. 2 (c), the P-type body region 16, the gate insulating film 12, and the gate electrode 13 are formed. The formation of the body region 16 may be performed by implanting P-type impurities into the gate electrode 13 as a mask by self-alignment after the formation of the gate electrode 13, and then performing thermal diffusion.

Thereafter, the N-type high concentration drain region 14a and the source region 15 are formed, and the P-type body contact region 17 is formed, thereby completing the semiconductor device 1 shown in fig. 1.

By adopting the manufacturing method as described above, the distance x between the 1 st corner 11a and the 1 st position 11f can be reduced₁And a variation in suppression effect of hot carrier deterioration is reduced.

(embodiment 2)

The semiconductor device and the method for manufacturing the same according to embodiment 2 will be described below.

Fig. 3 is a sectional view showing semiconductor device 2 according to embodiment 2 of the present invention.

The semiconductor device 2 according to embodiment 2 is formed on a semiconductor substrate 20 such as P-type silicon, and includes: an N-type drain region 24 and source region 25, a P-type body region 26 formed between the drain region 24 and source region 25, a P-type body contact region 27 formed on the body region 26, a gate insulating film 22, and a gate electrode 23. The drain region 24 includes a high concentration drain region 24a, a 1 st drain drift region 24b, and a 2 nd drain drift region 24 c. Further, a trench 211 is provided in the drain region 24, and the STI insulating film 21 having a film thickness thicker than the gate insulating film 22 is formed in the trench 211. In embodiment 2, the sidewall insulating film 29 is formed so as to contact both side surfaces of the gate electrode 23 on the STI insulating film 21. Hereinafter, embodiment 2 will be described centering on the features of embodiment 1.

The 2 nd drain drift region 24c is formed by an N-type impurity having a higher impurity concentration than the 1 st drain drift region 24b in a region of the body region 26 within the 1 st drain drift region 24 b. The distance between the 2 nd drain drift region 24c and the body region 26 is set in consideration of the extension of the depletion layer and the like so as not to impair the required drain withstand voltage. Furthermore, in order to relax the drain electric field at the 1 st corner 21a, the drain electric field is set to be away from the 1 st corner1 corner 21a distance x₂The 1 st position 21f of (3) extends in the direction of the 2 nd corner 21b and forms the 2 nd drain drift region 24c so as to contact the trench bottom surface 21 e. Further, the drain resistance is reduced by making the impurity concentration of the 2 nd drain drift region 24c higher than that of the 1 st drain drift region 24 b.

The sidewall insulating film 29 is formed so as to contact both side surfaces of the gate electrode 23. Here, a sidewall insulating film 29 provided so as to be in contact with a side surface facing the high-concentration drain region 24a is formed on the STI insulating film 21. The position of the end of the sidewall insulating film 29 facing the high-concentration drain region 24a is substantially the same as the 1 st position 21f in a plan view. In embodiment 2, the sidewall insulating film 29 functions as a mask in ion implantation for forming the 2 nd drain drift region 24 c.

In embodiment 2, the concentration of the drain current in the vicinity of the 1 st corner 21a also occurs in the same manner as in the conventional case. However, since the impurity concentration of the 1 st drain drift region 24b is reduced compared to the conventional one, the generation of hot carriers and the degradation of hot carriers are suppressed. Furthermore, at a distance x from the 1 st corner 21a₂the 1 st position 21f of (2) is formed with a 2 nd drain drift region 24c having a higher impurity concentration than the 1 st drain drift region 24b so as to extend in the direction of the 2 nd corner 21 b. Therefore, an increase in drain resistance accompanying a decrease in impurity concentration of the 1 st drain drift region 24b is suppressed.

By doing so, embodiment 2 achieves a higher withstand voltage of the drain voltage due to a lower concentration of the 1 st drain drift region 24b, a reduction in the drain resistance due to the structure of the 2 nd drain drift region 24c, a reduction in the on-resistance, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

next, a method for manufacturing the semiconductor device 2 according ~ embodiment 2 will be described with reference ~ fig. 4 (a) ~ (c) and centering on characteristic steps.

first, as shown in fig. 4a, the N-type 1 st drain drift region 24b is formed by ion implantation and thermal diffusion of N-type impurities from the surface of the P-type semiconductor substrate 20, then, a mask insulating film is deposited, a mask insulating film opening is formed by etching the mask insulating film to expose (not shown) the surface of the semiconductor substrate 20, then, the mask insulating film is used as a mask to etch from the surface of the semiconductor substrate 20 to a depth not exceeding the 1 st drain drift region 24b to form the trench 211, then, an insulating film such as a silicon oxide film is deposited thereon, and planarization is performed by a CMP method or the like, thereby forming the STI insulating film 21 in the trench 211, the STI insulating film 21 is surrounded by the 1 st trench side surface 21c, the 2 nd trench side surface 21d, and the trench bottom surface 21e, and the 1 st corner portion 21a and the 2 nd corner portion 21b formed at the intersection of those surfaces, and the thickness thereof is about 350 to 450nm thicker than the gate insulating film formed thereafter, and this step is similar to embodiment 1.

Next, as shown in fig. 4 (b), a body region 26, a gate insulating film 22, a gate electrode 23, a high concentration drain region 24a, a source region 25, and a body contact region 27 are formed. Thereafter, an insulating film such as a silicon oxide film is deposited on the gate electrode 23, and an etch back (etch back) is performed under an anisotropic dry etching condition, thereby forming the sidewall insulating film 29 so as to be in contact with both side surfaces of the gate electrode 23. The formation of the body region 26 may be performed by implanting P-type impurities into the gate electrode 23 as a mask after forming the gate insulating film 22 and the gate electrode 23, and then performing thermal diffusion. By performing the patterning of the gate electrode 23 by performing the position alignment of the alignment mark formed in the same layer as the STI insulating film 21, the positional alignment deviation between the 1 st corner portion 21a and the end portion of the gate electrode 23 on the high-concentration drain region 24a side is suppressed. Similarly, the distance x between the 1 st corner 21a and the end of the sidewall insulating film 29 formed on the side surface of the gate electrode 23 on the high-concentration drain region 24a side is also reduced₂The deviation of (2).

Next, as shown in fig. 4 (c), a resist 28 is applied to the surface of the semiconductor substrate 20, and a resist opening is formed in a region including the 2 nd drain drift region 24c where a predetermined region is to be formed by photolithography. A resist opening is formed at an arbitrary position on the sidewall insulating film 29 on the side of the gate electrode 23 facing the high-concentration drain region 24aThe location of the boundary. Next, N-type impurities having a higher concentration than that of the 1 st drain drift region 24b are ion-implanted using the resist 28 and the sidewall insulating film 29 as masks, thereby forming a 2 nd drain drift region 24 c. At this time, high ion implantation energy is selected so that the 2 nd drain drift region 24c can be formed below the trench bottom surface 21e without exceeding the depth of the 1 st drain drift region 24 b. According to the above, the 2 nd drain drift region 24c is formed at the distance x from the 1 st corner 21a₂And includes a region where the high-concentration drain region 24a forms a predetermined region, and the 1 st position 21f of (1) is directed toward the 2 nd corner portion 21 b.

After that, the resist 28 is stripped, and the semiconductor device 2 shown in fig. 3 is completed.

By adopting the manufacturing method as described above, the distance x between the 1 st corner 21a and the 1 st position 21f can be reduced₂The deviation of (2). When the distance x is resolved₂In the case of the variation of (2), first, the 1 st variation component is a positional alignment variation between the trench 211 and the 2 nd drain drift region. This 1 st misalignment component is equivalent to the misalignment of the trench 111 and the resist 18 in embodiment 1. The 2 nd deviation component is a finished deviation of the ion implantation mask boundary when the 2 nd drain drift region is formed by ion implantation, but the effect of reducing this deviation is high in embodiment 2.

The boundary of the ion implantation mask used in embodiment 2 is the end portion of the sidewall insulating film 29 formed self-aligned on the basis of the gate electrode 23 formed with a thin resist. It is generally assumed that: the thicker the resist used for patterning, the more susceptible it is to the influence of the pattern density or the variation of the taper angle (taper angle) of the pattern boundary, and the larger the completion variation of the pattern boundary. Therefore, the end portion of the sidewall insulating film 29 formed by self-alignment based on the gate electrode 23 formed with a thin resist can have less finish variation than the boundary finish variation of a thick resist.

By adopting the manufacturing method as described above, the distance x between the 1 st corner 21a and the 1 st position 21f can be reduced₂And a deviation of the suppression effect of the hot carrier deterioration is reducedThe semiconductor device of (1).

(embodiment 3)

The semiconductor device and the method for manufacturing the same according to embodiment 3 will be described below.

fig. 5 is a sectional view showing semiconductor device 3 according to embodiment 3 of the present invention.

The semiconductor device 3 of embodiment 3 is formed on a semiconductor substrate 30 such as P-type silicon, and includes: an N-type drain region 34 and source region 35, a P-type body region 36 formed between the drain region 34 and source region 35, a P-type body contact region 37 formed on the body region 36, a gate insulating film 32, and a gate electrode 33. The drain region 34 includes a surface drain drift region 34d in addition to the high concentration drain region 34a, the 1 st drain drift region 34b, and the 2 nd drain drift region 34 c. A trench 311 is provided in the drain region 34, and an STI insulating film 31 having a film thickness thicker than the gate insulating film 32 is formed in the trench 311. Hereinafter, embodiment 3 will be described centering on the features of embodiment 1.

The surface drain drift region 34d is formed in a region which is in contact with the 1 st trench side surface 31c and is located below the gate insulating film 32 to a depth shallower than the 1 st corner 31 a. The surface drain drift region 34d is formed of an N-type impurity having a higher impurity concentration than the 1 st drain drift region 34 b.

The side surface of the gate electrode 33 facing the high-concentration drain region 34a is set at a position slightly overlapping the STI insulating film 31. This position is a position slightly overlapping to the extent that the surface drain drift region 34d can be formed by ion implantation through the side surface of the gate electrode 33 from the vertical direction at an inclination angle of 15 degrees or more.

In embodiment 3, a surface drain drift region 34d is provided to reduce the drain resistance. In this region, the drain electric field is relatively high, but the drain current density is not high, and therefore, it is difficult to generate hot carriers. The current flowing in this portion flows in a meandering manner as shown by a path a in fig. 13, and therefore the equivalent resistance increases. Thus, in embodiment 3, the table is setThe planar drain drift region 34d reduces the drain resistance. Further, similarly to embodiment 1, the distance x is set from the 1 st corner 31a₃The 2 nd drain drift region 34c having a higher impurity concentration than the 1 st drain drift region 34b is formed so as to extend toward the high-concentration drain region 34a from the 1 st position 31 f.

Therefore, embodiment 3 achieves a higher withstand voltage of the drain voltage due to a lower concentration of the 1 st drain drift region 34b, a reduction in the drain resistance due to the structures of the surface drain drift region 34d and the 2 nd drain drift region 34c, a reduction in the on-resistance, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

next, a method for manufacturing a semiconductor device 3 according ~ embodiment 3 will be described with reference ~ fig. 6 (a) ~ (c) and centering on characteristic steps.

first, as shown in fig. 6 a, the N-type 1 st drain drift region 34b is formed by ion implantation and thermal diffusion of N-type impurities from the surface of the P-type semiconductor substrate 30, then, a mask insulating film is deposited, a mask insulating film opening is formed by etching the mask insulating film to expose (not shown) the surface of the semiconductor substrate 30, then, the mask insulating film is used as a mask to etch from the surface of the semiconductor substrate 30 to a depth not exceeding the 1 st drain drift region 34b to form the trench 311, then, an insulating film such as a silicon oxide film is deposited thereon, and planarization is performed by a CMP method or the like, thereby forming the STI insulating film 31 in the trench 311, the STI insulating film 31 is surrounded by the 1 st trench side surface 31c, the 2 nd trench side surface 31d, the trench bottom surface 31e, and the 1 st corner 31a, the 2 nd corner 31b formed at the intersection of those surfaces, and has a thickness of about 350 to 450nm larger than the gate insulating film to be formed thereafter, and this step is similar to embodiment 1.

next, as shown in fig. 6 (b), a resist 38 is applied to the surface of the semiconductor substrate 30, and a resist opening is formed in a predetermined region in the 2 nd drain drift region 34c by photolithography. The resist 38 is patterned by aligning the alignment mark formed in the same layer as the STI insulating film 31. Thus, the 1 st corner part is suppressed31a and 1 st position 31f₃So that the distance x can be set within a range where the 2 nd drain drift region 34c does not contact the 1 st corner 31a₃Becomes shorter. By making the distance x₃Becomes shorter to reduce the drain resistance. Next, N-type impurities having a higher concentration than that of the 1 st drain drift region 34b are ion-implanted using the resist 38 as a mask, thereby forming a 2 nd drain drift region 34 c. At this time, high ion implantation energy is selected for the 2 nd drain drift region 34c to be formed below the trench bottom surface 31e and not to exceed the depth of the 1 st drain drift region 34 b. According to the above, the 2 nd drain drift region 34c is formed at the distance x from the 1 st corner 31a₃and includes a region where the high-concentration drain region 34a forms a predetermined region, and the 1 st position 31f of (1) is directed toward the 2 nd corner portion 31 b.

Next, as shown in fig. 6 (c), after the resist 38 is stripped, the P-type body region 36, the gate insulating film 32, and the gate electrode 33 are formed. The formation of the body region 36 may be performed by implanting P-type impurities into the gate electrode 33 as a mask by self-alignment after the formation of the gate electrode 33, and then performing thermal diffusion.

Next, a resist 38 is applied to the surface of the semiconductor substrate 30, and a resist opening is formed in a region to be ion-implanted for forming the surface drain drift region 34d by photolithography. The boundary position of the resist opening is set to an arbitrary position where the end portion of the gate electrode 33 on the side where the high-concentration drain region 34a is to be formed is exposed. Next, using the resist 38 and the gate electrode 33 as masks, N-type impurities having a higher concentration than that of the 1 st drain drift region 34b are ion-implanted so as to be inclined at an angle of 15 degrees or more, thereby forming a surface drain drift region 34 d.

Thereafter, the N-type high concentration drain region 34a and the source region 35 are formed, and the P-type body contact region 37 is formed, thereby completing the semiconductor device 3 shown in fig. 5.

By adopting the manufacturing method as described above, the surface drain drift region 34d can be formed so as to be self-adjustable with respect to the position of the trench 311, and therefore, the drain resistance in this region can be reduced and variations in drain resistance can be suppressed. Therefore, the on-resistance can be stably reduced while suppressing hot carrier deterioration by the formation of the 2 nd drain drift region 34c and the surface drain drift region 34 d.

(embodiment 4)

The semiconductor device and the method for manufacturing the same according to embodiment 4 will be described below.

Fig. 7 is a sectional view showing semiconductor device 4 according to embodiment 4 of the present invention.

The semiconductor device 4 of embodiment 4 is formed on a semiconductor substrate 40 such as P-type silicon, and includes: an N-type drain region 44 and a source region 45, a P-type body region 46 formed between the drain region 44 and the source region 45, a P-type body contact region 47 formed on the body region 46, a gate insulating film 42, and a gate electrode 43. The drain region 44 includes a high concentration drain region 44a, a 1 st drain drift region 44b, a 2 nd drain drift region 44c, and a 3 rd drain drift region 44 d. Further, a trench 411 is provided in the drain region 44, and the STI insulating film 41 having a film thickness thicker than the gate insulating film 42 is formed in the trench 411. Hereinafter, embodiment 4 will be described centering on the features of embodiment 1.

The 2 nd drain drift region 44c is formed in a region of the 1 st drain drift region 44b away from the body region 46, and is formed of an N-type impurity having a higher impurity concentration than the 1 st drain drift region 44 b. The distance between the 2 nd drain drift region 44c and the body region 46 is set in consideration of the extension of the depletion layer and the like so as not to impair the required drain withstand voltage. Furthermore, in order to relax the drain electric field in the drain current concentration portion generated in the vicinity of the 1 st corner portion 41a, the distance x is set to be greater than the 1 st corner portion 41a₄The 1 st position 41f of (3) extends in the direction of the 2 nd corner 41b and forms the 2 nd drain drift region 44c so as to contact the trench bottom surface 41 e.

A 3 rd drain drift region 44d is formed in a region which is in contact with the 2 nd drain drift region 44c in the 1 st drain drift region 44b and includes the high-concentration drain region 44a and the 2 nd corner portion 41b in a plan view. Further, the 3 rd drain drift region 44d is composed of N-type impurities having higher impurity concentration than the 1 st drain drift region 44b and the 2 nd drain drift region 44 c.

In the semiconductor device 4 according to embodiment 4, the drain resistance is reduced by providing the 3 rd drain drift region 44d having a high impurity concentration in addition to the 2 nd drain drift region 44 c. By applying a voltage to the drain, the electric field is highest at the boundary with the body region 46 in the electric field distribution in the depletion layer extending from the boundary into the 1 st drain drift region 44b, and the electric field decreases as the distance from the boundary increases. Therefore, the electric field at the position of the 2 nd drain drift region 44c where the impurity concentration is increased as compared with the 1 st drain drift region 44b and the electric field at the boundary position of the body region 46 can be decreased by an amount. Similarly, in the 3 rd drain drift region 44d further away from the boundary with the body region 46, the impurity concentration can be increased as compared with the 2 nd drain drift region 44c, whereby the drain resistance can be reduced.

That is, with the configuration as shown in fig. 7, embodiment 4 achieves a higher withstand voltage of the drain voltage due to a lower concentration of the 1 st drain drift region 44b, a reduction in the drain resistance due to the structures of the 2 nd drain drift region 44c and the 3 rd drain drift region 44d, a reduction in the on-resistance, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

next, a method for manufacturing a semiconductor device 4 according ~ embodiment 4 will be described with reference ~ fig. 8 (a) ~ (c) and centering on characteristic steps.

First, as shown in fig. 8 (a), the 1 st drain drift region 44b of the N type is formed by ion implantation and thermal diffusion of an N type impurity from the surface of the P type semiconductor substrate 40. Next, a mask insulating film 412 for forming a trench 411 in the semiconductor substrate 40 is formed on the semiconductor substrate 40. As the mask insulating film 412, a film which can resist trench etching to be performed next is used. For this purpose, the mask insulating film 412 may be a laminated film of a silicon oxide film and a silicon nitride film, for example. Next, after an opening is formed by etching the mask insulating film 412 in a region where the trench 411 is to be formed, the semiconductor substrate 40 is processed by anisotropic dry etching using the mask insulating film 412 as a mask, and the trench 411 is formed below the opening. The anisotropic dry Etching method is a technique for Etching along the opening of the mask insulating film 412 in a substantially vertical direction, and for example, a RIE (Reactive Ion Etching) method is known. In this etching process, the adhesion of the secondary product to the trench side surface also occurs at the same time, and therefore, as shown in fig. 8 (a), the 1 st trench side surface 41c and the 2 nd trench side surface 41d are frequently formed in a forward tapered shape. However, lateral etching in which the positions of the 1 st trench side surface 41c and the 2 nd trench side surface 41d spread outside the opening of the mask insulating film 412 is suppressed.

Next, as shown in fig. 8 (b), additional etching is further performed from the state of fig. 8 (a), and the etching of the trench is advanced so as to spread laterally outward from the end of the opening of the mask insulating film 412 simultaneously with the deepening of the trench 411. This etching is performed to spread the 1 st corner portion 41a and the 2 nd corner portion 41b outside the opening of the mask insulating film 412 in a plan view. For the Etching at this time, isotropic Dry Etching conditions known in a CDE (Chemical Dry Etching) method and the like are used. By performing the above additional etching, the trench 411 having the 1 st corner portion 41a, the 2 nd corner portion 41b, the 1 st trench side surface 41c, the 2 nd trench side surface 41d, and the trench bottom surface 41e is formed.

next, as shown in fig. 8 (c), N-type impurities are ion-implanted into the trench bottom surface 41e in the vertical direction indicated by the solid arrow using the mask insulating film 412 as a mask, thereby forming the 2 nd drain drift region 44 c. At this time, since the 1 st corner 41a and the 2 nd corner 41b are enlarged as compared with the opening of the mask insulating film 412, the 2 nd drain drift region 44c is separated from the 1 st corner 41a and the 2 nd corner 41b by a distance x₄Is formed between the inner 1 st position 41f and the 2 nd position 41 g. Note that, from the state of fig. 8 (c), in order to reduce the N-type impurity concentration in the 1 st drain drift region 44b in the vicinity of the 1 st corner 41a, the 2 nd corner 41b, the 1 st trench side surface 41c, and the 2 nd trench side surface 41d, P-type impurities may be ion-implanted from the vertical direction at an inclination angle of 15 degrees or more as necessary (not shown in the figure)Shown). The N-type impurity is controlled to be less than the N-type impurity of the 2 nd drain drift region 44c so as not to affect the impurity concentration of the 2 nd drain drift region 44 c.

After that, the mask insulating film 412 is peeled off, an insulating film such as a silicon oxide film is deposited, and planarization is performed by a CMP method or the like, thereby forming the STI insulating film 41 in the trench 411. Next, similarly to fig. 2 b, a resist is applied to the surface of the semiconductor substrate 40, a resist opening is formed in a predetermined region in the 3 rd drain drift region including the 2 nd corner 41b and the 2 nd position 41g by photolithography, and an N-type impurity (not shown) is ion-implanted into the resist opening. At this time, high ion implantation energy is selected for the 3 rd drain drift region 44d to be formed below the trench bottom surface 41e and not to exceed the depth of the 1 st drain drift region 44 b. Then, N-type impurities having a higher impurity concentration than the 2 nd drain drift region 44c are implanted to form a 3 rd drain drift region 44 d. Then, the semiconductor device 4 shown in fig. 7 is completed through formation of the gate insulating film 42, formation of the gate electrode 43, formation of the body region 46, formation of the high-concentration drain region 44a or the source region 45, and the like.

In the method of manufacturing the semiconductor device according to embodiment 4, since additional etching or N-type impurity implantation is performed without using a photolithography technique using the mask insulating film 412, the 2 nd drain drift region 44c can be formed in a self-adjusting manner with respect to the shape of the trench 411. Therefore, the distance x in fig. 7 can be reduced₄The variation in the suppression effect of the hot carrier deterioration is reduced.

In embodiment 4, N-type impurity implantation for forming the 2 nd drain drift region 44c is performed on the trench bottom surface 41e before the STI insulating film 41 is formed. Therefore, it is possible to achieve a reduction in the spread of the implantation range caused by the ion implantation at low energy and a reduction in the variation in the implantation depth based on the variation in the thickness of the STI insulating film 41. Therefore, a stable reduction in drain resistance can be achieved.

(embodiment 5)

Fig. 9 is a sectional view showing a semiconductor device 5 according to embodiment 5 of the present invention.

The semiconductor device 5 of embodiment 5 is formed on a semiconductor substrate 50 such as P-type silicon, and includes: an N-type drain region 54 and source region 55, a P-type body region 56 formed between the drain region 54 and source region 55, a P-type body contact region 57 formed on the body region 56, a gate insulating film 52, and a gate electrode 53. The drain region 54 includes a high concentration drain region 54a, a 1 st drain drift region 54b, a 2 nd drain drift region 54c, and a 3 rd drain drift region 54 d. A trench 511 is formed in the drain region 54, and an STI insulating film 51 having a film thickness thicker than the gate insulating film 52 is formed in the trench 511. Further, in embodiment 5, a sidewall insulating film 59 is formed outside the STI insulating film 51 in the trench 511 so as to be in contact with the 1 st trench side surface 51c and the 2 nd trench side surface 51d, respectively. Hereinafter, embodiment 5 will be described centering on the features of embodiment 1.

The 2 nd drain drift region 54c is formed in a region apart from the body region 56 in the 1 st drain drift region 54b, and is formed of an N-type impurity having a higher impurity concentration than the 1 st drain drift region 54 b. Furthermore, in order to relax the drain electric field in the drain current concentration portion generated in the vicinity of the 1 st corner 51a, the distance x is set to be greater than the 1 st corner 51a₅The 1 st position 51f of (3) extends in the direction of the 2 nd corner 51b and forms the 2 nd drain drift region 54c so as to contact the trench bottom surface 51 e.

The sidewall insulating film 59 is formed on the trench bottom surface 51e between the 1 st corner 51a and the 1 st position 51f and between the 2 nd corner 51b and the 2 nd position 51g so as to contact the 1 st trench side surface 51c and the 2 nd trench side surface 51d, respectively. The STI insulating film 51 is formed in the trench 511 so as to be in contact with the sidewall insulating film 59.

A 3 rd drain drift region 54d is formed in the 1 st drain drift region 54b adjacent to the 2 nd drain drift region 54c and in a region including the high concentration drain region 54a, the 2 nd corner 51b, and the 2 nd position 51g in a plan view. Further, the 3 rd drain drift region 54d is composed of N-type impurities having higher impurity concentration than the 1 st drain drift region 54b and the 2 nd drain drift region 54 c.

in embodiment 5, the 2 nd drain drift region 54c is separated from the 1 st corner 51a by a distance x, as in embodiment 4₅By extending the 1 st position 51f in the direction of the 2 nd corner 51b, the drain electric field in the vicinity of the 1 st corner 51a is relaxed, and hot carrier degradation is suppressed. Therefore, embodiment 5 achieves a higher withstand voltage of the drain voltage due to a lower concentration of the 1 st drain drift region 54b, a reduction in the drain resistance due to the structure of the 2 nd drain drift region 54c, a reduction in the on-resistance, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

in addition, in the semiconductor device 5 of embodiment 5, the 3 rd drain drift region 54d having an impurity concentration higher than that of the 2 nd drain drift region 54c is provided, thereby reducing the drain resistance. By applying a voltage to the drain, the drain electric field is highest at the boundary with the body region 56 in the electric field distribution in the depletion layer extending from the boundary into the 1 st drain drift region 54b, and the drain electric field decreases as the distance from the boundary increases. Therefore, the drain electric field at the position of the 2 nd drain drift region 54c where the impurity concentration is increased as compared with the 1 st drain drift region 54b and the electric field at the boundary position of the body region 56 can be decreased by an amount lower than each other. Similarly, in the 3 rd drain drift region 54d further away from the boundary with the body region 56, the impurity concentration can be increased as compared with the 2 nd drain drift region 54c, whereby the drain resistance can be reduced.

That is, with the configuration as shown in fig. 9, embodiment 5 achieves a higher withstand voltage of the drain voltage due to a lower concentration of the 1 st drain drift region 54b, a reduction in the drain resistance due to the structures of the 2 nd drain drift region 54c and the 3 rd drain drift region 54d, a reduction in the on-resistance, and an improvement in the long-term reliability due to suppression of hot carrier degradation.

next, a method for manufacturing a semiconductor device 5 according ~ embodiment 5 will be described with reference ~ fig. 10 (a) ~ (c) and centering on characteristic steps.

first, as shown in fig. 10 (a), the 1 st drain drift region 54b of the N type is formed by ion implantation and thermal diffusion of an N type impurity from the surface of the P type semiconductor substrate 50. Next, a mask insulating film 512 for forming a trench in the semiconductor substrate 50 is formed on the semiconductor substrate 50. As the mask insulating film 512, a film which can resist trench etching to be performed next is used. Next, after the mask insulating film 512 in the region where the trench is to be formed is etched to form an opening, the semiconductor substrate 50 is processed by anisotropic dry etching using the mask insulating film 512 as a mask, and a trench 511 is formed below the opening of the mask insulating film 512. The anisotropic dry etching method is a technique of etching along the opening of the mask insulating film 512 in a substantially vertical direction, and for example, RIE method is known. From the state of fig. 10 (a), P-type impurities (not shown) may be ion-implanted from the vertical direction at an inclination angle of 15 degrees or more as necessary in order to reduce the N-type impurity concentration in the 1 st drain drift region 54b in the vicinity of the 1 st corner 51a, the 2 nd corner 51b, the 1 st trench side 51c, and the 2 nd trench side 51 d.

Next, as shown in fig. 10 (b), an insulating film such as a silicon oxide film having a film thickness not completely filling the trench 511 is deposited in the trench 511 and on the semiconductor substrate 50. Then, by etching back under anisotropic dry etching conditions, the sidewall insulating film 59 is formed so as to contact the 1 st trench side surface 51c and the 2 nd trench side surface 51 d. In order to protect the trench bottom surface 51e from damage due to etch-back during formation of the sidewall insulating film 59, the sidewall insulating film 59 may be formed after forming the trench 511 by forming an insulating film on the trench bottom surface 51 e. The sidewall insulating film 59 has a width of a distance x on the trench bottom surface 51e₅Thus, the distance x from the 1 st corner 51a is determined₅And a distance x from the 2 nd corner 51b and the 1 st position 51f₅2 nd position 51 g. Furthermore, the distance x₅The distances from the end of the 2 nd drain drift region 54c formed later to the 1 st corner 51a and the 2 nd corner 51b are the same. The distance x can be arbitrarily adjusted by the thickness of the insulating film for forming the sidewall insulating film 59₅。

Next, as shown in fig. 10 (c), N-type impurities are ion-implanted into the trench bottom surface 51e in the vertical direction indicated by the solid arrow using the mask insulating film 512 and the sidewall insulating film 59 as masks, and a 2 nd drain drift region 54c is formed between the 1 st position 51f and the 2 nd position 51 g.

thereafter, an insulating film such as a silicon oxide film is deposited and planarized by a CMP method or the like, thereby forming the STI insulating film 51 on the inner side of the sidewall insulating film 59 in the trench 511. Next, similarly to fig. 2 b, a resist is applied to the surface of the semiconductor substrate 50, a resist opening is formed in a predetermined region in the 3 rd drain drift region including the 2 nd corner 51b and the 2 nd position 51g by photolithography, and an N-type impurity (not shown) is ion-implanted into the resist opening. At this time, high ion implantation energy is selected for the 3 rd drain drift region 54d to be formed below the trench bottom surface 51e and not to exceed the depth of the 1 st drain drift region 54 b. Then, N-type impurities having a higher impurity concentration than the 2 nd drain drift region 54c are implanted to form a 3 rd drain drift region 54 d. Then, the semiconductor device 5 shown in fig. 9 is completed through formation of the gate insulating film 52, formation of the gate electrode 53, formation of the body region 56, formation of the high-concentration drain region 54a or the source region 55, and the like.

In the method of manufacturing a semiconductor device according to embodiment 5, since the sidewall insulating film 59 to be a mask for N-type impurity implantation is formed on the 1 st trench side surface 51c and the 2 nd trench side surface 51d without using a photolithography technique, the 2 nd drain drift region 54c can be formed in a self-alignment manner with respect to the shape of the trench 511. Therefore, the distance x in fig. 9 can be reduced₅The variation in the suppression effect of the hot carrier deterioration is reduced.

In addition, as in embodiment 4, N-type impurity implantation for forming the 2 nd drain drift region 54c is performed on the trench bottom surface 51e before the STI insulating film 51 is formed. Therefore, it is possible to achieve a reduction in the spread of the implantation range caused by the ion implantation at low energy and a reduction in the variation in the implantation depth based on the variation in the thickness of the STI insulating film 51. Therefore, a stable reduction in drain resistance can be achieved.

The structures and the manufacturing methods described in the embodiments of the present invention are not limited to the respective embodiments, and can be combined as appropriate within a range not departing from the gist of the present invention.

for example, as shown in fig. 11, in a semiconductor device 6 formed on a P-type semiconductor substrate 60 and including an N-type drain region 64 and a source region 65, a P-type body region 66, a P-type body contact region 67, a gate insulating film 62, and a gate electrode 63, the features of embodiment 3 and embodiment 5 can be combined. Here, the surface drain drift region 64e described in embodiment 3 is formed so as to contact the outside of the 1 st trench side surface 61c on which the sidewall insulating film 69 is formed. Further, the 2 nd drain drift region 64c and the 3 rd drain drift region 64d described in embodiment 5 are provided under the STI insulating film 61 and under the high-concentration drain region 64 a. With this configuration, the drain resistance is reduced by the 2 nd drain drift region 64c, the 3 rd drain drift region 64d, and the surface drain drift region 64e, which have higher impurity concentrations than the 1 st drain drift region 64 b. Furthermore, at a distance x from the 1 st corner 61a₆The 2 nd drain drift region 64c is formed so as to extend toward the high concentration drain region 64a from the 1 st position 61f, whereby hot carrier degradation and variations thereof are suppressed. This can realize a high withstand voltage, a reduction in on-resistance, and an improvement in long-term reliability in the semiconductor device.

The present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention.

For example, as shown in fig. 12, in an SOI (Silicon on Insulator) substrate 70 including a P-type Silicon layer 701, an insulating layer 702, and a P-type support substrate 703, the semiconductor device shown in embodiment 1 may be mounted on the Silicon layer 701. Namely, the following semiconductor device 7: is formed on the P-type silicon layer 701, and includes: a drain region 74 and a source region 75 including an N-type high concentration drain region 74a, a 1 st drain drift region 74b, and a 2 nd drain drift region 74c, a P-type body region 76 formed between the drain region 74 and the source region 75, a gate insulating film 72, and a gate electrode 73.

With such a configuration, a drain voltage can be appliedIn this case, the depletion layer on the P-type silicon layer 701 side is extended to the insulating layer 702 below the 1 st drain drift region 74b, and further, the depletion layer is extended to the support substrate 703 side through the insulating layer 702. Then, simultaneously with the relaxation of the electric field of the N-type drain region 74 under the STI insulating film 71 by the RESURF effect, the electric field can be relaxed also in the regions of the silicon layer 701, the insulating layer 702, and the support substrate 703, and a withstand voltage of 100V or more can be obtained. On the other hand, at a distance x from the 1 st corner 71a₇The 2 nd drain drift region 74c is formed so as to extend toward the high concentration drain region 74a from the 1 st position 71f, thereby suppressing hot carrier degradation and reducing the drain resistance.

That is, in the semiconductor device 7, the high withstand voltage of the drain voltage of 100V or more, the reduction of the drain resistance due to the structure of the 2 nd drain drift region 74c, the reduction of the on resistance, and the improvement of the long-term reliability due to the suppression of the hot carrier deterioration are realized.

Description of reference numerals

10. 20, 30, 40, 50, 60, 80 semiconductor substrate

11. 21, 31, 41, 51, 61, 71, 81 STI insulating film

11a, 21a, 31a, 41a, 51a, 61a, 71a, 81a corner 1

11b, 21b, 31b, 41b, 51b, 81b, 2 nd corner

11c, 21c, 31c, 41c, 51c, 61c, 81c, 1 st groove side

11d, 21d, 31d, 41d, 51d, 81d groove side 2

11e, 21e, 31e, 41e, 51e, 81e groove bottom surface

11f, 21f, 31f, 41f, 51f, 61f, 71f position 1

41g, 51g 2 nd position

12. 22, 32, 42, 52, 62, 72, 82 gate insulating film

13. 23, 33, 43, 53, 63, 73, 83 gate electrode

14. 24, 34, 44, 54, 64, 74, 84 drain region

14a, 24a, 34a, 44a, 54a, 64a, 74a, 84a high concentration drain region

14b, 24b, 34b, 44b, 54b, 64b, 74b, 84b No. 1 drain drift region

14c, 24c, 34c, 44c, 54c, 64c, 74c 2 nd drain drift region

44d, 54d, 64d 3 rd drain drift region

34d, 64e surface drain drift region

15. 25, 35, 45, 55, 65, 75, 85 source regions

16. 26, 36, 46, 56, 66, 76, 86 body region

17. 27, 37, 47, 57, 67 body contact area

18. 28, 38 resist

29. 59, 69 side wall insulating film

111. 211, 311, 411, 511 groove

412. 512 mask insulating film

70 SOI substrate

701 silicon layer

702 insulating layer

703 supporting the substrate.