阅读说明：本技术 一种基于GaN的鳍式场效应晶体管器件及其制造方法 (GaN-based fin field effect transistor device and manufacturing method thereof ) 是由 马晓华 何皓 张鹏 张濛 吕玲 于 2019-07-30 设计创作，主要内容包括：本发明提供一种基于GaN的鳍式场效应晶体管器件及其制造方法。所述器件,包括依次设置的衬底、缓冲层、势垒层、钝化层,其中：所述势垒层上一端设置有源极、另一端设置有漏极；所述钝化层设置在所述源极和所述漏极之间的势垒层上；所述钝化层中部设置有开口；所述开口对应的势垒层区域中设置有多个凹槽；相邻凹槽之间设置有鳍片；所述钝化层上设置有T型栅极,所述T型栅极覆盖所述凹槽以及所述鳍片；所述凹槽的长度与所述T型栅极底部的长度相等；所述鳍片的厚度与所述凹槽的深度相等；所述凹槽远离所述钝化层部分的宽度大于靠近所述钝化层部分的宽度。(The invention provides a GaN-based fin field effect transistor device and a manufacturing method thereof. The device comprises a substrate, a buffer layer, a barrier layer and a passivation layer which are sequentially arranged, wherein: a source electrode is arranged at one end of the barrier layer, and a drain electrode is arranged at the other end of the barrier layer; the passivation layer is arranged on the barrier layer between the source electrode and the drain electrode; an opening is formed in the middle of the passivation layer; a plurality of grooves are formed in the region of the barrier layer corresponding to the opening; fins are arranged between the adjacent grooves; a T-shaped grid is arranged on the passivation layer and covers the groove and the fins; the length of the groove is equal to that of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove; the width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.)

1. a GaN-based FinFET device, comprising a substrate, a buffer layer, a barrier layer, and a passivation layer disposed in that order, wherein:

a source electrode is arranged at one end of the barrier layer, and a drain electrode is arranged at the other end of the barrier layer;

The passivation layer is arranged on the barrier layer between the source electrode and the drain electrode; an opening is formed in the middle of the passivation layer;

a plurality of grooves are arranged in the region of the barrier layer corresponding to the opening; fins are arranged between the adjacent grooves;

A T-shaped grid is arranged on the passivation layer and covers the groove and the fins; the length of the groove is equal to that of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove;

the width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.

2. The GaN-based FinFET device of claim 1, wherein the groove cross-section comprises a rectangular region and two isosceles triangular regions located outside a source end-proximal side and a drain end-proximal side of the rectangular region, respectively, and wherein the groove length is the distance between the vertices of the isosceles triangles.

3. The GaN-based FinFET device of claim 1, wherein a minimum distance between adjacent grooves is not less than 100 nm.

4. A method of fabricating a GaN-based finfet device, comprising:

preparing a source electrode and a drain electrode on the surface of the GaN heterojunction material;

preparing a passivation layer on the barrier layer between the source electrode and the drain electrode;

etching the passivation layer to form a rectangular opening on the passivation layer;

Photoetching and etching a plurality of grooves on the barrier layer of the GaN-based heterojunction layer according to a preset shape, and forming fins between the adjacent grooves;

preparing a T-shaped grid; the T-shaped grid electrode covers the groove and the fin;

the length of the groove is equal to the width of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove.

5. The method of claim 4, wherein the step of fabricating the source and the drain on the surface of the GaN heterojunction material comprises:

And photoetching a source-drain pattern on the plane of the GaN heterojunction material, depositing source-drain metal, and annealing in a nitrogen atmosphere to prepare a source electrode and a drain electrode.

6. the method of claim 4, wherein fabricating the passivation layer on the barrier layer between the source and drain comprises:

And growing a SiN passivation layer on the surface of the barrier layer of the heterojunction material by a PECVD (plasma enhanced chemical vapor deposition) deposition technology.

7. the method of claim 4, wherein etching the passivation layer to form a rectangular opening in the passivation layer comprises:

Forming a photoresist pattern of a fin on the surface of the passivation layer by a photoetching technology; the photoetching technology adopts fluorine-based gas as etching process gas;

and etching the passivation layer by adopting an inductively coupled plasma etching technology or a reactive ion etching technology, wherein the surface of the passivation layer without the photoresist mask is etched to form the opening.

8. The method of claim 7, wherein the step of lithographically etching a plurality of recesses in the barrier layer and the upper portion of the GaN-based heterojunction layer according to the predetermined shape to form fins between adjacent recesses comprises:

adopting Cl-based gas as etching process gas, continuously etching the barrier layer and the buffer layer of the GaN-based heterojunction layer exposed out of the opening to form grooves, and forming fin structures between the adjacent grooves;

The width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.

9. The method of claim 8, wherein the pre-processing module is specifically configured to:

etching the fin and the barrier layer at the gate position by using an inductive coupling plasma etching technology or a reactive ion etching technology to form a gate pattern and etch away a passivation layer which is not masked by the photoresist by using F-based gas as etching process gas;

and photoetching a grid pattern at the grid position, carrying out metal evaporation on the whole surface of the passivation layer, and then stripping off the photoresist to form the T-shaped grid.

Technical Field

The invention relates to the technical field of electronics, in particular to a GaN-based fin field effect transistor device and a manufacturing method thereof.

Background

GaN (gallium nitride) has been widely spotlighted as a semiconductor electronic material having physical properties such as a wide band, a high saturation velocity, etc. in the field of high-temperature, high-speed, and high-power electronics. AlGaN (aluminum gallium nitrogen)/GaN HEMTs (high electron mobility transistors) based on GaN materials have very good prospects in the field of microwave power devices due to high-concentration two-dimensional electron gas, high electron mobility and excellent breakdown field strength. As the device size decreases, short channel effects become more pronounced, causing device performance degradation. And a fin gate field effect transistor (FinFET) controls a device channel through three directions, so that the short channel effect is improved.

Transconductance g_mreflects the control capability of a gate to channel current and the source resistance R in an actual device_sthe effective voltage applied between the grid and the source is reduced, and the transconductance g of the saturation region is influenced_mand thus the linearity of the device. The measured transconductance satisfies g_m＝g_m*/(1+R_s·g_m) Wherein g is_mIs an intrinsic transconductance.

In 2013, Dong Seup Lee et al studied R_sThe modulation of the transconductance of the device. Research shows that the electric field intensity of the region can be reduced by adopting a wider source Channel region structure, so that the situation that the source resistance is increased along With the increase of the output current of the device is relieved, and the Linearity of the device is further improved (see Dong Seup Lee Nanowire Channel InAlN/GaN HEMTs With High Linearity of gm and fT IEEE ELECTRON DEVICE LETTERS, VOL.34, NO.8 and AUGUST 2013).

Chinese patent publication (publication No. CN106684141A) discloses a GaN fin-type high electron mobility transistor with high linearity. The device is provided with a passivation layer above a barrier layer, a groove is arranged in the passivation layer, the groove etches the barrier layer and the buffer layer only in the groove area to form GaN-based three-dimensional fins which are arranged periodically, and an isolation groove formed by etching is arranged between adjacent fins. The GaN-based three-dimensional fin structure is characterized in that the GaN-based three-dimensional fin is completely surrounded by gate metal, and a T-shaped gate structure is adopted. The device has good gate control capability and higher linearity, but the three-dimensional fin of the device is of a conventional rectangular structure, so that the device is still further optimized, and the space of linearity is improved.

one problem with current GaN-based FinFET devices remains insufficient linearity, which limits their further applications; under the condition that the process of the GaN-based Fin structure device is gradually mature, the space for improving the performance by the process improvement is smaller and smaller, and the improvement on the structure is needed to further improve the linearity.

disclosure of Invention

Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a GaN-based fin field effect transistor device, which comprises a substrate, a buffer layer, a barrier layer and a passivation layer which are sequentially arranged, wherein:

A source electrode is arranged at one end of the barrier layer, and a drain electrode is arranged at the other end of the barrier layer;

The passivation layer is arranged on the barrier layer between the source electrode and the drain electrode; an opening is formed in the middle of the passivation layer;

at least two grooves are arranged in the region of the barrier layer corresponding to the opening; fins are arranged between the adjacent grooves;

a T-shaped grid is arranged on the passivation layer and covers the groove and the fins; the length of the groove is equal to that of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove;

the width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.

Optionally, the cross section of the groove comprises a rectangular area and two isosceles triangular areas, and the isosceles triangular areas are respectively located on the outer side of one side of the rectangular area close to the source end and the outer side of one side close to the drain end;

And on the outer side, the length of the groove is the distance between the vertexes of the isosceles triangles.

Optionally, the minimum distance between adjacent 2 grooves is not less than 100 nm.

meanwhile, the invention also provides a manufacturing method of the GaN-based fin field effect transistor device, which comprises the following steps:

preparing a source electrode and a drain electrode on the surface of the GaN heterojunction material;

preparing a passivation layer on the barrier layer between the source electrode and the drain electrode;

Etching the passivation layer to form a rectangular opening on the passivation layer;

photoetching and etching a plurality of grooves on the barrier layer of the GaN-based heterojunction layer according to a preset shape, and forming fins between the adjacent grooves;

Preparing a T-shaped grid; the T-shaped grid electrode covers the groove and the fin;

the length of the groove is equal to that of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove.

Optionally, the step of preparing the source and the drain on the surface of the GaN heterojunction material includes:

and photoetching a source-drain pattern on the plane of the GaN heterojunction material, depositing source-drain metal, and annealing in a nitrogen atmosphere to prepare a source electrode and a drain electrode.

Optionally, the step of preparing a passivation layer on the barrier layer between the source electrode and the drain electrode includes:

a SiN passivation layer is grown on the surface of the barrier layer of the heterojunction material by a PECVD (Plasma Enhanced Chemical Vapor Deposition) Deposition technique.

Optionally, the etching the passivation layer to form a rectangular opening on the passivation layer specifically includes:

forming a photoresist pattern of a fin on the surface of the passivation layer by a photoetching technology; the photoetching technology adopts fluorine-based gas as etching process gas;

and etching the passivation layer by adopting an inductively coupled plasma etching technology or a reactive ion etching technology, wherein the surface of the passivation layer without the photoresist mask is etched to form the opening.

Optionally, the step of performing photolithography and etching on the barrier layer and the upper surface of the GaN-based heterojunction layer according to the preset shape to form at least two grooves, and forming fins between adjacent grooves includes:

Adopting Cl-based gas as etching process gas, continuously etching the barrier layer and the buffer layer of the GaN-based heterojunction layer exposed out of the opening to form grooves, and forming fin structures between the adjacent grooves;

The width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.

optionally, the step of preparing the T-shaped gate specifically includes:

Etching the fin and the barrier layer at the gate position by using an inductive coupling plasma etching technology or a reactive ion etching technology to form a gate pattern and etch away a passivation layer which is not masked by the photoresist by using F-based gas as etching process gas;

And photoetching a grid pattern at the grid position, carrying out metal evaporation on the whole surface of the passivation layer, and then stripping off the photoresist to form the T-shaped grid.

according to the GaN-based fin field effect transistor device provided by the embodiment of the invention, the width of the middle of the groove is larger than that of the two sides, so that the width of the fin is narrow in the middle and wide in the two sides, and the width of the joint area from the fin to the channel is gradually changed, so that the electric field distribution at the position, close to the fin, of the channel area is more uniform, the electric field intensity at the position is reduced, the resistance of the channel area is reduced, and the linearity of the device is further improved.

drawings

the following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

fig. 1 is a schematic diagram of a GaN-based finfet device structure according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional view of a GaN-based finfet device recess provided in accordance with an embodiment of the present invention;

fig. 3 is a schematic flow chart illustrating a method of fabricating a GaN-based finfet device according to an embodiment of the present invention;

FIGS. 4A-4E are schematic product structures at various steps of a GaN-based FinFET device fabrication process flow according to embodiments of the invention;

fig. 5 is a schematic diagram comparing fin structures of a GaN-based finfet device according to an embodiment of the present invention and a conventional finfet device of the prior art;

fig. 6 is a graph of field strength comparison simulation results at the junction of the fin and the source channel region of a GaN-based finfet device according to an embodiment of the present invention and a conventional finfet device of the prior art.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The invention firstly provides a GaN-based fin field effect transistor device, the structure of which is shown in fig. 1, and the GaN-based fin field effect transistor device comprises a substrate 101, a buffer layer 102, a barrier layer 103 and a passivation layer 104 which are sequentially arranged, wherein:

a source electrode 105 is arranged at one end of the barrier layer 103, and a drain electrode 106 is arranged at the other end of the barrier layer;

the passivation layer 104 is disposed on the barrier layer 103 between the source electrode 105 and the drain electrode 106; an opening is formed in the middle of the passivation layer 104;

A plurality of grooves 107 are arranged in the region of the barrier layer 103 corresponding to the opening; fins 108 are arranged between the adjacent grooves 107;

a T-shaped gate 109 is arranged on the passivation layer 104, and the T-shaped gate 109 covers the groove 107 and the fin 108; the length of the groove 107 is equal to that of the bottom of the T-shaped gate 109; the thickness of the fin 108 is equal to the depth of the groove 107;

The width of the portion of the groove 107 away from the passivation layer 104 is greater than the width of the portion close to the passivation layer 104.

The conventional rectangular fin structure has an abrupt change in width of the fin-channel junction region, and through simulation analysis, we find that the local electric field intensity of the channel region at a position close to the fin is large, so that the average electric field intensity of the region is large, and the resistance of the channel region is increased.

According to the GaN-based fin field effect transistor device provided by the embodiment of the invention, the width of the middle of the groove is larger than that of the two sides, so that the width of the fin is narrow in the middle and wide in the two sides, and the width of the joint area from the fin to the channel is gradually changed, so that the electric field distribution at the position, close to the fin, of the channel area is more uniform, the electric field intensity at the position is reduced, the resistance of the channel area is reduced, and the linearity of the device is further improved.

In some embodiments of the present invention, as shown in fig. 2, the cross section of the groove 201 includes a rectangular region 202 and two isosceles triangular regions 203, the isosceles triangular regions 203 are respectively located outside a side of the rectangular region close to the source end and outside a side close to the drain end, and the length of the groove 201 is the distance a between the vertices of the isosceles triangles.

fig. 5 is a comparison of fin structures of a GaN-based finfet device according to an embodiment of the invention and a conventional device. The upper half part of the figure 5 is a fin of a conventional field effect transistor, the conventional fin is a cuboid, and the width of the fin is abrupt change from a source-drain channel region to a fin region; the lower half part of fig. 5 is a fin structure of the GaN-based finfet device according to the embodiment of the present invention, and the width is gradually changed from the source/drain channel region to the fin region, so that the electric field distribution width of the channel region is linearly changed at a trapezoidal position, thereby optimizing the distribution of the electric field in the channel region.

By adopting the groove with the hexagonal cross section, the requirement that the pattern from the middle part of the fin to the channel region is separately gradually changed can be met, and the requirement of easy manufacture can also be met.

in other embodiments of the present invention, the cross section of the groove may also be other structures with gradually changing widths, such as a diamond shape, an irregular polygon, and the like.

Further, the present invention also provides a method for manufacturing a GaN-based finfet device, as shown in fig. 3, including:

Step 301: preparing a source electrode and a drain electrode on the surface of the GaN heterojunction material; as shown in fig. 4A, a source 401 and a drain 402 are located across the barrier layer of GaN heterojunction material 403, respectively.

step 302: preparing a passivation layer on the barrier layer between the source electrode and the drain electrode; as shown in fig. 4B, a passivation layer 404 covers the barrier layer of GaN heterojunction material 403 between the source 401 and drain 402.

Step 303: etching the passivation layer to form a rectangular opening on the passivation layer; as shown in fig. 4C;

Step 304: photoetching and etching at least two grooves on the barrier layer of the GaN-based heterojunction layer according to a preset shape, and forming fins between the adjacent grooves; still referring to fig. 4D, grooves 405 are etched in the exposed barrier layer at the openings, with portions of the barrier layer and portions of the buffer layer between the grooves 405 becoming fins 406;

step 305: preparing a T-shaped grid; the T-shaped grid electrode covers the groove and the fin; as shown in fig. 4E, T-shaped gate 407 fills into the recess, surrounding the fin in three directions;

The length of the groove is equal to that of the bottom of the T-shaped grid; the thickness of the fin is equal to the depth of the groove, namely the bottom surface of the groove is positioned in the buffer layer, and the fin comprises a part of the buffer layer and a part of the barrier layer between adjacent grooves.

The method for manufacturing the GaN-based FinFET device provided by the embodiment of the invention is used for manufacturing the GaN-based FinFET device provided by any one of the embodiments of the invention. The GaN heterojunction material comprises a substrate, a buffer layer and a barrier layer which are sequentially arranged.

in some embodiments of the present invention, the step of preparing the source and the drain on the surface of the GaN heterojunction material comprises:

And photoetching a source-drain pattern on the plane of the GaN heterojunction material, depositing source-drain metal, and annealing in a nitrogen atmosphere to prepare a source electrode and a drain electrode.

In some embodiments of the present invention, the step of preparing a passivation layer on the barrier layer between the source electrode and the drain electrode comprises:

And growing a SiN passivation layer on the surface of the barrier layer of the heterojunction material by a PECVD (plasma enhanced chemical vapor deposition) deposition technology.

in some embodiments of the present invention, the etching the passivation layer to form a rectangular opening on the passivation layer specifically includes:

forming a photoresist pattern of a fin on the surface of the passivation layer by a photoetching technology; the photoetching technology adopts fluorine-based gas as etching process gas; the fluorine-based gas may be CF₄Or SF₆。

And etching the passivation layer by adopting an inductively coupled plasma etching technology or a reactive ion etching technology, wherein the surface of the passivation layer without the photoresist mask is etched to form the opening.

in some embodiments of the present invention, the step of performing photolithography and etching on the barrier layer and the upper portion of the GaN-based heterojunction layer according to the predetermined shape to form at least two grooves, and forming the fin between the adjacent grooves includes:

Adopting Cl-based gas as etching process gas, continuously etching the barrier layer and the buffer layer of the GaN-based heterojunction layer exposed out of the opening to form grooves, and forming fin structures between the adjacent grooves; the Cl-based gas may be BCl₃or Cl₂etc.;

The width of the groove far away from the passivation layer part is larger than that of the groove near the passivation layer part.

In some embodiments of the present invention, the step of preparing the T-shaped gate specifically includes:

etching the fin and the barrier layer at the gate position by using an inductive coupling plasma etching technology or a reactive ion etching technology to form a gate pattern and etch away a passivation layer which is not masked by the photoresist by using F-based gas as etching process gas; the F-based gas may be CF₄、SF₆；

And photoetching a grid pattern at the grid position, carrying out metal evaporation on the whole surface of the passivation layer, and then stripping off the photoresist to form the T-shaped grid.

according to the GaN-based FinFET device provided by the embodiment of the invention, the width of the groove is larger than that of the middle part and larger than that of the two sides, so that the width of the fin is narrow in the middle and wide in the two sides, and the width of the joint area from the fin area to the channel area is gradually changed, so that the electric field distribution of the channel area close to the fin area is more uniform, the electric field intensity of the position is reduced, the resistance of the channel area is reduced, and the linearity of the device is further improved. Fig. 6 is a simulation result diagram of electric field strength in a source-drain channel region of a GaN-based fin field effect transistor device and a simulation result diagram of electric field strength in a source-drain channel region of a field effect transistor in the prior art, and it can be seen that electric field distribution in the source-drain channel region of the GaN-based fin field effect transistor device provided by the present invention is optimized, peak value is reduced, source resistance is further reduced, and linearity is improved.

In summary, the principle and embodiments of the present invention are described herein by using specific examples, and the above descriptions of the examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.