阅读说明：本技术 异质栅介质的异质结隧穿场效应晶体管及其制作方法 (Heterojunction tunneling field effect transistor of heterogeneous gate dielectric and manufacturing method thereof ) 是由 段小玲 王树龙 王刚 张进成 张涛 刘志宏 赵胜雷 许晟瑞 郝跃 于 2021-07-26 设计创作，主要内容包括：本发明公开了一种异质栅介质的异质结隧穿场效应晶体管及其制作方法,主要解决现有隧穿场效应晶体管开态电流小和双极效应严重的问题。其包括源极、栅极、漏极、源区、沟道区和漏区,载流子通过源极进入沟道区并通过漏极离开沟道区,沟道区包括“一”部和“1”部,“1”部包括与“一”部连接的第一连接端,以及与第一连接端相对设置的第二连接端,第二连接端通过漏区连接漏极,“1”部的两侧设置有两个栅极,两个栅极与“1”部之间分别设置有两个第一异质介质,栅极和第一异质介质垂直于第二异质介质设置,且第一异质介质与第二异质介质的高度之和与“1”部相等,栅极与第一异质介质高度相等,“一”部两侧分别设置有两个源极。(The invention discloses a heterojunction tunneling field effect transistor of a heterogeneous gate medium and a manufacturing method thereof, and mainly solves the problems of small on-state current and serious bipolar effect of the traditional tunneling field effect transistor. The charge carrier source comprises a source electrode, a grid electrode, a drain electrode, a source region, a channel region and a drain region, wherein the charge carrier enters the channel region through the source electrode and leaves the channel region through the drain electrode, the channel region comprises a first connecting end and a second connecting end, the first connecting end is connected with the first connecting end, the second connecting end is opposite to the first connecting end, the second connecting end is connected with the drain electrode through the drain region, two grid electrodes are arranged on two sides of the 1 part, two first heterogeneous media are respectively arranged between the two grid electrodes and the 1 part, the grid electrodes and the first heterogeneous media are perpendicular to the second heterogeneous media, the sum of the heights of the first heterogeneous media and the second heterogeneous media is equal to the height of the 1 part, the heights of the grid electrodes and the first heterogeneous media are equal, and two source electrodes are respectively arranged on two sides of the first part.)

1. A heterojunction tunneling field effect transistor of a heterogeneous gate medium comprises a source electrode, a grid electrode, a drain electrode, a source region, a channel region and a drain region, current carriers enter the channel region through the source electrode and leave the channel region through the drain electrode, the grid electrode is used for modulating an electrode for switching on and off the channel region, the heterojunction tunneling field effect transistor is characterized in that the channel region comprises a 'one' portion and a '1' portion, the '1' portion comprises a first connecting end connected with the 'one' portion and a second connecting end arranged opposite to the first connecting end, and the second connecting end is connected with the first connecting end through an N⁺The drain region is connected with the drain electrode, two grid electrodes are arranged on two sides of the '1' part, two first heterogeneous media are respectively arranged between the two grid electrodes and the '1' part, the grid electrodes and the first heterogeneous media are perpendicular to the second heterogeneous media, the sum of the heights of the first heterogeneous media and the second heterogeneous media is equal to the height of the '1' part, the height of the grid electrodes is equal to the height of the first heterogeneous media, and two source electrodes are respectively arranged on two sides of the 'one' part.

2. The heterojunction tunneling field effect transistor of the heterogeneous gate dielectric of claim 1, wherein the material of the first heterogeneous medium is a low-K dielectric material, and/or

The material of the second heterogeneous medium is a high-K medium material.

3. The heterojunction tunneling field effect transistor of claim 2, wherein the first heterogeneous medium is silicon dioxide and/or the second heterogeneous medium is hafnium oxide.

4. The heterojunction tunneling field effect transistor of claim 1, further comprising two source regions and two interlayers located on both sides of the two source regions and the "one" portion, wherein the input ends of the source regions are connected to the source regionsIts output end is connected with the N⁺The output end of the type interlayer is respectively connected with the two sides of the first part;

the source region is used for enlarging a tunneling region and enlarging carriers, and N is⁺The interlayer is used for reducing tunneling visual barrier and increasing tunneling probability.

5. A heterojunction tunneling field effect transistor according to claim 4, further comprising an SOI substrate under said "one" portion.

6. The heterojunction tunneling field effect transistor of claim 5, wherein the length of the SOI substrate is equal to the length of the "one" part and two P's on both sides of the "one" part⁺The sum of the lengths of the source region and the two interlayers.

7. A manufacturing method of a heterojunction tunneling field effect transistor based on the heterogeneous gate dielectric of any one of claims 1 to 6, wherein the manufacturing method comprises the following steps:

s1: sequentially preparing SOI substrates of bottom silicon, an oxide buried layer and top silicon;

s2: etching the region outside the drain region on the surface of the top layer silicon to form an inverted T-shaped structure to obtain an inverted T-shaped channel region;

s3: etching two sides of the top layer silicon to form source region grooves, epitaxially depositing a silicon germanium material to fill the source region grooves at the temperature of 400-600 ℃, and introducing boron doping gas into the silicon to carry out in-situ doping on the source region to form a P-type source region;

s4: photoetching patterns of a drain region and an interlayer region on the surface of the top layer silicon in sequence, respectively injecting arsenic ions with corresponding measurement into the drain region and the interlayer region by adopting an ion injection process, and annealing and activating impurities to form an N + type drain region and an N + interlayer region;

s5: growing second heterogeneous gate dielectric hafnium oxide on the surfaces of the source region and the interlayer region;

s6: growing first heterogeneous gate dielectric silicon dioxide on two sides of the 1 part of the channel region, and depositing polycrystalline silicon to form a gate;

s7: and photoetching source electrode and drain electrode windows in the source region and the drain region, and depositing metal to form a source electrode and a drain electrode.

Technical Field

The invention relates to the technical field of transistors, in particular to a heterojunction tunneling field effect transistor of a heterogeneous gate medium and a manufacturing method thereof.

Background

Due to the development of semiconductor manufacturing processes, the feature size of transistors is continuously reduced, so that the integrated circuit is continuously developed towards high performance and low cost. However, in the conventional CMOS field effect transistor low power consumption digital integrated circuit based on the hot electron emission mechanism, since the sub-threshold swing cannot break through the limit of 60mv/dec at room temperature, the power supply voltage cannot be reduced with the reduction of the device size, thereby further increasing the leakage current of the device, and the rapid increase of the number of devices per unit area finally leads to the rapid increase of the static power consumption and the dynamic power consumption of the integrated circuit. In addition, as the feature size is reduced to approach the physical limit, the integrated circuit manufacturing technology also encounters the parameter physical limit and the process manufacturing bottleneck, such as gate leakage and channel leakage caused by quantum tunneling effect, hot carrier effect of short channel, negative bias temperature instability, drain induced barrier lowering, channel carrier distribution quantum fluctuation, etc., which seriously affects the expected performance of the device. In order to reduce the subthreshold swing and the off-state leakage current, research on the tunneling field effect transistor TFET is carried out. The tunneling field effect transistor TFET based on the band-band tunneling BTBT principle can obtain a sub-threshold swing SS lower than 60mV/Dec at room temperature and is not easily influenced by a short channel effect, so that the tunneling field effect transistor TFET can further reduce a power supply voltage VDD, and the TFET can have lower off-state current due to the existence of a tunneling barrier, thereby meeting the application of a low-power-consumption integrated circuit.

Although TFETs have great application prospects in the field of low power consumption, conventional silicon-based TFETs have the disadvantages of small on-state current and serious bipolar effect, which limits further development of TFET devices.

Disclosure of Invention

The invention aims to provide a heterojunction tunneling field effect transistor of a heterogeneous gate medium and a manufacturing method thereof, and aims to solve the problems that the existing silicon-based TFET has the defects of small on-state current and serious bipolar effect.

The technical scheme for solving the technical problems is as follows:

the invention provides a heterojunction tunneling field effect transistor of heterogeneous gate media, which comprises a source electrode, a grid electrode, a drain electrode, a source region, a channel region and a drain region, wherein current carriers enter the channel region through the source electrode and leave the channel region through the drain electrode, the grid electrode is used for modulating an electrode for switching on and off the channel region, the channel region comprises a 'one' part and a '1' part, the '1' part comprises a first connecting end connected with the 'one' part and a second connecting end arranged opposite to the first connecting end, the second connecting end is connected with the drain electrode through the drain region, two grid electrodes are arranged on two sides of the '1' part, two first heterogeneous media are respectively arranged between the two grid electrodes and the '1' part, and the grid electrodes and the first heterogeneous media are arranged vertical to the second heterogeneous media, and the sum of the heights of the first heterogeneous medium and the second heterogeneous medium is equal to the height of the '1' part, the height of the grid electrode is equal to the height of the first heterogeneous medium, and two sides of the 'one' part are respectively provided with two source electrodes.

Optionally, the material of the first heterogeneous medium is a low-K medium material, and/or

The material of the second heterogeneous medium is a high-K medium material.

Optionally, the first heterogeneous medium is silicon dioxide, and/or the second heterogeneous medium is hafnium oxide.

Optionally, the tunneling field effect transistor further comprises two P's located on both sides of the two source electrodes and the "one" portion⁺Source region and two N⁺Type interlayer of said P⁺The input end of the source region is connected with the output end of the source electrode, and the output end of the source region is connected with the N⁺Input of the type sandwich, N⁺The output end of the type interlayer is respectively connected with the two sides of the first part; the P is⁺The source region is used for enlarging a tunneling region and enlarging carriers, and the N is⁺The interlayer is used for reducing tunneling visual barrier and increasing tunneling probability.

Optionally, the tunneling field effect transistor further comprises an SOI substrate located below the "one" portion.

Optionally, the length of the SOI substrate is equal to the length of the "one" portion and two P's on either side of the "one" portion⁺Source region and two N⁺Sum of length of type interlayer.

The invention also provides a manufacturing method of the heterojunction tunneling field effect transistor based on the heterogeneous gate medium, which comprises the following steps:

s1: sequentially preparing SOI substrates of bottom silicon, an oxide buried layer and top silicon;

s2: etching the region outside the drain region on the surface of the top layer silicon to form an inverted T-shaped structure to obtain an inverted T-shaped channel region;

s3: etching two sides of the top layer silicon to form source region grooves, epitaxially depositing a silicon germanium material to fill the source region grooves at the temperature of 400-600 ℃, and introducing boron doping gas into the silicon to carry out in-situ doping on the source region to form a P-type source region;

s4: photoetching patterns of a drain region and an interlayer region on the surface of the top layer silicon in sequence, respectively injecting arsenic ions with corresponding measurement into the drain region and the interlayer region by adopting an ion injection process, and annealing and activating impurities to form an N + type drain region and an N + interlayer region;

s5: growing second heterogeneous gate dielectric hafnium oxide on the surfaces of the source region and the interlayer region;

s6: growing first heterogeneous gate dielectric silicon dioxide on two sides of the 1 part of the channel region, and depositing polycrystalline silicon to form a gate;

s7: and photoetching source electrode and drain electrode windows in the source region and the drain region, and depositing metal to form a source electrode and a drain electrode.

The invention has the following beneficial effects:

the invention provides a hetero-gate dielectric double-gate SiGe/Si hetero-junction TFET structure (HGD-DG-HJTFET) of an inverted T-shaped channel different from the traditional Si-TFET. The existence of the '1' part and the 'one' part ensures that the channel region of the invention presents an inverted T shape, the inverted T-shaped channel can increase a tunneling region and improve the on-state current of a device, the heterogeneous gate dielectric structure ensures that a grid electrode has different grid control capacities to a source region and the channel region close to a drain, the bipolar effect of the TFET can be effectively inhibited, and in addition, Si is used in the source region and the channel_0.9Ge_0.1The heterojunction reduces the tunneling barrier width and the interlayer is used to improve the subthreshold characteristics of the device. Finally, the TFET structure can inhibit bipolar current while achieving higher on-state current.

Drawings

FIG. 1 is a block diagram of a heterojunction tunneling field effect transistor (HGD-DG-HJTFET) of a heterogeneous gate dielectric provided by the present invention;

FIG. 2 is a flow chart of a method for fabricating a heterojunction tunneling field effect transistor (HGD-DG-HJTFET) of a heterogeneous gate dielectric according to the present invention;

FIG. 3 is a process diagram of the heterojunction tunneling field effect transistor of the heterogeneous gate dielectric provided by the present invention;

FIG. 4 is a graph comparing transfer characteristics of an inverted T-channel heterojunction double-gate tunneling field effect transistor with or without a hetero-gate structure;

FIG. 5 shows the presence or absence of N⁺Graph comparing the transfer characteristics of HGD-DG-HJTFET with inverted T-shaped channel in interlayer.

Description of the reference numerals

1-a source electrode; 2-a grid; 3-a drain electrode; 4-a channel region; 41-a first connection end; 42-a second connection end; 5-a drain region; 6-a first heterogeneous medium; 7-a second heterogeneous medium; 8-N⁺A mold sandwich; 9-P⁺A source region; 10-SOI substrate.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

Example 1

The technical scheme for solving the technical problems is as follows:

the invention provides a heterojunction tunneling field effect transistor of heterogeneous gate media, which comprises a source electrode 1, a grid electrode 2, a drain electrode 3, a source region 9, a channel region 4 and a drain region 5, wherein current carriers enter the channel region 4 through the source electrode 1 and leave the channel region 4 through the drain electrode 3, the grid electrode 2 is used for modulating an electrode for switching on and off the channel region 4, the channel region 4 comprises a 'one' part and a '1' part, the '1' part comprises a first connecting end 41 connected with the 'one' part and a second connecting end 42 arranged opposite to the first connecting end 41, the second connecting end 42 is connected with the drain electrode 3 through the drain region 5, two grid electrodes 2 are arranged on two sides of the '1' part, two first heterogeneous media 6 are respectively arranged between the two grid electrodes 2 and the '1' part, the grid electrode 2 and the first heterogeneous medium 6 are arranged perpendicular to the second heterogeneous medium 7, the sum of the heights of the first heterogeneous medium 6 and the second heterogeneous medium 7 is equal to the height of the '1' part, the height of the grid electrode 2 is equal to the height of the first heterogeneous medium 6, and two source electrodes 1 are arranged on two sides of the 'one' part respectively.

The invention has the following beneficial effects:

the invention provides a hetero-gate dielectric double-gate SiGe/Si hetero-junction TFET structure (HGD-DG-HJTFET) of an inverted T-shaped channel different from the traditional Si-TFET. The existence of the '1' part and the 'one' part ensures that the channel region 4 of the invention presents an inverted T shape, the inverted T-shaped channel can increase a tunneling region and improve the on-state current of a device, the heterogeneous gate dielectric structure ensures that the grid 2 has different grid control capacities for the source region and the channel region 4 close to the drain, the bipolar effect of the TFET can be effectively inhibited, and in addition, Si is used in the source region and the channel_0.9Ge_0.1Heterojunction to reduce tunneling barrier width and use of clampThe layer improves the device subthreshold characteristics. Finally, the TFET structure can inhibit bipolar current while achieving higher on-state current.

Optionally, the material of the first heterogeneous medium 6 is a low-K medium material, and/or

The material of the second heterogeneous medium 7 is a high-K medium material.

Optionally, the first heterogeneous medium 6 is silicon dioxide, and/or the second heterogeneous medium 7 is hafnium oxide.

Optionally, the tunneling field effect transistor further comprises two P's located at both sides of the two source electrodes 1 and the "one" portion⁺Source region 9 and two N⁺Type interlayer 8, said P⁺The input end of the type source region 9 is connected with the output end of the source electrode 1, and the output end thereof is connected with the N⁺Input of the type interlayer 8, N⁺The output end of the type interlayer 8 is respectively connected with the two sides of the first part; the P is⁺The source region 9 is used for enlarging a tunneling region and enlarging carriers, and N is⁺The interlayer 8 is used for reducing tunneling visual barrier and increasing tunneling probability.

Optionally, the tunneling field effect transistor further comprises an SOI substrate 10 located below the "one" portion. The SOI substrate 10 is an insulator and can prevent leakage inside the transistor.

Optionally, the length of the SOI substrate 10 is equal to the length of the "one" portion and two P's on either side of the "one" portion⁺Source region and two N⁺The sum of the lengths of the mold sandwich 8.

Specifically, the channel region 4 is located right above the SOI substrate 10 and is placed in the center of the device in an inverted T shape, and the doping concentration is 1 × 10¹⁶/cm³The length of the channel close to the substrate is 30 +/-1 nm, the height is 10 +/-1 nm, the length of the rest channel is 26 +/-1 nm, and the height is 63 +/-1 nm.

N⁺The height of the interlayer 8 is 10 +/-1 nm, the length is 5 +/-0.5 nm, and the doping concentration is 5 multiplied by 10¹⁸/cm³Symmetrically located on both sides of the channel region 42;

P⁺the height of the source region 9 is 10 + -1 nm, and the length is 15 + -1 nmThe doping concentration is 6 multiplied by 10¹⁹/cm³Which is symmetrically located at N⁺Right and left sides of the interlayer 8 and N⁺The interlayers 8 are adjacent;

the first heterogeneous medium 6 adopts a high-K dielectric material HfO₂To improve the grid control capability, is horizontally arranged on P⁺Source regions 4 and N⁺Above the interlayer 8 and adjacent to the channel region 42, the height is 3 + -1 nm and the length is 13 + -1 nm.

The second heterogeneous medium 7 adopts a low-K medium material SiO2 to reduce bipolar current, is vertically arranged above the first heterogeneous medium 6 and is adjacent to the channel region 42, and has a height of 60 +/-1 nm and a length of 3 +/-1 nm.

N⁺The drain region 5 is located right above the channel, and has a height of 10 + -1 nm, a length of 26 + -1 nm, and a doping concentration of 5 × 10¹⁸/cm³。

Of course, these dimensions and dimensional ranges do not represent limitations of the present invention, and other dimensions may be devised by those skilled in the art in light of the present invention, and are within the scope of the present invention.

Example 2

The invention also provides a manufacturing method of the heterojunction tunneling field effect transistor based on the heterogeneous gate medium,

referring to fig. 2, the manufacturing method includes:

s1: the SOI substrate 10 of the bottom silicon, the oxidized physical layer, and the top silicon is prepared in this order.

The preparation method specifically comprises the following steps:

s11: preparing buried oxide layer silicon dioxide on a silicon wafer of bottom layer silicon by utilizing thermal oxidation;

s12: forming a silicon epitaxial layer on the surface of the buried oxide layer through epitaxial growth to form an SOI substrate;

s13: SOI substrate concentration of 1 × 10¹⁶cm^-3Doping P-type ions.

S2: and etching the region outside the drain region on the surface of the top layer silicon to form an inverted T-shaped structure, thereby obtaining an inverted T-shaped channel region.

S21: growing a layer of SiO on the surface of the top layer silicon₂Protective layer and coatingAnd photoresist is exposed and developed. Forming corresponding patterns at set positions on two sides of the top silicon surface by using a photoetching process;

s22: etching the interlayer pattern by using a dry etching process to form an inverted T-shaped structure;

s23: cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S3: preparation of doping concentration of 6X 10¹⁹/cm³P of⁺A source region 9.

S31: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a source region pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s32: etching the source region pattern by using a dry etching process, wherein the etching depth is the thickness of the top layer silicon, and a source region groove is formed;

s33: depositing silicon germanium material in the groove of the source region by using a selective epitaxial growth process, introducing boron doping gas to carry out in-situ doping on the source region, annealing to realize in-situ activation of doping elements, and forming the doped concentration of 6 multiplied by 10¹⁹/cm³P of⁺A source region;

s34: cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S4: preparation of doping concentration of 5X 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³N of (A)⁺And a region of the type interlayer 8.

S41: growing a layer of silicon dioxide on the surface of the top silicon to form a protective layer, coating photoresist, carrying out exposure and development, and forming a drain region and an interlayer pattern at a set position on the surface of the top silicon by utilizing a photoetching process;

s42: etching the source region and the interlayer pattern by using a dry etching process to obtain a drain region groove and an interlayer groove with required thickness;

s43: respectively injecting arsenic ions with corresponding measurement into the drain region groove and the interlayer groove by adopting an ion injection process, annealing and activating impurities to form a doped concentration of 5 multiplied by 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³N of (A)⁺A region of type interlayer 8;

cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S5: and growing second heterogeneous gate dielectric hafnium oxide on the surfaces of the source region and the interlayer region.

S51: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a second heterogeneous gate dielectric 7 pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s52: etching the second heterogeneous gate dielectric 7 pattern by using a dry etching process to remove the silicon dioxide protective layer;

s53: depositing high-K dielectric hafnium oxide in the high-K dielectric region by using a chemical vapor deposition process; and etching the redundant hafnium oxide on two sides by using a selective etching process.

Step 6: and growing first heterogeneous gate dielectric 6 silicon dioxide on two sides of the channel region 1 part, and depositing polycrystalline silicon to form a gate.

S61: depositing SiO on the grooves at two sides of the '1' part of the channel region of the obtained device by using a chemical vapor deposition process at 600 DEG C₂To make SiO₂Filling the groove of the gate region, performing flatness treatment on the surface of the top silicon layer by using mechanical polishing, coating photoresist, performing exposure and development, and forming a gate pattern at a set position on the surface of the top silicon layer by using a photoetching process;

s62: etching the grid pattern by using a dry etching process to form a grid groove; epitaxially growing heavily doped crystalline silicon gate materials in grooves on two sides of the '1' part of the channel region so as to form a gate 2;

s63: carrying out flatness treatment on the surface of the top silicon layer by using mechanical polishing, and removing the silicon dioxide protective layer and the polysilicon on the surface;

s64: the gate and drain regions 5 are protected using a photoresist mask and the SiO is selectively etched away using a reactive ion etching process₂The remainder of the process.

S7: at the P⁺Source region of the pattern9 and the drain region 5 are photoetched to form a source electrode window and a drain electrode window, and metal is deposited to form a source electrode 1 and a drain electrode 3.

S71: photoetching source electrode windows and drain electrode windows in the source region and the drain region, and respectively depositing a layer of Al metal film on the source electrode windows and the drain electrode windows by utilizing a chemical vapor deposition process at the temperature of 200 ℃ to form a source electrode 1 and a drain electrode 3;

s72: and washing the residual stripping solution by using ethanol and acetone to finish the preparation of the inverted T-shaped channel heterogeneous double-gate heterojunction tunneling field effect transistor HGD-DG-HJTFET.

Example 3 fabrication of a first hetero-gate dielectric of SiO₂The second heterogeneous gate dielectric with the thickness of 3nm and the thickness of 3nm is HfO₂The preparation method of the tunneling field effect transistor comprises the following steps:

s1: preparing an SOI substrate 10 of bottom silicon, oxidized physical layer and top silicon in this order, as shown in fig. 3 (a);

s11: preparing silicon dioxide of an oxygen burying layer on a silicon wafer by utilizing thermal oxidation;

s12: forming a silicon epitaxial layer on the surface of the buried oxide layer through epitaxial growth to form an SOI substrate 10;

s13: doping the SOI substrate 10 to a concentration of 1 × 10¹⁶cm^-3Doping P-type ions.

S2: etching the region outside the drain region on the top silicon surface to form an inverted T-shaped structure, and obtaining an inverted T-shaped channel region 4, as shown in FIG. 3 (b);

s21: growing a layer of SiO on the surface of the top layer silicon₂And (4) coating a photoresist on the protective layer, and carrying out exposure and development. Forming corresponding patterns at set positions on two sides of the top silicon surface by using a photoetching process;

s22: etching the interlayer pattern by using a dry etching process to form an inverted T-shaped structure;

s23: cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S3: preparation of doping concentration of 6X 10¹⁹/cm³P of⁺Source region 9, fig. 3 (c);

s31: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a source region pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s32: etching the source region pattern by using a dry etching process, wherein the etching depth is the thickness of the source region, and a source region groove is formed;

s33: depositing germanium-silicon material in the groove of the source region by using a selective epitaxial growth process, introducing boron doping gas to carry out in-situ doping on the source region, annealing to realize in-situ activation of doping elements, and forming the silicon-germanium material with the doping concentration of 6 multiplied by 10¹⁹/cm³P of⁺A source region 9;

cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S4: preparation of doping concentration of 5X 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³N of (A)⁺Zone of type interlayer 8, as in fig. 3 (d);

s41: growing a layer of silicon dioxide on the surface of the top silicon to form a protective layer, coating photoresist, carrying out exposure and development, and forming a drain region and an interlayer pattern at a set position on the surface of the top silicon by utilizing a photoetching process;

s42: etching the source region and the interlayer pattern by using a dry etching process to obtain a drain region groove and an interlayer groove with required thickness;

s43: respectively injecting arsenic ions with corresponding measurement into the groove of the drain region and the groove of the interlayer region by adopting an ion injection process, annealing and activating impurities to form a silicon nitride semiconductor material with the doping concentration of 5 multiplied by 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³N of (A)⁺A region of type interlayer 8;

cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S5: preparing a second heterogeneous gate dielectric HfO with the thickness of 3nm₂And a gate is fabricated, as shown in fig. 3 (e);

s51: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a second heterogeneous gate dielectric 7 pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s52: etching the second heterogeneous gate dielectric 7 pattern by using a dry etching process to remove the silicon dioxide protective layer;

s53: depositing high-K dielectric HfO with the thickness of 3nm in the high-K dielectric region by using a chemical vapor deposition process₂(ii) a Etching off redundant HfO on two sides by using selective etching process₂。

S6: preparing first heterogeneous gate dielectric SiO with the thickness of 3nm₂And a grid is manufactured, as shown in fig. 3 (f);

s61: depositing low-K dielectric SiO on the grooves at two sides of the '1' part of the channel region of the obtained device by using a chemical vapor deposition process at 600 DEG C₂To make SiO₂Filling the groove of the gate region, performing flatness treatment on the top silicon surface by using mechanical polishing, coating photoresist, performing exposure and development, and forming a gate pattern at a set position on the top silicon surface by using a photoetching process to ensure that SiO at two sides of the channel of the '1' part is formed₂The thickness is 3 nm;

s62: etching the grid pattern by using a dry etching process to form a grid groove; epitaxially growing a heavily doped crystalline silicon gate material in the groove of the gate region so as to form a gate 2;

s63: carrying out flatness treatment on the surface of the top silicon layer by using mechanical polishing, and removing the silicon dioxide protective layer and the polysilicon on the surface;

s64: the gate and drain regions 5 are protected using a photoresist mask and the SiO is selectively etched away using a reactive ion etching process₂The remainder of the process.

S7: at the P⁺Photoetching source electrode and drain electrode windows in the source region 9 and the drain region 5, and depositing metal to form a source electrode 1 and a drain electrode 3, as shown in fig. 3 (g);

s71: at the P⁺Photoetching a source electrode window and a drain electrode window in the source region 9 and the drain region 5, and respectively depositing a layer of Al metal film on the source electrode window and the drain electrode window by utilizing a chemical vapor deposition process at the temperature of 200 ℃ to form a source electrode 1 and a drain electrode 3;

s72: and cleaning the residual stripping solution by using ethanol and acetone to finish the preparation of the inverted T-shaped channel heterogeneous gate dielectric double-gate heterojunction tunneling field effect transistor HGD-DG-HJTFET.

Example 4 fabrication of a first hetero-gate dielectric of SiO₂The second heterogeneous gate dielectric with the thickness of 5nm and the thickness of 2nm is HfO₂A tunneling field effect transistor.

S1: preparing an SOI substrate of bottom silicon, an oxidized physical layer and top silicon in sequence, as shown in FIG. 3 (a);

s11, preparing the silicon dioxide of the buried oxide layer on the silicon wafer by thermal oxidation;

s12: forming a silicon epitaxial layer on the surface of the buried oxide layer through epitaxial growth to form an SOI substrate 10;

s13: doping the substrate to a concentration of 1 × 10 with respect to the SOI substrate¹⁶cm^-3Doping P-type ions.

S2: etching the region outside the drain region on the top silicon surface to form an inverted T-shaped structure, and obtaining an inverted T-shaped channel region 4, as shown in FIG. 3 (b);

s21: growing a layer of SiO on the surface of the top layer silicon₂And (4) coating a photoresist on the protective layer, and carrying out exposure and development. Forming corresponding patterns at set positions on two sides of the top silicon surface by using a photoetching process;

s22: etching the interlayer pattern by using a dry etching process to form an inverted T-shaped structure;

s23: cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S3: preparation of doping concentration of 6X 10¹⁹/cm³P of⁺Source region 9, fig. 3 (c);

s31: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a source region pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s32: etching the source region pattern by using a dry etching process, wherein the etching depth is the thickness of the top layer silicon, and a source region groove is formed;

s33: depositing silicon germanium material in the groove of the source region by using a selective epitaxial growth process, and simultaneously introducing boron doping gas to carry out in-situ doping on the source regionThen annealing to activate the doped element in situ to form a doped concentration of 6 × 10¹⁹/cm³P of⁺A source region 9;

s34: cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S4: preparation of doping concentration of 5X 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³N of (A)⁺A region of type interlayer 8, as shown in (d);

s41: growing a layer of silicon dioxide on the surface of the top silicon to form a protective layer, coating photoresist, carrying out exposure and development, and forming a drain region and an interlayer pattern at a set position on the surface of the top silicon by utilizing a photoetching process;

s42: etching the source region and the interlayer pattern by using a dry etching process to obtain a drain region groove and an interlayer groove with required thickness;

s43: respectively injecting arsenic ions with corresponding measurement into the drain region groove and the interlayer groove by adopting an ion injection process, annealing and activating impurities to form a doped concentration of 5 multiplied by 10¹⁸/cm³And doping concentration of 5 × 10¹⁸/cm³An N + interlayer region;

cleaning the photoresist, cleaning with HF solution to remove SiO₂And (3) a layer.

S5: preparation of high-K dielectric HfO with thickness of 2nm₂As in fig. 3 (e);

s51: growing a layer of silicon dioxide on the surface of the top silicon layer to form a protective layer, coating photoresist, carrying out exposure and development, and forming a second heterogeneous gate dielectric 7 pattern at a set position on the surface of the top silicon layer by utilizing a photoetching process;

s52: and etching the second heterogeneous gate dielectric 7 pattern by using a dry etching process to remove the silicon dioxide protective layer.

S53: depositing high-K dielectric HfO with the thickness of 2nm in the high-K dielectric region by using a chemical vapor deposition process₂(ii) a Etching off redundant HfO on two sides by using selective etching process₂。

S6: preparing a first heterogeneous gate dielectric 6SiO with the thickness of 3nm₂And making a gate2, as in fig. 3 (f);

s61: depositing SiO on the grooves at two sides of the '1' part of the channel region of the obtained device by using a chemical vapor deposition process at 600 DEG C₂To make SiO₂Filling the groove of the gate region, performing flatness treatment on the top silicon surface by using mechanical polishing, coating photoresist, performing exposure and development, and forming a gate pattern at a set position on the top silicon surface by using a photoetching process to ensure that SiO at two sides of the channel of the '1' part is formed₂The thickness was 5 nm.

S62: etching the grid pattern by using a dry etching process to form a grid groove; epitaxially growing a heavily doped crystalline silicon gate material in the groove of the gate region so as to form a gate 2;

s63: and (4) carrying out flatness treatment on the top silicon surface by using mechanical polishing, and removing the silicon dioxide protective layer and the polysilicon on the surface.

S64: the gate and drain regions 5 are protected using a photoresist mask and the SiO is selectively etched away using a reactive ion etching process₂The remainder of the process.

S7: photoetching source electrode and drain electrode windows in the source region and the drain region, and depositing metal to form a source electrode 1 and a drain electrode 3, as shown in figure 3 (g);

s71: photoetching source electrode windows and drain electrode windows in the source region and the drain region, and respectively depositing a layer of Al metal film on the source electrode windows and the drain electrode windows by utilizing a chemical vapor deposition process at the temperature of 200 ℃ to form a source electrode 1 and a drain electrode 3;

s72: and cleaning the residual stripping solution by using ethanol and acetone to finish the preparation of the double-gate heterojunction tunneling field effect transistor HGD-DG-HJTFET of the inverted T-shaped channel heterogeneous gate medium.

Example 5

In addition, the invention uses synopsys sentaurus TCAD software to simulate the inverted T-shaped channel heterogeneous gate dielectric double-gate heterojunction tunneling field effect transistor, so the effect of the invention can be further illustrated by the following simulation result:

simulation 1: increasing the gate voltage from-1V to 1V, using a second gate dielectric SiO₂Inverted T-shaped channel heterogeneous gate dielectric double-gate differential gate with thickness of 3nmThe respective transfer characteristic curves of the homogeneous gate dielectric double-gate heterojunction tunneling field effect transistor (HGD-DG-HJTFET) with the inverted T-shaped channel are simulated, and the result is shown in FIG. 4.

Simulation 2: increasing the gate voltage from-1V to 1V, using a second gate dielectric SiO₂Simulation of existence of N for inverted T-shaped channel heterogeneous gate dielectric double-gate heterojunction tunneling field effect transistor (HGD-DG-HJTFET) with thickness of 3nm⁺The result of the transfer characteristic curve for type interlayer 8 is fig. 5.

As can be seen from FIG. 4, the gate dielectric is SiO only₂The low-K dielectric also weakens the gate control capability, the device on-state current is the minimum of three devices, and the average subthreshold swing of the device is the maximum (67 mV/dec), although the TFET has weaker bipolar effect. And the gate dielectric is only HfO₂The TFET of (a) has a higher on-state current, but the bipolar effect is also significant. However, due to the existence of heterogeneous gate dielectric, the on-state current and the gate dielectric of the HGD-DG-HJTFET are only HfO₂The TFET of the transistor is at the same level, and the same gate dielectric for inhibiting the bipolar effect is only SiO₂The TFETs of (a) were consistent, while the average subthreshold swing was only 18 mV/dec. Therefore, the HGD-DG-HJTFET provided by the method not only can inhibit bipolar current, but also can keep on-state current at a high level, and the device also has good subthreshold characteristics.

From FIG. 4, it can be seen whether or not N is present⁺The type interlayer 8 has no effect on the bipolar characteristics of the suppression device because both employ a heterogeneous gate dielectric. And adding N⁺The subthreshold characteristic of the device is obviously improved after the type interlayer 8 is formed, because N is⁺The interlayer 8 can improve the tunneling incidence rate of the device at low grid voltage, the SiGe/Si heterojunction can improve the on-state current of the device, and the N⁺The type interlayer 8 improves the subthreshold characteristics of the device, and the two improve the electrical characteristics of the device together.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.