阅读说明：本技术 全包覆式栅极结构及其制造方法 (Fully-wrapped grid structure and manufacturing method thereof ) 是由 萧孟轩 云惟胜 陈维宁 李东颖 叶凌彦 于 2019-02-27 设计创作，主要内容包括：本发明实施例涉及全包覆式栅极结构及其制造方法。本揭露提供全包覆式栅极结构,其包含：半导体鳍片,其具有顶表面；第一纳米线,其在所述顶表面上方；第一空间,其在所述顶表面与所述第一纳米线之间；第N纳米线及第N+1纳米线,其在所述第一纳米线上方；及第二空间,其在所述第N纳米线与所述第N+1纳米线之间。所述第一空间大于所述第二空间。本揭露还提供一种用于制造本文中所描述的所述全包覆式栅极结构的方法。(The embodiment of the invention relates to a fully-wrapped grid structure and a manufacturing method thereof. The present disclosure provides a fully-wrapped-gate structure, comprising: a semiconductor fin having a top surface; a first nanowire over the top surface; a first space between the top surface and the first nanowire; an Nth nanowire and an (N +1) th nanowire over the first nanowire; and a second space between the nth nanowire and the (N +1) th nanowire. The first space is larger than the second space. The present disclosure also provides a method for fabricating the fully capped gate structure described herein.)

1. A fully wrapped-around gate structure, comprising:

A semiconductor fin having a top surface;

A first nanowire over the top surface;

A first space between the top surface and the first nanowire;

An Nth nanowire and an (N +1) th nanowire above the first nanowire, N being an integer greater than 1; and

A second space between the Nth nanowire and the (N +1) th nanowire;

Wherein the first space is larger than the second space.

Technical Field

The embodiment of the invention relates to a fully-wrapped grid structure and a manufacturing method thereof.

Background

A transistor, such as a FinFET transistor, includes a source region, a drain region, and a channel region between the source and drain regions. The transistor includes a gate region that controls the channel region to operate the transistor. The gate region may be formed around one or more surfaces of the channel region, which provides enhanced control of the channel region for the gate region since the transistor may be controlled by the 3D gate region (rather than just the 2D gate region associated with a 2D planar transistor).

Disclosure of Invention

According to an embodiment of the present invention, a fully-wrapped-gate structure includes: a semiconductor fin having a top surface; a first nanowire over the top surface; a first space between the top surface and the first nanowire; an Nth nanowire and an (N +1) th nanowire above the first nanowire, N being an integer greater than 1; and a second space between the nth nanowire and the (N +1) th nanowire; wherein the first space is larger than the second space.

According to an embodiment of the present invention, a semiconductor structure comprises: a P-type transistor, comprising: a semiconductor fin having a top surface; a first SiGe nanowire over the top surface of the semiconductor fin; a second SiGe nanowire, an Nth SiGe nanowire and an (N +1) th SiGe nanowire, which are above the first SiGe nanowire, wherein N is an integer greater than 1; a first space between the first SiGe nanowire and the second SiGe nanowire; and a second space between the nth SiGe nanowire and the (N +1) th SiGe nanowire; wherein the first space is larger than the second space.

According to an embodiment of the present invention, a method for forming a fully-wrapped-around gate structure comprises: forming a first nanowire material and a second nanowire material stack over a top surface of a substrate; patterning the first and second nanowire material stacks and the substrate to form semiconductor fins separated from each other by isolations; forming a dummy gate orthogonally over the semiconductor fin; selectively removing the first nanowire material not covered by the dummy gate, thereby exposing a second nanowire at a source/drain region; removing the dummy gate; and selectively removing the first nanowire material previously covered by the dummy gate, thereby exposing the second nanowire at a channel region.

Drawings

One or more embodiments are depicted by way of example, and not limitation, in the figures of the accompanying drawings in which elements having the same reference number designation represent similar elements throughout. Unless otherwise disclosed, the drawings are not to scale.

fig. 1 is a cross-sectional view showing an interface at an epitaxial stack of a semiconductor structure.

Fig. 2A is a diagram showing the thickness of an interface at an epitaxial stack of the semiconductor structure in fig. 1.

Fig. 2B is a diagram showing the thickness of an interface at an epitaxial stack of the semiconductor structure in fig. 1.

Fig. 3A and 3B are cross-sectional views in the X-direction of a PFET and an NFET, respectively, according to some embodiments of the present disclosure.

Figure 4 is a cross-sectional view at a channel region of a GAA structure according to some embodiments of the present disclosure.

Figure 5 is a cross-sectional view at a source/drain region of a GAA structure according to some embodiments of the present disclosure.

Fig. 6-14 are cross-sectional views during intermediate stages of a manufacturing operation, according to some embodiments of the present disclosure.

Detailed Description

The making and using of embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. Reference will now be made in detail to the exemplary embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the detailed description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This particular embodiment will particularly relate to elements forming part of, or cooperating more directly with, apparatus in accordance with the present disclosure. It is to be understood that elements not explicitly shown or described may take various forms. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that the following drawings are not to scale; rather, these figures are intended to be illustrative only.

Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The fully-wrapped-Gate (GAA) structure includes two key operations that are highly correlated with device yield and performance: epitaxial stack formation and epitaxial stack etching for nanowire release. In conventional GAA operations, epitaxial stack formation includes forming alternating layers of first nanowire material and second nanowire material, where the layers of first nanowire material have substantially the same thickness as the thickness of the second nanowire material. However, it was observed that after the nanowire release operation, the first nanowire released from the second nanowire material layer had different thicknesses depending on the level of the first nanowire. For example, it has generally been observed that the bottom nanowire closest to the top surface of the substrate has a thickness that is less than the top nanowire furthest from the top surface of the substrate. In other words, if alternating layers of first and second nanowire materials are initially epitaxially deposited at equal thicknesses, each of the nanowires has a different thickness after nanowire release. Variations in the thickness of the nanowires in the same device can have a detrimental effect on the gate control capability.

Referring to fig. 1, two types of interfaces a and B in alternating first and second nanowire material layers 100A and 100B may be identified. The alternating stacks are positioned over the substrate 100. The first type of interface a is an interface with a first layer of nanowire material 100A at the bottom and a second layer of nanowire material 100B at the top, and vice versa a second type of interface B. The first nanowire material layer 100A and the second nanowire material layer 100B have equal thicknesses when deposited.

As shown in fig. 2A, Secondary Ion Mass Spectrometry (SIMS) was performed at interface a to measure the thickness of interface a. In some embodiments, the aforementioned thickness of interface a is defined as a thickness encompassing 8 to 42 atomic percent of the first nanowire material. The first interface, as indicated by the X-axis of fig. 2A, is located furthest from the top surface of the substrate 100 underlying all of the layer of nanowire material, and the fifth interface is located closest to the top surface of the substrate 100. It was observed that the fifth interface (about 1.43nm) was thicker than the first interface (about 1.27 nm).

As shown in fig. 2B, Secondary Ion Mass Spectrometry (SIMS) was performed at the interface B to measure the thickness of the interface B. In some embodiments, the aforementioned thickness of interface B is defined as a thickness encompassing 8 to 42 atomic percent of the second nanowire material. The first interface, as indicated by the X-axis of fig. 2B, is located furthest from the top surface of the substrate underlying all of the layer of nanowire material, and the fifth interface is located closest to the top surface of the substrate. It was observed that the fifth interface (about 1.05nm) was thicker than the first interface (about 0.98nm), but the thickness of the fifth interface at interface B (about 1.05nm) was thinner than the fifth interface at interface a (about 1.43 nm).

According to the results shown in fig. 2A and 2B, the closer the interface is to the top surface of the substrate, the greater the interface thickness, whether interface a or interface B. This is due to the fact that: during epitaxial stack formation, the second nanowire material closer to the top surface of the substrate has a greater diffusion length at a greater thermal budget. For example, the first and second nanowire material layers of the bottom pair are subjected to prolonged high temperature exposure as compared to the high temperature exposure of the first and second nanowire material layers of the top pair. Thus, after an epitaxial stack etch for nanowire release is performed, an epitaxial stack with a thicker interface will produce a thinner nanowire, and an epitaxial stack with a thinner interface will produce a thicker nanowire. In other words, the thickness of the nanowire after nanowire release exhibits a varying thickness, in the sense that the nanowire closer to the top surface of the underlying substrate is thinner and the nanowire further from the top surface of the underlying substrate is thicker.

therefore, a new structure for solving the problem of the thickness variation of the nanowire is required. The structure provided in the present disclosure introduces a new epitaxial stack having: 1) a first layer of a first nanowire material over a top surface of the semiconductor substrate, the first layer of the first nanowire material having a first thickness; 2) a first layer of a second nanowire material over the first layer of the first nanowire material, the first layer of the second nanowire material having a second thickness; 3) an nth layer of the first nanowire material over the first layer of the second nanowire material, the nth layer of the first nanowire material having a third thickness; 4) an nth layer of a second nanowire material over the nth layer of the first nanowire material, the nth layer of the second nanowire material having a fourth thickness; 5) an N +1 th layer of the first nanowire material over the nth layer of the second nanowire material, the N +1 th layer of the first nanowire material having a fifth thickness; 6) an N +1 th layer of second nanowire material over the N +1 th layer of first nanowire material, the N +1 th layer of second nanowire material having a sixth thickness. The first thickness is greater than the third thickness, and the third thickness is greater than the fifth thickness. The second thickness is greater than the fourth thickness, and the fourth thickness is greater than the sixth thickness.

The new structures disclosed herein provide greater dimensional uniformity with respect to the size of the Si and/or silicon germanium nanowires in the final product, and thus better gate control is obtained. Furthermore, since the spacing between vertically adjacent nanowires at the bottom is greater than the spacing between vertically adjacent nanowires at the top of the epitaxial stack after nanowire release, loading effects caused by metal gate fill that occur at the bottom nanowire can also be mitigated.

Several material systems are currently known in the art for fully-wrapped-gate MOSFETs, including group III and group V materials, and are intended to be within the intended scope of the present disclosure. For example, on silicon substrates, Si nanowires for NFETs and SiGe nanowires for PFETs are commonly employed. On GaAs substrates, GaAs nanowires for NFETs and InGaAs nanowires for PFETs are generally employed. On a Ge/GaAs substrate, Ge nanowires for NFETs and GaAs nanowires for PFETs are generally employed. For the sake of brevity, the present disclosure provides illustration and detailed description only with Si nanowire and SiGe nanowire material systems. The same inventive concept may be applied to different semiconductor material systems under discussion.

Referring to fig. 3A and 3B, fig. 3A and 3B are top views showing a non-planar semiconductor structure and a separation line in different locations, according to some embodiments of the present disclosure. In fig. 3A, active regions 20A and 20B are depicted as two parallel stripes. In embodiments describing a fully wrapped-gate MOSFET structure, the active region includes a doped region of a patterned semiconductor substrate, and a nanowire channel over the patterned semiconductor substrate. In the following disclosure, the active region 20A may include portions of PMOS transistor structures and the active region 20B may include portions of NMOS transistor structures. In the present disclosure, the digital label 20A may generally refer to an active region having a PMOS transistor structure, and the digital label 20B may generally refer to an active region having an NMOS transistor structure. Two gates 200 and 200 'are disposed orthogonally over the active regions 20A and 20B, being adjoined at gate 200 by source/drain regions 201A, 201B, and at gate 200' by source/drain regions 201A ', 201B'. A cut line AA' passes through the gate 200 in a longitudinal direction of the gate 200, thereby showing a cross-section of the gate 200 and the underlying active regions 20A and 20B in subsequent fig. 4. Similarly, in fig. 3B, active regions 20A and 20B are depicted as two parallel stripes. In the following disclosure, the active region 20A may be a PMOS transistor structure, and the active region 20B may be an NMOS transistor structure. Two gates 200 and 200 'are disposed orthogonally over the active regions 20A and 20B, being adjoined at gate 200 by source/drain regions 201A, 201B, and at gate 200' by source/drain regions 201A ', 201B'. A cut line BB' passes through the source/drain regions 201A, 201B, thereby showing a cross-section of the source/drain regions 201A, 201B and the underlying active regions 20A and 20B in subsequent fig. 5.

Referring to fig. 4, fig. 4 is a cross-sectional view of a semiconductor structure 40 divided along the dividing line AA' of fig. 3, according to some embodiments of the present disclosure. Semiconductor structure 40 includes PMOS20A and NMOS 20B. In some embodiments, PMOS20A may or may not be disposed adjacent to NMOS 20B.

The semiconductor structure 40 includes a substrate 100 patterned into at least two semiconductor fins 100A, 100B. In some embodiments, the substrate 100 includes silicon, and the substrate 100 is formed according to a FinFET arrangement that includes one or more silicon fins separated by isolation structures 103, such as Shallow Trench Isolations (STI). For example, a first fin 100A and a second fin 100B are formed from the substrate 100 and have a top surface 100T at each of the fins 100A, 100B. In some embodiments, an n-type dopant (e.g., phosphorus) is applied by an Anti-punch through (APT) implant to form an APT region (not shown in fig. 4) proximate to top surface 100T in PMOS 20A. In some embodiments, an APT (not shown in fig. 4) proximate to top surface 100T in NMOS20B is formed with a p-type dopant, such as boron, by another APT implant.

Still referring to fig. 4, the PMOS20A further includes a plurality of SiGe nanowires 101A, 102A, 103A, 104A, 105A along the longitudinal direction of the first fin 100A, connecting source/drains 201A (shown in fig. 5) at both ends of the SiGe nanowires 101A, 102A, 103A, 104A, 105A. Among all the SiGe nanowires, 101A is referred to as a first SiGe nanowire, which is the nanowire closest to the top surface 100T of the semiconductor fin 100A. Of all the SiGe nanowires, 105A is referred to as the fifth SiGe nanowire, which is the nanowire farthest from the top surface 100T of the semiconductor fin 100A. Although only five SiGe nanowires are depicted in fig. 4, the number of nanowires above the top surface 100T of the semiconductor fin 100A is not so limited. Any number compatible with device design and technology is within the scope of the present disclosure. In some embodiments, the first SiGe nanowire is not necessarily the nanowire closest to the top surface 100T. In other words, the first SiGe nanowire may be second or third near the top surface 100T as long as the so-called second SiGe nanowire is further from the top surface 100T than the first SiGe nanowire.

In some embodiments, the space between the top surface 100T and the first SiGe nanowire 101A is denoted as S1, the space between the first SiGe nanowire 101A and the second SiGe nanowire 102A is denoted as S2, the space between the second SiGe nanowire 102A and the third SiGe nanowire 103A is denoted as S3, the space between the third SiGe nanowire 103A and the fourth SiGe nanowire 104A is denoted as S4, and the space between the fourth SiGe nanowire 104A and the fifth SiGe nanowire 105A is denoted as S5. In the present disclosure, the space S1 is larger than any one of the spaces S2, S3, S4, and S5. Space S2 is larger than any of spaces S3, S4, and S5. Space S3 is larger than either of spaces S4 and S5. Space S4 is larger than space S5. In some embodiments, space S1 is greater than space S2, space S2 is then greater than space S3, space S3 is then greater than space S4, and space S4 is then greater than space S5. In some embodiments, the gate 200 is filled between adjacent SiGe nanowires 101A, 102A, 103A, 104A, 105A and between the top surface 100T and the bottom SiGe nanowire 101A.

In the naming convention provided above, the space between the nth and N +1 th SiGe nanowires is denoted as S (N + 1). In some embodiments, when N is equal to or greater than 6, S (N +1) is at least 1nm greater than S1. In some embodiments, when N is equal to or greater than 6, S (N +1) is at least greater than S1 by a range from about 0.5nm to about 1.5 nm.

In some embodiments, the thickness of the first SiGe nanowire 101A is denoted as T1, the thickness of the second SiGe nanowire 102A is denoted as T2, the thickness of the third SiGe nanowire 103A is denoted as T3, the thickness of the fourth SiGe nanowire 104A is denoted as T4, and the thickness of the fifth SiGe nanowire 105A is denoted as T5. In the present disclosure, the thickness T1 is substantially the same as any of the thicknesses T2, T3, T4, and T5. In some embodiments, the thickness of the SiGe lines 101A-105A is measured at a defined boundary between the SiGe and the metal gate material.

Similarly, the NMOS20B further includes a plurality of Si nanowires 101B, 102B, 103B, 104B, 105B along the longitudinal direction of the second fin 100B, connecting source/drains 201B (shown in fig. 5) at both ends of the Si nanowires 101B, 102B, 103B, 104B, 105B. Among all Si nanowires, 101B is referred to as the first Si nanowire, which is the nanowire closest to the top surface 100T of the semiconductor fin 100B. Of all the Si nanowires, 105B is referred to as the fifth Si nanowire, which is the nanowire farthest from the top surface 100T of the semiconductor fin 100B. Although only five Si nanowires are depicted in fig. 4, the number of nanowires above the top surface 100T of the semiconductor fin 100B is not so limited. Any number compatible with device design and technology is within the scope of the present disclosure. In some embodiments, the first Si nanowire does not have to be the nanowire closest to the top surface 100T. In other words, the first Si nanowire may be second or third close to the top surface 100T as long as the so-called second Si nanowire is farther from the top surface 100T than the first Si nanowire.

in some embodiments, the space between the top surface 100T and the first Si nanowire 101B is denoted as S1', the space between the first Si nanowire 101B and the second Si nanowire 102B is denoted as S2', the space between the second Si nanowire 102B and the third Si nanowire 103B is denoted as S3', the space between the third Si nanowire 103B and the fourth Si nanowire 104B is denoted as S4', and the space between the fourth Si nanowire 104B and the fifth Si nanowire 105B is denoted as S5 '. In the present disclosure, the space S1' is greater than any of the spaces S2', S3', S4' and S5 '. The space S2 'is larger than any of the spaces S3', S4', and S5'. The space S3' is larger than either of the spaces S4' and S5 '. The space S4 'is larger than the space S5'. In some embodiments, space S1 'is greater than space S2', space S2 'is then greater than space S3', space S3 'is then greater than space S4', and space S4 'is then greater than space S5'. In some embodiments, a gate 200' is filled between adjacent Si nanowires 101B, 102B, 103B, 104B, 105B and between the top surface 100T and the bottom Si nanowire 101B.

In the naming convention provided above, the space between the nth Si nanowire and the N +1 th Si nanowire is denoted as S (N + 1)'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least 0.5nm greater than S1'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least greater than S1' by a range from about 0.5nm to about 1.5 nm.

In some embodiments, the thickness of the first Si nanowire 101B is denoted as T1', the thickness of the second Si nanowire 102B is denoted as T2', the thickness of the third Si nanowire 103B is denoted as T3', the thickness of the fourth Si nanowire 104B is denoted as T4', and the thickness of the fifth Si nanowire 105B is denoted as T5 '. In the present disclosure, the thickness T1' is substantially the same as any of the thicknesses T2', T3', T4' and T5 '. In some embodiments, the thickness of the Si lines 101B-105B is measured at a defined boundary between Si and the metal gate material.

Referring to fig. 5, fig. 5 is a cross-sectional view of a semiconductor structure 50 divided along a dividing line BB' of fig. 3B, according to some embodiments of the present disclosure. Semiconductor structure 50 includes PMOS20A and NMOS 20B. In some embodiments, PMOS20A may or may not be disposed adjacent to NMOS 20B. The same reference numerals in fig. 5 and 4 refer to the same components or their equivalents and are not repeated here for the sake of brevity. In fig. 5, the source/drain 201A of PMOS20A surrounds SiGe nanowires 101A, 102A, 103A, 104A, while the source/drain 201B of NMOS20B surrounds Si nanowires 101B, 102B, 103B, 104B and barrier layer 110B. As shown in fig. 5, the profile of the source/drain 201A or 201B shows faceted sidewalls according to each nanowire.

The semiconductor structure 50 includes a substrate 100 patterned into at least two semiconductor fins 100A, 100B. In some embodiments, the substrate 100 includes silicon, and the substrate 100 is formed according to a FinFET arrangement that includes one or more silicon fins separated by isolation structures 103, such as Shallow Trench Isolations (STI). For example, a first fin 100A and a second fin 100B are formed from the substrate 100 and have a top surface 100T at each of the fins 100A, 100B. In some embodiments, an anti-punch through (APT) region (not shown in fig. 5) proximate to top surface 100T in PMOS20A is formed with an n-type dopant, such as phosphorus, by the APT implant. In some embodiments, an APT (not shown in fig. 5) proximate to top surface 100T in NMOS20B is formed with a p-type dopant, such as boron, by another APT implant.

Referring to fig. 5, the NMOS20B further includes a plurality of Si nanowires 101B, 102B, 103B, 104B along the longitudinal direction of the second fin 100B, which connect source/drains 201B at both ends of the Si nanowires 101B, 102B, 103B, 104B. Among all Si nanowires, 101B is referred to as the first Si nanowire, which is the nanowire closest to the top surface 100T of the semiconductor fin 100B. Among all the Si nanowires, 104B is referred to as a fourth Si nanowire, which is the nanowire farthest from the top surface 100T of the semiconductor fin 100B. Although only four Si nanowires are depicted in fig. 5, the number of nanowires above the top surface 100T of the semiconductor fin 100B is not limited thereto. Any number compatible with device design and technology is within the scope of the present disclosure. In some embodiments, the first Si nanowire does not have to be the nanowire closest to the top surface 100T. In other words, the first Si nanowire may be second or third close to the top surface 100T as long as the so-called second Si nanowire is farther from the top surface 100T than the first Si nanowire.

in some embodiments, the space between the top surface 100T and the first Si nanowire 101B is denoted as S1', the space between the first Si nanowire 101B and the second Si nanowire 102B is denoted as S2', the space between the second Si nanowire 102B and the third Si nanowire 103B is denoted as S3', and the space between the third Si nanowire 103B and the fourth Si nanowire 104B is denoted as S4'. In the present disclosure, the space S1 'is larger than any one of the spaces S2', S3 'and S4'. The space S2' is larger than either of the spaces S3' and S4 '. The space S3 'is larger than the space S4'. In some embodiments, space S1 'is larger than space S2', space S2 'is then larger than space S3', and space S3 'is then larger than space S4'. In some embodiments, source/drains 201B are filled between adjacent Si nanowires 101B, 102B, 103B, 104B and between the top surface 100T and the first Si nanowire 101B.

In the naming convention provided above, the space between the nth Si nanowire and the N +1 th Si nanowire is denoted as S (N + 1)'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least 1nm greater than S1'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least greater than S1' by a range from about 0.5nm to about 1.5 nm.

In some embodiments, the thickness of the first Si nanowire 101B is denoted as T1', the thickness of the second Si nanowire 102B is denoted as T2', the thickness of the third Si nanowire 103B is denoted as T3', and the thickness of the fourth Si nanowire 104B is denoted as T4'. In the present disclosure, the thickness T1 'is substantially the same as any of the thicknesses T2', T3', and T4'. In some embodiments, the thickness of the Si lines 101B-104B is measured at a defined boundary between the Si and the source/drain material 201B.

Similarly, the PMOS20A further includes a plurality of SiGe nanowires 101A, 102A, 103A, 104A along the longitudinal direction of the first fin 100A, which connect the source/drain 201A at both ends of the SiGe nanowires 101A, 102A, 103A, 104A. Among all the SiGe nanowires, 101A is referred to as a first SiGe nanowire, which is the nanowire closest to the top surface 100T of the semiconductor fin 100A. Among all the SiGe nanowires, 104A is referred to as a fourth SiGe nanowire, which is the nanowire farthest from the top surface 100T of the semiconductor fin 100A. Although only four SiGe nanowires are depicted in fig. 5, the number of nanowires above the top surface 100T of the semiconductor fin 100A is not limited thereto. Any number compatible with device design and technology is within the scope of the present disclosure. In some embodiments, the first SiGe nanowire does not have to be the nanowire closest to the top surface 100T. In other words, the first SiGe nanowire may be second or third near the top surface 100T as long as the so-called second SiGe nanowire is farther from the top surface 100T than the first SiGe nanowire.

In the naming convention provided above, the space between the nth and N +1 th SiGe nanowires is denoted as S (N + 1). In some embodiments, when N is equal to or greater than 6, S (N +1) is at least 1nm greater than S1. In some embodiments, when N is equal to or greater than 6, S (N +1) is at least greater than S1 by a range from about 0.5nm to about 1.5 nm.

In some embodiments, the thickness of the first SiGe nanowire 101A is denoted as T1, the thickness of the second SiGe nanowire 102A is denoted as T2, the thickness of the third SiGe nanowire 103A is denoted as T3, and the thickness of the fourth SiGe nanowire 104A is denoted as T4. In the present disclosure, the thickness T1 is substantially the same as any of the thicknesses T2, T3, and T4. In some embodiments, the thickness of the SiGe lines 101A-104A is measured at a defined boundary between the SiGe and the source/drain material 201A.

Fig. 6-14 are cross-sectional views showing intermediate operations in fabricating semiconductor structures, according to some embodiments of the present disclosure. For overall purposes, the left side of substrate 100 shows the fabrication operations of PMOS20A, and the right side of substrate 100 shows the fabrication operations of NMOS 20B. In fig. 6, a sacrificial layer 1003 is formed over the top surface 100T of the substrate 100. In some embodiments, the sacrificial layer 1003 may be an oxide or nitride deposited by CVD, PVD, or other suitable method. In PMOS20A, a first implant operation 1001 is performed to form an n-type well 1001A extending downward from top surface 100T. In some embodiments, the first implanted energetic dopant penetrates the sacrificial layer 1003 and into the substrate 100. Similarly, in NMOS20B, a second implant operation 1001' is performed to form a p-type well 1001B extending downward from top surface 100T. Masking or photoresist patterning is performed between the first and second implants to form n-type well 1001A and p-type well 1001B, respectively, and is omitted here for simplicity. In addition, forming the p-type well 1001B does not necessarily have to be an operation immediately after forming the n-type well 1001A. In some embodiments, the operations for fabricating PMOS20A may be performed before the operations for fabricating NMOS 20B. In some embodiments, the operations for fabricating PMOS20A may be performed in turn with the operations for fabricating NMOS 20B.

In fig. 7, a first anti-punch through (APT) implant operation 1002 is performed to provide an n-type dopant, such as phosphorus or arsenic, into the first APT region 101P in PMOS 20A. First APT region 101P is shallower than n-type well 1001A and is proximate to top surface 100T. A second anti-punch-through (APT) implant operation 1002 'is performed to provide a P-type dopant, such as boron, into the second APT region 101P' in the NMOS 20B. The second APT region 101P' is shallower than the P-type well 1001B and is proximate to the top surface 100T. Both the first APT region 101P and the second APT region 101P' underlie the sacrificial layer 1003 and abut the sacrificial layer 1003. In fig. 12, the sacrificial layer 1003 is removed from the top surface 100T of the semiconductor substrate 100 in PMOS20A and NMOS20B by an oxide or nitride strip operation.

In fig. 8, a first channel material and a second channel material stack are formed over the top surface 100T. For example, silicon and silicon germanium stacks 140 are formed over barrier layers 110A, 110B. For example, a first silicon and silicon germanium stack will be formed over the substrate 100. The first silicon and silicon germanium stack includes one or more silicon layers and one or more silicon germanium layers. For example, a first silicon and silicon germanium stack comprises a first silicon germanium layer 101A, a first silicon layer 101B, a second silicon germanium layer 102A, a second silicon layer 102B, a third silicon germanium layer 103A, a third silicon layer 103B, and so on. It should be appreciated that any number of silicon layers or silicon germanium layers may be formed. In one example, the silicon germanium layer includes between about 20% and about 75% germanium. Alternatively, at least one of the sige layers 101A, 102A, 103A, 104A, 105A may be replaced by a pure ge layer. The silicon and silicon germanium stack 140 and substrate 100 are then patterned to form semiconductor fins 100A and 100B, which are separated by STI103, as shown in fig. 9. In some embodiments, the at least one liner 1001 is formed after patterning the silicon and silicon germanium stack 140 and the substrate 100. For example, the at least one liner 1001 may be comprised of a nitride material. Subsequently, STI103 is disposed to fill the trench between semiconductor fins 100A and 100B. Optionally, an etch-back operation comprising fluorine gas is performed to create an appropriate height for the STI103, e.g., a height that allows silicon and silicon germanium stacked fins fabricated with the silicon and silicon germanium stacks 140 to be exposed and cover the underlying bulk fins derived from the substrate 100. In some embodiments, a wet etch is performed to remove at least a portion of the liner 1001 previously deposited at the sidewalls of the silicon and silicon germanium stacked fins, e.g., for removing nitride material.

As shown in fig. 8, silicon and silicon germanium stacks 140 are deposited with various thicknesses. For example, as-deposited thickness D1 of sige layer 101A is different from thickness D2 of as-deposited sige layer 102A, thickness D3 of as-deposited sige layer 103A, thickness D4 of as-deposited sige layer 104A, and thickness D5 of as-deposited sige layer 105A. In particular, the thickness D1 is designed to be greater than any of D2, D3, D4, and D5. In some embodiments, the thickness D1 is designed to be greater than D2, D2 is greater than D3, D3 is greater than D4, and D4 is greater than D5.

In the naming convention provided above, the thickness of the nth sige layer is denoted as DN. In some embodiments, when N is equal to or greater than 6, DN is at least 1.5nm greater than D1. In some embodiments, when N is equal to or greater than 6, DN is at least greater than D1 by a range from about 1.5nm to about 2.0 nm.

Similarly, the thickness D1' of the as-deposited silicon 101B is different from the thickness D2' of the as-deposited silicon layer 102B, the thickness D3' of the as-deposited silicon layer 103B, the thickness D4' of the as-deposited silicon layer 104B, and the thickness D5' of the as-deposited silicon layer 105B. In particular, the thickness D1' is designed to be greater than any of D2', D3', D4', and D5 '. In some embodiments, thickness D1 'is designed to be greater than D2', D2 'greater than D3', D3 'greater than D4', and D4 'greater than D5'.

In the naming convention provided above, the thickness of the nth silicon layer is denoted DN'. In some embodiments, when N is equal to or greater than 6, DN 'is at least 1.5nm greater than D1'. In some embodiments, when N is equal to or greater than 6, DN 'is at least a range from about 1.5nm to about 2.0nm greater than D1'.

In fig. 10, an input/output (I/O) oxide layer 150 is conformally formed over portions of fins 100A, 100B, patterned silicon and silicon germanium stack 140, and the top surface of STI 103. After forming the input/output (I/O) oxide layer 150, a dummy gate 160 is formed orthogonally across the first and second fins 100A, 100B by a subsequent patterning operation. The dummy gate 160 is a sacrificial gate, such as a polysilicon gate (polygate), formed by patterning techniques to protect the gate or channel region from the formation of the source/drains 201A, 201B. In some embodiments, the source/drains 201A, 201B may be comprised of SiGeB or SiP. The source/drain 201A, 201B may have facet boundaries due to limited epitaxial growth in certain specific crystal directions (crystallographic).

In some embodiments, under the protection of the dummy gate 160, the silicon and silicon germanium stacks 140 at the source/drain regions may be completely removed before forming the source/drains 201A, 201B in the recesses created by removing the silicon and silicon germanium stacks 140. In some embodiments, the silicon and silicon germanium stacks 140 at the source/drain regions are neither released nor removed prior to forming the source/drains 201A, 201B under the protection of the dummy gate 160. In other words, source/drain material is deposited over the silicon and silicon germanium stacks 140 at the source/drain regions.

In some embodiments, the dummy gate 160 is used as a hard mask for a subsequent first nanowire release operation at the source/drain regions (not shown in fig. 10) prior to formation of the source/drains 201A, 201B under protection of the dummy gate 160. When the silicon germanium nanowires in the PMOS are first released, the silicon-based material will be removed by an appropriate etchant. On the other hand, when the silicon nanowires in the corresponding NMOS are released, the silicon germanium-based material will be removed by an appropriate etchant. After the first nanowire release operation in the PMOS and corresponding NMOS, source/drains 201A, 201B are then formed at both ends of the release nanowire (not shown in this disclosure). Alternatively, the release nanowires are in the source/drains 201A, 201B.

Fig. 11 and 12 show a second nanowire release operation at the channel regions of PMOS20A and NMOS 20B. The second nanowire release operation is performed at the channel region initially covered by the dummy gate 160 as compared to the first nanowire release operation, which is performed at the source/drains 201A, 201B not covered by the dummy gate 160 and which utilizes the dummy gate 160 as a hard mask. In fig. 11, a hard mask 170 is disposed over PMOS20A and exposes NMOS20B to a silicon nanowire release operation. As previously discussed, utilizing an appropriate etchant to release the Si nanowires 101B, 102B, 103B, 104B, 105B has a lower selectivity to silicon-based materials and a greater selectivity to non-silicon-based materials (e.g., silicon-germanium-based materials). As shown in fig. 11, the released Si nanowires 101B, 102B, 103B, 104B, 105B each have thicknesses T1', T2', T3', T4', and T5', respectively. After the silicon nanowire is released, the thicknesses of the Si nanowire T1', T2', T3', T4' and T5 'are different from the thicknesses D1', D2', D3', D4 'and D5' of the as-deposited silicon layer 101B, 102B, 103B, 104B, 105B. For example, thickness T1 'is greater than thickness D1'. In some embodiments, the thicknesses D1', D2', D3', D4' and D5 'of the silicon layers 101B, 102B, 103B, 104B, 105B follow the relationship of D1' > D2'> D3' > D4'> D5, while the thicknesses T1', T2', T3', T4 'and T5' of the released Si nanowires follow a substantially equal relationship to each other.

As shown in fig. 11, the released Si nanowires 101B, 102B, 103B, 104B, 105B each have a spacing S1', S2', S3', S4', and S5' respectively from their neighboring Si nanowires. Due to the fact that the diffusion interface at the bottom of the silicon and silicon germanium stack 140 is thicker than the diffusion interface at the top thereof, the spacing S1 'near the bottom of the stack 140 appears to be greater than the spacing S5' away from the bottom of the stack 140. In some embodiments, spacings S1', S2', S3', S4', and S5 'follow the relationship S1' > S2'> S3' > S4'> S5'. In the naming convention provided above, the spacing between the nth and N +1 th Si nanowires is denoted as S (N + 1)'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least 1nm greater than S1'. In some embodiments, when N is equal to or greater than 6, S (N +1) 'is at least greater than S1' by a range from about 1nm to about 1.5 nm.

Similarly, in fig. 12, a hard mask 180 is disposed over NMOS20B and PMOS20A is exposed to a silicon germanium nanowire release operation. As previously discussed, the etchant used to release the SiGe nanowires 101A, 102A, 103A, 104A, 105A has a lower selectivity to silicon-germanium based materials and a greater selectivity to non-silicon-germanium based materials (e.g., silicon-based materials). As shown in fig. 12, the released SiGe nanowires 101A, 102A, 103A, 104A, 105A each have a thickness T1, T2, T3, T4, and T5, respectively. After SiGe nanowire release, the thicknesses T1, T2, T3, T4, and T5 of the SiGe nanowires are different from the thicknesses D1, D2, D3, D4, and D5 of the as-deposited silicon layers 101A, 102A, 103A, 104A, 105A. For example, thickness T1 is greater than thickness D1. In some embodiments, the thicknesses D1, D2, D3, D4, and D5 of the silicon layers 101A, 102A, 103A, 104A, 105A follow the relationship of D1> D2> D3> D4> D5, while the thicknesses T1, T2, T3, T4, and T5 of the released SiGe nanowires follow a substantially equal relationship to each other.

As shown in fig. 12, the released SiGe nanowires 101A, 102A, 103A, 104A, 105A each have a spacing S1, S2, S3, S4, and S5, respectively, from their neighboring SiGe nanowires. Due to the fact that the diffusion interface at the bottom of the silicon and silicon germanium stack 140 is thicker than the diffusion interface at the top thereof, the spacing S1 near the bottom of the stack 140 appears to be greater than the spacing S5 away from the bottom of the stack 140. In some embodiments, spacings S1, S2, S3, S4, and S5 follow the relationship S1> S2> S3> S4> S5. In the naming convention provided above, the spacing between the nth and N +1 th SiGe nanowires is denoted as S (N + 1). In some embodiments, when N is equal to or greater than 6, S (N +1) is at least 1nm greater than S1. In some embodiments, when N is equal to or greater than 6, S (N +1) is at least greater than S1 by a range from about 1nm to about 1.5 nm.

Fig. 13 shows the semiconductor structure 130 after removing the hard mask 180 in fig. 12. Subsequently, a gate material 200, 200' (or a replacement gate material) is deposited to fill the spaces between adjacent released nanowires as well as the spaces between the top surface 100T and the bottom SiGe nanowire 101A or the bottom Si nanowire 101B, as shown in fig. 14. In some embodiments, gate material fill is performed at PMOS20A before NMOS 20B. In other embodiments, gate material fill is performed at NMOS20B before PMOS 20A. In some embodiments, replacement gate materials including an interface layer material, a high dielectric coefficient layer, a titanium nitride cap/barrier layer, a work function metal layer, and a tungsten gate metal may be formed around and over a plurality of the released nanowires in PMOS20A and NMOS 20B.

Some embodiments provide a fully-wrapped-gate structure having: a semiconductor substrate having a top surface; a first nanowire over the top surface; a first space between the top surface and the first nanowire; an Nth nanowire and an (N +1) th nanowire over the first nanowire; and a second space between the nth nanowire and the (N +1) th nanowire. The first space is larger than the second space.

Some embodiments provide a semiconductor structure comprising a P-type transistor. The P-type transistor includes: a semiconductor substrate having a top surface; a first SiGe nanowire over the top surface of the semiconductor substrate; a second SiGe nanowire, an Nth SiGe nanowire and an (N +1) th SiGe nanowire above the first SiGe nanowire; a first space between the first SiGe nanowire and the second SiGe nanowire; and a second space between the nth SiGe nanowire and the (N +1) th SiGe nanowire. The first space is larger than the second space.

Some embodiments provide a method for fabricating a semiconductor structure, comprising: (1) forming a first nanowire material and a second nanowire material stack over a top surface of a substrate; (2) patterning the first and second nanowire material stacks and the substrate to form semiconductor fins separated from each other by isolations; (3) forming a dummy gate orthogonally over the semiconductor fin; (4) selectively removing the first nanowire material not covered by the dummy gate, thereby exposing a second nanowire at a source/drain region; (5) removing the dummy gate; and (6) selectively removing the first nanowire material previously covered by the dummy gate, thereby exposing the second nanowire at a channel region.

Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims. For example, many of the processes discussed above may be implemented in different ways and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present embodiments, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present embodiments. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Description of the symbols

20A active region/PMOS

20B active region/NMOS

40 semiconductor structure

50 semiconductor structure

100 substrate

100A first nanowire material layer (fig. 1)/semiconductor fin/first fin

100B second nanowire material layer (FIG. 1)/semiconductor fin/second fin

100T top surface

101A SiGe nanowire/first SiGe nanowire/bottom SiGe nanowire/SiGe wire/SiGe layer

101B Si nanowire/first Si nanowire/bottom Si nanowire/Si wire/silicon layer/silicon

101P first anti-punch through (APT) region

101P' second anti-punch through (APT) region

102A SiGe nanowire/second SiGe nanowire/SiGe wire/SiGe layer

102B Si nanowire/second Si nanowire/Si wire/silicon layer

103 isolation Structure/Shallow Trench Isolation (STI)

103A SiGe nanowire/third SiGe nanowire/SiGe wire/SiGe layer

103B Si nanowire/third Si nanowire/Si wire/silicon layer

104A SiGe nanowire/fourth SiGe nanowire/SiGe wire/SiGe layer

104B Si nanowire/fourth Si nanowire/Si wire/silicon layer

105A SiGe nanowire/fifth SiGe nanowire/SiGe wire/SiGe layer

105B Si nanowire/fifth Si nanowire/Si wire/silicon layer

130 semiconductor structure

140 silicon and silicon germanium stack

150 input/output (I/O) oxide layer

160 dummy gate

170 hard mask

180 hard mask

200 gate/gate material

200' gate/gate material

201A Source/Drain region/Source/Drain Material

201B Source/Drain region/Source/Drain Material

201A' Source/Drain region

201B' Source/Drain region

1001 first implant operation (figure 6)/liner

1001' second implantation operation

1002 first anti-punch-through (APT) implant operation

1002' second anti punch-through (APT) implant operation

Model 1001A n well

Model 1001B p well

1003 sacrificial layer

AA' parting line

BB' parting line

Thickness D1

Thickness D1

Thickness D2

Thickness D2

Thickness D3

Thickness D3

Thickness D4

Thickness D4

Thickness D5

Thickness D5

S1 space

Space S1

S2 space

Space S2

S3 space

Space S3

S4 space

Space S4

S5 space

Space S5

T1 thickness

Thickness T1

T2 thickness

Thickness T2

T3 thickness

Thickness T3

T4 thickness

Thickness T4

T5 thickness

Thickness T5