阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 周飞 于 2018-06-07 设计创作，主要内容包括：一种半导体结构及其形成方法,其中形成方法包括：提供基底,基底表面具有鳍部结构,鳍部结构沿鳍部结构高度方向上包括掺杂区,掺杂区鳍部结构包括多层堆叠的鳍部单元,鳍部单元包括第一鳍部和位于第一鳍部顶部的第二鳍部,第一鳍部和第二鳍部的材料不同,横跨鳍部结构的伪栅结构；在伪栅结构两侧的掺杂区鳍部结构内形成源漏开口；去除所述源漏开口侧壁的部分第一鳍部,在相邻第二鳍部之间形成第一开口；在第一开口内形成掺杂层,掺杂层内具有掺杂离子；进行退火处理,使掺杂离子进入第二鳍部内。所述方法形成的半导体器件性能较好。(A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a fin part structure, the fin part structure comprises a doped region along the height direction of the fin part structure, the fin part structure in the doped region comprises a plurality of layers of stacked fin part units, each fin part unit comprises a first fin part and a second fin part positioned at the top of the first fin part, the first fin part and the second fin part are made of different materials and cross a pseudo-gate structure of the fin part structure; forming source and drain openings in the doping region fin part structures on two sides of the pseudo gate structure; removing part of the first fin parts on the side walls of the source drain openings, and forming first openings between adjacent second fin parts; forming a doping layer in the first opening, wherein doping ions are arranged in the doping layer; and annealing to make the doped ions enter the second fin portion. The semiconductor device formed by the method has better performance.)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein the surface of the substrate is provided with a fin part structure, the fin part structure comprises a doped region along the height direction of the fin part structure, the fin part structure of the doped region comprises a plurality of layers of stacked fin part units, each fin part unit comprises a first fin part and a second fin part positioned at the top of the first fin part, the first fin part and the second fin part are made of different materials and cross over a pseudo-gate structure of the fin part structure;

Forming source and drain openings in the doping region fin part structures on two sides of the pseudo gate structure;

Removing part of the first fin parts on the side walls of the source drain openings, and forming first openings between adjacent second fin parts;

forming a doping layer in the first opening, wherein doping ions are arranged in the doping layer;

And annealing to make the doped ions enter the second fin portion and form a lightly doped region in the second fin portion.

2. The method of forming a semiconductor structure of claim 1, wherein the material of the doped layer comprises silicon; the doping concentration of the doping ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

3. The method of claim 1, wherein the dopant ions are N-type ions when the device being formed is an NMOS transistor; when the formed device is a PMOS transistor, the doped ions are P-type ions.

4. The method of forming a semiconductor structure of claim 1, wherein the annealing process comprises: spike annealing process; the parameters of the spike annealing process include: the annealing temperature is 900-1050 ℃.

5. The method of forming a semiconductor structure of claim 1, wherein a material of the first fin comprises silicon germanium or silicon carbide; the material of the second fin includes silicon, a group III-V element, InGaAs, or germanium.

6. The method for forming a semiconductor structure according to claim 5, wherein the process for forming the first opening includes a wet etching process; when the first fin portion is made of silicon germanium and the fin portion is made of silicon, parameters of the wet etching process include: the etchant comprises dilute hydrochloric acid, the volume concentration of the etchant is 20-90%, and the temperature is 25-300 ℃.

7. The method for forming the semiconductor structure according to claim 1, wherein the sidewall of the dummy gate structure has a sidewall structure.

8. The method of claim 7, wherein a dimension of the first opening is less than or equal to a dimension of the sidewall structure along an extension direction of the fin structure; along the extending direction of the fin structure, the size of the first opening is: 1 to 2 nanometers.

9. The method of forming a semiconductor structure of claim 7, wherein after forming the lightly doped region, the method further comprises: removing the doped layer; after the doping layer is removed, removing a part of the first fin parts exposed by the first openings, forming second openings between adjacent second fin parts, wherein the size of each second opening is smaller than or equal to that of the corresponding side wall structure in the extending direction of the fin part structure; forming an insulating layer in the second opening, wherein the side wall of the insulating layer is flush with the side wall of the dummy gate structure; forming a source drain doped region in the source drain opening after the insulating layer is formed; forming a dielectric layer on the surfaces of the substrate and the source-drain doped region and on the side wall of the pseudo gate structure, wherein the dielectric layer is exposed out of the top surface of the pseudo gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; removing the first fin part exposed by the pseudo gate opening to suspend the second fin part; and after removing the first fin part, forming a grid electrode structure surrounding the second fin part.

10. The method of forming a semiconductor structure according to claim 9, wherein a material of the insulating layer comprises silicon nitride or silicon oxynitride.

11. the method of forming a semiconductor structure of claim 9, wherein along the extending direction of the fin structure, the insulating layer has a dimension of: 2 to 5 nanometers.

12. the method of claim 1, wherein the fin structure further comprises an isolation region at a bottom of the doped region along a height direction of the fin structure; the forming method further includes: and forming an isolation structure on the surface of the substrate, wherein the top of the isolation structure is lower than that of the fin structure, and the isolation structure covers the side wall of the fin structure of the whole or partial isolation region.

13. A semiconductor structure, comprising:

A substrate;

A dummy gate structure on the substrate;

The dummy gate structure is arranged on the surface of the substrate and stretches across the fin structure, the fin structure comprises a doped region along the height direction of the fin structure, the fin structure of the doped region comprises multiple layers of stacked fin units, each fin unit comprises a first fin and a second fin positioned at the top of the first fin, the first fin and the second fin are made of different materials, the side wall of the first fin is recessed towards the dummy gate structure relative to the side wall of the second fin, and a first opening is formed between every two adjacent fins;

Source and drain openings in the doped region fin structure at two sides of the dummy gate structure;

And the doping layer is positioned in the first opening and is internally provided with doping ions.

14. The semiconductor structure of claim 13, wherein the dopant ions are N-type ions when the device formed is an NMOS transistor.

15. The semiconductor structure of claim 13, wherein the dopant ions are P-type ions when the device formed is a PMOS transistor.

16. The semiconductor structure of claim 13, wherein the material of the doped layer comprises silicon; the doping concentration of the doping ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

17. The semiconductor structure of claim 13, wherein sidewalls of the dummy gate structure have a sidewall structure; in the extending direction of the fin structure, the size of the first opening is smaller than or equal to that of the side wall structure; along the extending direction of the fin structure, the size of the first opening is: 1 to 2 nanometers.

18. The semiconductor structure of claim 13, wherein the fin structure further comprises an isolation region at a bottom of the doped region along a height direction of the fin structure; the semiconductor structure further comprises an isolation structure located on the surface of the substrate, wherein the top of the isolation structure is lower than the top of the fin structure, and covers the side wall of the fin structure of the whole or partial isolation region.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.

In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.

However, the performance of the semiconductor device formed by the prior art is poor.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.

To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a fin part structure, the fin part structure comprises a doped region along the height direction of the fin part structure, the doped region fin part structure comprises a plurality of layers of stacked fin part units, each fin part unit comprises a first fin part and a second fin part positioned at the top of the first fin part, the first fin part and the second fin part are made of different materials and cross a pseudo gate structure of the fin part structure; forming source and drain openings in the doping region fin part structures on two sides of the pseudo gate structure; removing part of the first fin parts on the side walls of the source drain openings, and forming first openings between adjacent second fin parts; forming a doping layer in the first opening, wherein doping ions are arranged in the doping layer; and annealing to make the doped ions enter the second fin portion.

Optionally, the material of the doped layer comprises silicon; the doping concentration of the doping ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

Optionally, when the formed device is an NMOS transistor, the doped ions are N-type ions; when the formed device is a PMOS transistor, the doped ions are P-type ions.

Optionally, the annealing process includes: spike annealing process; the parameters of the spike annealing process include: the annealing temperature is 900-1050 ℃.

Optionally, the material of the first fin portion includes silicon germanium or silicon carbide; the material of the second fin includes silicon, a group III-V element, InGaAs, or germanium.

optionally, the forming process of the first opening includes a wet etching process; when the first fin portion is made of silicon germanium and the second fin portion is made of silicon, parameters of the wet etching process include: the etchant comprises dilute hydrochloric acid, the volume concentration of the etchant is 20-90%, and the temperature is 25-300 ℃.

optionally, the sidewall of the dummy gate structure has a sidewall structure.

Optionally, in the extending direction of the fin structure, the size of the first opening is smaller than or equal to the size of the side wall structure; along the extending direction of the fin structure, the size of the first opening is: 1 to 2 nanometers.

optionally, after the annealing process, the forming method further includes: removing the doped layer; after the doping layer is removed, removing a part of the first fin parts exposed by the first openings, forming second openings between adjacent second fin parts, wherein the size of each second opening is smaller than or equal to that of the corresponding side wall structure in the extending direction of the fin part structure; forming an insulating layer in the second opening, wherein the side wall of the insulating layer is flush with the side wall of the dummy gate structure; forming a source drain doped region in the source drain opening after the insulating layer is formed; forming a dielectric layer on the surfaces of the substrate and the source-drain doped region and on the side wall of the pseudo gate structure, wherein the dielectric layer is exposed out of the top surface of the pseudo gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; after forming the pseudo gate opening, removing the first fin part to suspend the second fin part; and after removing the first fin part, forming a grid electrode structure surrounding the second fin part.

Optionally, the material of the insulating layer includes silicon nitride or silicon oxynitride.

Optionally, in the extending direction of the fin structure, the size of the insulating layer is: 2 to 5 nanometers.

optionally, the fin structure further includes an isolation region located at the bottom of the doped region along the height direction of the fin structure; the forming method further includes: and forming an isolation structure on the surface of the substrate, wherein the top of the isolation structure is lower than that of the fin structure, and covers the side wall of the fin structure of the whole or partial isolation region.

the present invention also provides a semiconductor structure comprising: a substrate; a dummy gate structure on the substrate; the dummy gate structure is arranged on the surface of the substrate and stretches across the fin structure, the fin structure comprises a doped region along the height direction of the fin structure, the doped region fin structure comprises multiple layers of stacked fin units, each fin unit comprises a first fin and a second fin positioned at the top of the first fin, the first fin and the second fin are made of different materials, the side wall of the first fin is recessed towards the dummy gate structure relative to the side wall of the second fin, and a first opening is formed between every two adjacent fins; source and drain openings in the doped region fin structure at two sides of the dummy gate structure; and the doping layer is positioned in the first opening and is internally provided with doping ions.

Optionally, when the formed device is an NMOS transistor, the doped ions are N-type ions.

Optionally, when the formed device is a PMOS transistor, the doping ions are P-type ions.

Optionally, the material of the doped layer comprises silicon; the doping concentration of the doping ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

optionally, the side wall of the dummy gate structure has a side wall structure; in the extending direction of the fin structure, the size of the first opening is smaller than or equal to that of the side wall structure; along the extending direction of the fin structure, the size of the first opening is: 1 to 2 nanometers.

optionally, the fin structure further includes an isolation region located at the bottom of the doped region along the height direction of the fin structure; the semiconductor structure further comprises an isolation structure located on the surface of the substrate, wherein the top of the isolation structure is lower than the top of the fin structure, and covers the side wall of the fin structure of the whole or partial isolation region.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

In the method for forming the semiconductor structure provided by the technical scheme of the invention, after the source/drain opening is formed, the first fin part on the side wall part of the source/drain opening is removed to form the first opening. The first opening is used for containing the doping layer in a follow-up mode, doping ions are arranged in the doping layer, and the doping ions enter the second fin portion through an annealing treatment process in a follow-up mode to form a light doping area. The annealing treatment has less loss to the second fin part, and is beneficial to improving the performance of the semiconductor device.

Furthermore, after the lightly doped region is formed, a second opening is formed at the bottom of the first opening, so that on one hand, the doped ions can be prevented from being too close to the channel region, and the doped ions are prevented from diffusing into the channel region and being communicated; on the other hand, the first opening and the second opening are used for subsequently accommodating the insulating layer, so that the size of the insulating layer in the extension direction of the second fin portion is larger, the distance between the subsequent source-drain doped region and the channel is longer, the parasitic capacitance is favorably reduced, and the performance of the semiconductor device is improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

Fig. 2 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background, the performance of semiconductor devices is poor.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, wherein a gate structure 101 is formed on a surface of the substrate 100; lightly doped regions 102 are formed in the substrate 100 on both sides of the gate structure 101.

In the above method, the forming process of the lightly doped region 102 includes an ion implantation process, and the ion implantation process includes ion implantation. Specifically, the method of the ion implantation process includes: the implanted ions enter the substrate 100 under the influence of a certain implantation energy. However, due to the existence of the implantation energy, the loss of the implanted ions to the substrate 100 is large, which is not favorable for improving the performance of the semiconductor device.

In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: after source and drain openings are formed, removing the first fin parts on the side wall parts of the source and drain openings, and forming first openings between the adjacent second fin parts; forming a doping layer in the first opening, wherein doping ions are arranged in the doping layer; and annealing to make the doped ions enter the second fin part to form a lightly doped region. The device formed by the method has better performance.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 2, an initial substrate 200 is provided; a plurality of stacked fin material units (not shown) are formed on the surface of the initial substrate 200, each fin material unit includes a first fin material layer 201 and a second fin material layer 202 located on top of the first fin material layer 201, and the second fin material layer 202 is made of a different material from the first fin material layer 201.

In this embodiment, the material of the initial substrate 200 is silicon. The cost of silicon is low, which is beneficial to reducing the manufacturing cost of the semiconductor device.

In other embodiments, the material of the initial substrate comprises germanium or silicon germanium.

A portion of the initial substrate 200 is used for a subsequent formation of the substrate, and a portion of the initial substrate 200, the first fin material layer 201, and the second fin material layer 202 are used for a subsequent formation of the fin structure. The first fin material layer 201 is used to form a first fin portion in the fin structure, and the second fin material layer 202 is used to form a second fin portion in the fin structure.

The alternating stacking of the first fin material layer 201 and the second fin material layer 202 means that: because the first fin material layer 201 and the second fin material layer 202 are made of different materials, the first fin material layer 201 is used for forming a first fin portion later, and the second fin material layer 202 is used for forming a second fin portion later, the first fin portion is removed later, a suspended second fin portion is formed, and a gate structure surrounding the second fin portion is formed.

The first fin material layer 201 and the second fin material layer 202 are made of different materials, and the first fin material layer 201 and the second fin material layer 202 have different etching selection ratios, so that the second fin is less damaged when a part of the first fin is removed subsequently.

In this embodiment, the material of the initial substrate 200 and the material of the second fin material layer 202 are silicon, and the material of the first fin material layer 202 is silicon germanium.

In other embodiments, the material of the first fin material layer includes: silicon carbide, the material of the second fin material layer comprising: group III-V elements, InGaAs, or germanium.

Referring to fig. 3 and 4, fig. 4 is a cross-sectional view taken along line C-C1 in fig. 3, and fig. 3 is a cross-sectional view taken along line D-D1 in fig. 4, wherein the initial substrate 200, the first fin material layer 201, and the second fin material layer 202 are patterned to form a substrate 203 and a fin structure (not shown) on the surface of the substrate 203, the fin structure including a doped region B along a height direction of the fin structure.

Fig. 3 corresponds to the cross-sectional direction of fig. 2.

The method for forming the substrate 203 and the fin structure comprises the following steps: forming a first mask layer (not shown) on top of the multi-layer stacked fin material units, the first mask layer exposing top surfaces of portions of the multi-layer stacked fin material units; and etching the fin material unit and part of the substrate 200 by taking the first mask layer as a mask to form a substrate 203 and a fin structure positioned on the surface of the substrate 203.

The material of the first mask layer comprises silicon nitride or titanium nitride. The first mask layer is used to form a mask for the substrate 203 and the fin structure.

The process for etching the fin material unit and part of the substrate 200 by using the first mask layer as a mask comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

The fin structure includes a fin unit (not shown), and the fin unit includes a first fin 204 formed by the first fin material layer 201 and a second fin 205 formed by the second fin material layer 202, so that the first fin 204 and the second fin 205 are made of different materials, and thus, in the subsequent process of removing the first fin 204, the damage to the second fin 205 is small, which is beneficial to improving the performance of the semiconductor device.

The fin structure further comprises an isolation region A located at the bottom of the doped region B along the height direction of the fin structure. The forming method further includes: an isolation structure 206 is formed on the surface of the substrate 203, wherein the top of the isolation structure 206 is lower than the top of the fin structure, and the isolation structure 206 covers the sidewalls of all or part of the fin structure of the isolation region a.

The method for forming the isolation structure 206 includes: forming isolation structure films on the surface of the substrate 203 and on the side wall and the top surface of the fin structure; part of the isolation structure film is removed to form the isolation structure 206.

The isolation structure film is made of silicon oxide or silicon oxynitride, and the isolation structure film is formed by a chemical vapor deposition process or a physical vapor deposition process.

The process for removing part of the isolation structure film comprises the following steps: one or two of the wet etching process and the dry etching process are combined.

The isolation structure 206 is used to achieve electrical isolation between semiconductor devices.

Referring to fig. 5, a dummy gate structure is formed across the fin structure.

the dummy gate structure comprises a dummy gate dielectric layer 209 covering the doped region B, a dummy gate layer 207 positioned on the surface of the dummy gate dielectric layer 209, and a sidewall structure 208 positioned on the sidewalls of the dummy gate dielectric layer 209 and the dummy gate layer 207.

the material of the dummy gate dielectric layer 209 comprises silicon oxide, and the material of the dummy gate layer 207 comprises silicon.

The sidewall structure 208 includes a first sidewall (not shown) on the sidewalls of the dummy gate dielectric layer 209 and the dummy gate layer 207, and a second sidewall (not shown) on the sidewall of the first sidewall. The first side wall is made of silicon nitride or silicon oxynitride, and the second side wall is made of silicon nitride or silicon oxynitride.

The sidewall structure 208 is used to define the position of the subsequent source/drain opening.

The top of the pseudo gate structure is provided with a second mask layer (not marked in the figure), and the material of the second mask layer comprises silicon nitride or titanium nitride. The second mask layer is used as a mask for forming the dummy gate layer 207 and the dummy gate dielectric layer 209.

referring to fig. 6, a source/drain opening 210 is formed in the doped region B fin structure on both sides of the gate structure and the sidewall structure 208 by using the gate structure 207 and the sidewall structure 208 as masks.

The forming process of the source and drain openings 210 includes: one or two of the dry etching process and the wet etching process are combined.

Since the source-drain opening 210 is located in the doped region B, the first fin portion 204 and the second fin portion 205 are exposed on the sidewall of the source-drain opening 210, which is beneficial to removing a portion of the first fin portion 204 subsequently, and forming a first opening between adjacent second fin portions 205.

The source drain opening 210 is used for subsequently accommodating a source drain doped region.

Referring to fig. 7, sidewall portions of the source/drain openings 210 of the first fin 204 are removed, and a first opening 211 is formed between adjacent second fins 205.

The process for removing the first fin 204 on the sidewall portion of the source/drain opening 210 includes a wet etching process.

In this embodiment, the parameters of the wet etching process include: the etchant comprises dilute hydrochloric acid, the volume concentration of the etchant is 20-90%, and the temperature is 25-300 ℃.

Since the first fin 204 and the second fin 205 are made of different materials, the etchant has different etching selectivity for the first fin 204 and the second fin 205, and the removal rate of the etchant for the first fin 204 is far greater than that for the second fin 205, so that the second fin 205 is less damaged after the first opening 211 is formed.

The dimension of the first opening 211 in the extending direction of the fin structure is: 1 nanometer to 2 nanometers, the significance of selecting the size of the first opening 211 along the extending direction of the fin structure is as follows: if the dimension of the first opening 211 along the extending direction of the fin structure is smaller than 1 nm, subsequent doping ions are difficult to dope to the position of a lightly doped region to be formed, which is not beneficial to improving the performance of the semiconductor device; if the dimension of the first opening 211 in the extending direction of the fin structure is greater than 2 nm, so that the subsequent doped ions are too close to the channel region, the doped ions are easy to diffuse into the channel region, a short channel effect is easy to occur, and the performance of the semiconductor device is not improved.

In the extending direction of the fin structure, the size of the first opening 211 is smaller than or equal to the size of the sidewall structure 208, which is beneficial to doping the doped ions into the position to be doped subsequently.

The first opening 211 is used for subsequently accommodating a doped layer.

Referring to fig. 8, a doped layer 212 is formed in the first opening 211 (see fig. 7), the doped layer 212 fills the first opening 211, and the doped layer 212 has doped ions therein; an annealing process is performed to diffuse the dopant ions into the second fin 205, thereby forming a lightly doped region (not shown).

In this embodiment, the doping layer 212 further covers the sidewalls of the second fin 205, the sidewalls and the bottom surfaces of the source and drain openings 210, and the sidewalls and the top surface of the dummy gate structure.

In other embodiments, the doped layer is only within the first opening.

The material of the doped layer 212 comprises silicon, and the doping concentration of the doped ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

The type of the dopant ions is related to the type of the transistor. In this embodiment, the transistor is an NMOS transistor, and thus, the dopant ions are N-type ions, such as: phosphorus ions or arsenic ions.

In other embodiments, the transistor is a PMOS transistor, and thus, the dopant ions are P-type ions, such as: boron ions.

the doped ions are physically doped in the doped layer 212, and then through an annealing process, the doped ions can diffuse out of the doped layer 212 and enter the second fin 205 to form a lightly doped region.

The annealing treatment process comprises the following steps: and (5) spike annealing process.

In this embodiment, the parameters of the spike annealing process include: the annealing temperature is 900-1050 ℃.

The annealing temperature is chosen in the sense that: if the annealing temperature is lower than 900 ℃, the diffusion rate of the doped ions into the to-be-formed lightly doped region is slower, so that the annealing time is longer, and the process efficiency is not favorably improved; if the annealing temperature is higher than 1050 ℃, the doped ions diffuse too fast, which is not favorable for controlling the doped ions.

In the annealing process, there are no high-energy ions, so that the doped ions enter the second fin portion 205 by annealing, which can effectively avoid the damage to the fin portion structure by ion implantation, and is beneficial to improving the performance of the semiconductor device.

Referring to fig. 9, after the lightly doped region is formed, the doped layer 212 is removed.

The process of removing the doped layer 211 includes: one or two of the dry etching process and the wet etching process are combined.

the doped layer 212 is removed to expose the sidewall and the bottom surface of the first opening 211, which is beneficial for the subsequent formation of a second opening.

Referring to fig. 10, after the doped layer 212 is removed, the exposed portions of the first fins 204 of the first openings 211 (see fig. 9) are removed, and second openings 250 are formed between adjacent second fins 205.

In other embodiments, after removing the doping layer, a portion of the first fin exposed by the first opening is not removed.

The process of removing the portion of the first fin 204 exposed by the first opening 211 includes: one or two of the wet etching process and the dry etching process are combined.

The significance of removing the exposed portion of the first fin 204 of the first opening 211 is: the second opening 250 is larger in size along the extending direction of the fin structure, the second opening 250 is used for subsequently accommodating an insulating layer, the insulating layer is larger in size along the extending direction of the fin structure, and the subsequent source/drain doped region is further away from the channel, so that the parasitic capacitance between the source/drain doped region and the channel is favorably reduced, and the performance of the semiconductor device is improved. In the extending direction of the fin structure, the size of the second opening 250 is smaller than or equal to the size of the sidewall structure 208, which is beneficial to preventing doped ions from being connected in series.

Referring to fig. 11, an insulating layer 213 is formed in the second opening 250, and the insulating layer 213 fills the second opening 250.

The method for forming the insulating layer 213 includes: forming insulating material films on the surface of the isolation structure 206, the side wall and the bottom surface of the source-drain opening 210, in the second opening, and on the side wall and the top surface of the dummy gate structure; and removing the surface of the isolation structure 206, the side walls and the bottom surfaces of the source and drain openings 210, and the side walls and the top surfaces of the gate structures to form an insulating material film, and forming the insulating layer 213 in the second openings.

the material of the insulating material film comprises silicon nitride, silicon oxycarbide or silicon oxynitride. The forming process of the insulating material film comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

The process for removing the surface of the isolation structure 206, the sidewall and the bottom surface of the source-drain opening 210, and the sidewall and the top surface of the gate structure to form the insulating material film comprises the following steps: one or two of the dry etching process and the wet etching process are combined.

The dimension of the insulating layer 213 along the extending direction of the fin structure is: 2 nm to 5 nm, the dimension of the insulating layer 213 in the extending direction of the fin structure is large, so that the distance between a subsequently formed source-drain doped region and a channel region is long, the parasitic capacitance between the source-drain doped region and the channel is small, and the performance of a semiconductor device is improved.

Referring to fig. 12, after the insulating layer 213 is formed, a source/drain doped region 214 is formed in the source/drain opening 210 (see fig. 11).

The method for forming the source-drain doped region 214 includes: forming an epitaxial layer in the source-drain opening 210; and doping source and drain ions into the epitaxial layer to form a source and drain doped region 214.

The material of the epitaxial layer and the conductivity type of the source and drain ions are related to the type of the transistor. In this embodiment, the transistor is an NMOS transistor, the material of the epitaxial layer includes silicon carbide or silicon, and the source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions. In other embodiments, the transistor is a PMOS transistor, the material of the epitaxial layer includes silicon germanium or silicon, and the source and drain ions are P-type ions, such as: boron ions.

The epitaxial layer forming process comprises an epitaxial growth process.

After the source-drain doped region 214 is formed, the forming method further includes: forming dielectric layers on the top surface of the isolation structure 206, the side wall and the top surface of the source-drain doped region 214, and the side wall and the top surface of the dummy gate structure, wherein the top of the dielectric layers is exposed out of the top surface of the dummy gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; after the dummy gate opening is formed, removing the first fin portion 204 to suspend the second fin portion 205; after removing the first fin 204, a gate structure surrounding the second fin 205 is formed.

Accordingly, the present invention further provides a semiconductor structure, please refer to fig. 8, which includes:

A substrate 203;

A dummy gate structure on the substrate 203;

A fin structure is arranged on the surface of the substrate 203, the dummy gate structure crosses the fin structure, the fin structure comprises a doped region B along the height direction of the fin structure, the fin structure in the doped region B comprises a plurality of stacked fin units, the fin unit comprises a first fin 204 and a second fin 205 arranged on the top of the first fin 204, the first fin 204 and the second fin 205 are made of different materials, the sidewall of the first fin 204 is recessed towards the dummy gate structure relative to the sidewall of the second fin 205, and a first opening 211 is arranged between every two adjacent fins 205 (see fig. 7);

The source-drain openings 210 are positioned in the fin part structures of the doping regions B on two sides of the pseudo gate structure;

A doped layer 212 located in the first opening 211, wherein the doped layer 212 has doped ions therein.

When the formed device is an NMOS transistor, the doped ions are N-type ions.

when the formed device is a PMOS transistor, the doped ions are P-type ions.

The material of the doped layer 212 comprises silicon; the doping concentration of the doping ions is 1.0E20 atomic number/cubic centimeter to 5.0E22 atomic number/cubic centimeter.

The side wall of the pseudo gate structure is provided with a side wall structure 208; in the extending direction of the fin structure, the size of the first opening 211 is smaller than or equal to the size of the sidewall structure 208; along the extending direction of the fin structure, the size of the first opening 211 is: 1 to 2 nanometers.

The fin structure further comprises an isolation region A located at the bottom of the doped region B along the height direction of the fin structure; the semiconductor structure further comprises an isolation structure 206 located on the surface of the substrate 203, wherein the top of the isolation structure 206 is lower than the top of the fin structure and covers all or part of the sidewalls of the fin structure in the isolation region a.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.